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Generation of Sawtooth Wave Using Verilog: Abhaya Kotnala

This document describes generating sawtooth waves using Verilog code. It defines a counter module that takes a clock signal as input and outputs a counter register. The counter increments by 1 each clock cycle until it reaches either 499 for a 200 kHz sawtooth wave, or 999 for a 100 kHz wave, then resets to 0. The code is simulated and generates the desired sawtooth waves as seen in the results figures, successfully implementing sawtooth wave generation.

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Abhay Kotnala
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0% found this document useful (0 votes)
46 views2 pages

Generation of Sawtooth Wave Using Verilog: Abhaya Kotnala

This document describes generating sawtooth waves using Verilog code. It defines a counter module that takes a clock signal as input and outputs a counter register. The counter increments by 1 each clock cycle until it reaches either 499 for a 200 kHz sawtooth wave, or 999 for a 100 kHz wave, then resets to 0. The code is simulated and generates the desired sawtooth waves as seen in the results figures, successfully implementing sawtooth wave generation.

Uploaded by

Abhay Kotnala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Generation of Sawtooth wave using Verilog

Abhaya Kotnala
SCEE
IIT Mandi
Himachal Pradesh, India
T21082@[Link]

I. A IM (
499 for dividing the clock by 500
• To generate a Sawtooth wave of 200 kHz for a given K= (1)
999 for dividing the clock by 1000
oscillator of frequency 100 MHz.
III. R ESULTS
• To generate a Sawtooth wave of 200 kHz for a given
oscillator of frequency 100 MHz. A. Verilog Code
1) For 200 kHz:

II. F LOW C HART module counter(clk , counter);


input clk;
Start output reg[8:0] counter = 0;
always @ (posedge clk)
if (counter < 499)
Define Module counter = counter +1 ;
Counter else
counter = 0;
endmodule
Define Input
Clock with 2) For 100 kHz:
frequency 100MHz module counter(clk , counter);
input clk;
Define output output reg[9:0] counter = 0;
register Counter and always @ (posedge clk)
assign value = 0 if (counter < 999)
counter = counter +1 ;
else
ounter = 0;
endmodule

B. Simulation
is Counter = K?
1) For 200 kHz: Verilog code is simulated using
the software “Modelsim PE Student Edition”. Fig. 2.
Simulation result showing the generated sawtooth signal
Yes No Increment and clock signals period of generated sawtooth waveform
Assign Counter = 0 is [Link] the frequency of generated wave is
counter by 1
1/5us = 200000 Hz = 200kHz.

End Module 2) For 100 kHz: Verilog code is simulated using the soft-
ware “Modelsim PE Student Edition”.The code is simulated
Stop for a period of 1 millisecond. It can be seen from the result
that the time Fig. 2. Simulation result showing the generated
Clock f requency
Where “K” = Required f requency of Sawtooth wave sawtooth signal and clock signals
999 and resets when it reaches 0.
IV. C ONCLUSION
The verliog code for generation of sawtooth wave was
simulated. The clock signal of 100Mhz frequency is given
as an input and a sawtooth wave of 200kHz and 100 kHZ
frequency is obtained. Hence, the generation of sawtooth wave
was implemented successfully.

Fig. 1. Simulation result showing the generated sawtooth signal (f = 200


KHz)and clock signals

Fig. 2. Simulation result showing the generated sawtooth signal (f = 100KHz)


and clock signals

C. Analysis
1) For 200KHz: Given frequency of clock is 100 Mhz
Hence the time period of the clock is 10ns. The sawtooth
wave could be generated with the help of a down counter.
Required frequency of the sawtooth wave = 200kHz. Hence,
the number of counts to be counted by the counter before
reset = 100MHz/200khz = 500 counts. Hence the counter
starts at 499 and resets when it reaches 0.

2) For 100KHz: Given frequency of clock is 100 Mhz


Hence the time period of the clock is 10ns. The sawtooth
wave could be generated with the help of a down counter.
Required frequency of the sawtooth wave = 100kHz. Hence,
the number of counts to be counted by the counter before reset
= 100MHz/100khz = 1000 counts. Hence the counter starts at

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