L4984

CCM PFC controller

Datasheet — preliminary data

Features
■ Line-modulated fixed-off-time (LM-FOT)
control of CCM-operated PFC pre-regulators
■ Proprietary LM-FOT modulator for nearly fixed-
frequency operation
■ Proprietary multiplier design for minimum THD
of AC input current
■ Fast “bi-directional” input voltage feedforward
(1/V2 correction) SSOP10
■ Accurate adjustable output overvoltage
protection
■ Protection against feedback loop failure
(latched shutdown)
Table 1. Device summary
■ Inductor saturation protection
Order code Package Packaging
■ AC brownout detection
■ Digital leading-edge blanking on current sense L4984D Tube
SSOP10
■ Soft-start L4984DTR Tape and reel

■ 1% (at Tj = 25 °C) internal reference voltage

■ - 600 / + 800 mA totem pole gate driver with
active pull-down during UVLO and voltage
clamp
■ SSOP10 package

Applications
■ PFC pre-regulators for:
– IEC61000-3-2 and JEIDA-MITI compliant
SMPS in excess of 1 KW
– Desktop PC, server, web server

August 2012 Doc ID 023489 Rev 1 1/35

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com 35
change without notice.

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Contents L4984

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Feedback failure detection (FFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

12 Power management and housekeeping functions . . . . . . . . . . . . . . . . 30

13 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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L4984 List of figures

List of figures

Figure 1. Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. IC consumption vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. IC consumption vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. VCC Zener voltage vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Startup & UVLO vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Feedback reference vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. E/A output clamp levels vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. UVLO saturation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. OVP levels vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Inductor saturation threshold vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Vcs clamp vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Timer pin charging current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Brownout threshold (on VFF) vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. RFF discharge vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Line drop detection threshold vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. VMULTpk - VVFF dropout vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. PFC_OK enable threshold vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. FFD threshold vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20. Multiplier characteristics at VFF=1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Multiplier characteristics at VFF=3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Multiplier gain vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Gate drive clamp vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Gate drive output saturation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Delay to output vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Line-modulated fixed-off-time modulator: a) internal block diagram; b) key waveforms. . . 17
Figure 27. Typical frequency change along a line half-cycle in a boost PFC operated in LM-FOT
(left) and TM (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. Line-modulated fixed-off-time-controlled boost PFC: current waveforms . . . . . . . . . . . . . . 19
Figure 29. Line-modulated fixed-off-time-controlled boost PFC: input current harmonic contents . . . 20
Figure 30. Output voltage setting, OVP and FFD functions: internal block diagram . . . . . . . . . . . . . . 21
Figure 31. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic . . . 23
Figure 32. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . . 25
Figure 33. Effect of boost inductor saturation on MOSFET current and detection method . . . . . . . . . 27
Figure 34. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 35. HD optimization: standard PFC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. Interface circuits that let DC-DC converter controller IC disable the L4984 . . . . . . . . . . . . 30
Figure 37. SSO10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Description L4984

1 Description

The L4984 is a current-mode PFC controller operating with line-modulated fixed-off-time

(LM-FOT) control. A proprietary LM-FOT modulator allows fixed-frequency operation for
boost PFC converters as long as they are operated in CCM (continuous conduction mode).
The chip comes in a 10-pin SO package and offers a low-cost solution for CCM-operated
boost PFC pre-regulators in EN61000-3-2 and JEIDA-MITI compliant applications, in a
power range that spans from few hundred W to 1 KW and above.
The highly linear multiplier includes a special circuit, able to reduce the crossover distortion
of the AC input current, that allows wide-range-mains operation with a reasonably low THD,
even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and an accurate
(1% at Tj = 25 °C) internal voltage reference. Loop stability is optimized by the voltage
feedforward function (1/V2 correction), which in this IC uses a proprietary technique that
also significantly improves line transient response in the case of mains drops and surges
(“bi-directional”).
The device features low consumption and includes a disable function suitable for IC remote
on/off. These features allow use in applications which also comply with the latest energy
saving requirements (Blue Angel, ENERGY STAR®, Energy2000, etc.).
In addition to overvoltage protection able to keep the output voltage under control during
transient conditions, the IC is also provided with protection against feedback loop failures or
erroneous settings. Other onboard protection functions allow that brownout conditions and
boost inductor saturation can be safely handled. Soft-start limits peak current and extends
off-time to prevent flux runaway in the initial cycles.
The totem pole output stage, capable of 600 mA source and 800 mA sink current, is suitable
for big MOSFETs or IGBT drive.

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 2
L4984

TIMER Vcc
Figure 1.

7 10
Voltage
references VOLTAGE
0.23 V UVLO
REGULATOR

…
+ Disable
0.27 V
6
- Internal Supply Bus
UVLO
2.5 V -
2.4 V OVP L_OVP
Block diagram

LM-FOT 9
+ MODULATOR S Q1
Stop GD
1.66 V + R
DRIVER
Electrical diagram

- & CLAMP

2
COMP DISABLE

Disable

Doc ID 023489 Rev 1

Q S L_OVP
Q1 LEB OVP
INV - Brownout
1 R UVLO
2.5 V + Error Amplifier

MULT
3 Ideal rectifier
- + GND
8
-
1/V2 MULTIPLIER
+
CS

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0.88 V 4
+ 0.8 V
Brownout + 300 us Stop
0.88 V
- MAINS DROP 1.7 V
- Monostable
DETECTOR

VFF

AM13217v1
Block diagram

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Block diagram L4984

Table 2. Absolute maximum ratings

Symbol Pin Parameter Value Unit

VCC 10 IC supply voltage (Icc = 20 mA) Self-limited V

- 1, 3, 6 Max. pin voltage (Ipin = 1 mA) Self-limited V
- 2, 4, 5, 7 Analog inputs & outputs -0.3 to 8 V
VFF pin 5 Maximum withstanding voltage range +/- 1500 V
test condition: CDF-AEC-Q100-002 “human
1 to 4 body model”
Other pins +/- 2000 V
6 to 10 Acceptance criteria: “normal performance”

Figure 2. Pin connection (top view)

INV 1 10 Vcc
COMP 2 9 GD
MULT 3 8 GND
CS 4 7 TIMER
VFF 5 6 PFC_OK
AM13218v1

Table 3. Thermal data

Symbol Parameter Value Unit

Rth j-amb Max. thermal resistance, junction-to-ambient 120 °C/W

Ptot Power dissipation at Tamb = 50 °C 0.75 W
Tj Junction temperature operating range -40 to 150 °C
Tstg Storage temperature -55 to 150 °C

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L4984 Block diagram

Table 4. Pin functions

N. Name Function

Inverting input of the error amplifier. The information on the output voltage of
1 INV the PFC pre-regulator is fed into the pin through a resistor divider. The pin
normally features high impedance.
Output of the error amplifier. A compensation network is placed between this
pin and INV (pin 1) to achieve stability of the voltage control loop and ensure
2 COMP high power factor and low THD. To avoid uncontrolled rise of the output
voltage at zero load, when the voltage on the pin falls below 2.4 V the gate
driver output is inhibited (burst-mode operation).
Main input to the multiplier. This pin is connected to the rectified mains
voltage via a resistor divider and provides the sinusoidal reference to the
3 MULT
current loop. The voltage on this pin is used also to derive the information on
the RMS mains voltage. At startup this pin is used also to perform soft-start.
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor; the resulting voltage is applied to this pin and compared to
an internal sinusoidal-shaped reference, generated by the multiplier, to
determine the turn-off instant of the external Power MOSFET. The pin is
4 CS equipped with about 220 ns digital leading-edge blanking for improved noise
immunity. A second comparison level set at 1.7 V detects abnormal currents
(e.g. due to boost inductor saturation) and, on this occurrence, activates a
safety procedure that temporarily stops the converter and limits the stress of
the power components.
Second input to the multiplier for 1/V2 function. A capacitor and a parallel
resistor must be connected from the pin to GND. They complete the internal
peak-holding circuit that derives the information on the RMS mains voltage.
The resistor should range from 100 kΩ (minimum) to 2 MΩ (maximum). The
voltage on this pin, a DC level equal to the peak voltage on pin MULT (3),
5 VFF compensates the control loop gain dependence on the mains voltage. This
pin is also internally connected to a comparator in order to provide brownout
(AC mains undervoltage) protection. A voltage below 0.8 V shuts down (not
latched) the IC and brings its consumption to a considerably lower level. The
IC restarts as the voltage at the pin goes above 0.88 V. Never connect the pin
directly to GND.
PFC pre-regulator output voltage monitoring/disable function. This pin
senses the output voltage of the PFC pre-regulator through a resistor divider
and is used for protection purposes. If the voltage on the pin exceeds 2.5 V,
the IC stops switching and restarts as the voltage falls below 2.4 V. However,
6 PFC_OK if at the same time the voltage on the INV pin falls below 1.66 V, a feedback
failure is assumed. In this case the device is latched off. Normal operation
can be resumed only by cycling VCC. If the voltage on this pin is brought
below 0.23 V, the IC is shut down. To restart the IC the voltage on the pin
must go above 0.27 V. This can be used as a remote on/off control input.
LM-FOT modulator setting. A capacitor connected between this pin and
ground is charged by an accurate internal generator during the off-time of the
external Power MOSFET (i.e. while pin GD is low), therefore generating a
7 TIMER
voltage ramp. As the voltage ramp equals the voltage on the MULT pin, the
off-time of the Power MOSFET is terminated, the GD pin is driven high and
the ramp is reset at zero.

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Block diagram L4984

Table 4. Pin functions (continued)

N. Name Function

Ground. Current return for both the signal part of the IC and the gate driver.
Keep the PCB trace that goes from this pin to the “cold” end of the sense
8 GND resistor separate from the trace that collects the grounding of the bias
components (output voltage sensing divider, multiplier bias divider and LM-
FOT modulator setting).
Gate driver output. The totem pole output stage is able to drive Power
MOSFETs and IGBTs. It is capable of 600 mA source current and 800 mA
9 GD sink current (minimum values). The high-level voltage of this pin is clamped
at about 12 V to avoid excessive gate voltages in case the pin is supplied with
a high VCC.
Supply voltage of both the signal part of the IC and the gate driver.
Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful in
10 VCC order to get a clean bias voltage for the signal part of the IC. The voltage on
the pin is internally clamped at 22.5 V min. to protect the internal circuits from
excessive supply voltages.

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L4984 Electrical characteristics

3 Electrical characteristics

(Tj = -25 to 125 °C, VCC = 12 V,(a) CTIMER = 470 pF, Co = 1 nF between pin GD and GND,
CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified.)

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply voltage
VCC Operating range After turn-on 10.3 22.5 V
VCCOn (1)
Turn-on threshold 11 12 13 V
VCCOff (1)
Turn-off threshold 8.7 9.5 10.3 V
VCCrestart VCC for resuming from latch OVP latched 5 6 7 V
Hys Hysteresis 2.3 2.7 V
VZ Zener voltage Icc = 20 mA 22.5 25 28 V
Supply current
Istart-up Startup current Before turn-on, VCC = 10 V 65 150 µA
Iq Quiescent current After turn-on, VMULT = 1 V 4 5 mA
ICC Operating supply current At 70 kHz 5 6.0 mA
VPFC_OK > VPFC_OK_S
and 200 280 µA
Iqdis Idle state quiescent current VINV < VINVD
VPFC_OK < VPFC_OK_D 1.5 2.2 mA
VPFC_OK > VPFC_OK_S
Iq Quiescent current or 2.2 3 mA
VCOMP < 2.3 V
Multiplier input
IMULT Input bias current VMULT = 0 to 3 V -0.2 -1 µA
VMULT Linear operation range 0 to 3 V
VCLAMP Internal clamp level IMULT = 1 mA 9 9.5 V

VMULT = 0 to 0.4 V
ΔV CS Output max. slope VVFF = 0.915 V 0.935 1.34 V/V
---------------------
-
ΔV MULT VCOMP = upper clamp

VMULT = VCOMP = 0.915 V

KM Gain(2) 0.248 0.304 0.360 V
VCOMP = 4 V
Error amplifier

Voltage feedback input Tj = 25 °C 2.475 2.5 2.525 V

VINV
threshold 10.3 V < VCC < 22.5 V (1) 2.455 2.545

a. Adjust VCC above VCCOn before setting at 12 V.

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Electrical characteristics L4984

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Line regulation VCC = 10.3 V to 22.5 V 2 5 mV

IINV Input bias current VINV = 0 to 4 V -0.2 -1 µA
VINVCLAMP Internal clamp level IINV = 1 mA 8 9 V
Gv Voltage gain Open loop 60 80 dB
GB Gain-bandwidth product 1 MHz
Source current VCOMP = 4 V, VINV = 2.4 V 2 4 mA
ICOMP
Sink current VCOMP = 4 V, VINV = 2.6 V 2.5 4.5 mA
Upper clamp voltage ISOURCE = 0.5 mA 5.7 6.2 6.7 V
VCOMP Burst-mode threshold (1)
2.3 2.4 2.5
Lower clamp voltage ISINK = 0.5 mA (3) 2.1 2.25 2.4
Current sense comparator
ICS Input bias current VCS = 0 1 µA
tLEB Leading edge blanking 145 220 400 ns
td(H-L) Delay to output 100 200 300 ns
VCOMP = upper clamp
VCSclamp Current sense reference clamp 0.84 0.88 0.93 V
VMULT = VVFF = 0.915 V (1)
VMULT = 0, VVFF = 3 V 35 47 mV
Vcsofst Current sense offset (2)
VMULT = 3 V, VVFF = 3 V 10
Boost inductor saturation detector
VCS_th (1)
Threshold on current sense 1.6 1.7 1.8 V
IINV E/A input pull-up current VCS > VCS_th, before restart 5 10 13 µA
tSTART Restart delay 300 µs
Pfc_ok functions
IPFC_OK Input bias current VPFC_OK = 0 to 2.6 V -0.1 -1 µA
VPFC_OK_C Clamp voltage IPFC_OK = 1 mA 9 9.5 V
(1)
VPFC_OK_S OVP threshold Voltage rising 2.435 2.5 2.565 V
VPFC_OK_R (1)
Restart threshold after OVP Voltage falling 2.34 2.4 2.46 V
VPFC_OK_D (1)
Disable threshold Voltage falling 0.12 0.23 0.35 V
VPFC_OK_E (1)
Enable threshold Voltage rising 0.15 0.27 0.38 V
Feedback failure detection
(1)
Feedback failure detection Voltage falling,
VINVD 1.61 1.66 1.71 V
threshold (on VINV) VPFC_OK = VPFC_OK_S
Voltage feedforward
VVFF Linear operation range 1 3 V

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L4984 Electrical characteristics

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Before turn-on 800 mV

ΔV Dropout VMULTpk-VVFF
After turn-on 20
ΔVVFF Line drop detection threshold Below peak value 40 70 100 mV
ΔVVFF Line drop detection threshold Below peak value Tj = 25 °C 60 70 90 mV
RDISCH Internal discharge resistor 5 10 20 kΩ
VDIS (1)
Disable threshold Voltage falling 0.745 0.8 0.855 V
VEN (1)
Enable threshold Voltage rising 0.845 0.88 0.915 V
Fixed-off-time modulator
ITIMER Programming current VMULT = 1 V 148 156 163 µA
TOFF Programmed off-time VMULT = 1 V 2.88 3 3.18 µs
RDIS Discharge resistance 35 60 120 Ω
CTIMER Timing capacitor range 0.1 2.2 nF
TOFF_pk Programming range On the peak of VMULT 1.45 50 µs
Soft-start
TSS Activation time 300 µs
VMULTx Pull-up voltage 10 kΩ from MULT to GND 4.1 V
Gate driver
VOL Output low voltage Isink = 100 mA 0.6 1.2 V
VOH Output high voltage Isource = 5 mA 9.8 10.3 V
Isrcpk Peak source current -0.6 A
Isnkpk Peak sink current 0.8 A
tf Voltage fall time 30 60 ns
tr Voltage rise time 45 110 ns
VOclamp Output clamp voltage Isource = 5 mA; Vcc = 20 V 10 12 15 V
UVLO saturation VCC = 0 to VCCon, Isink = 2 mA 1.1 V
1. Parameters tracking each other.
2. The multiplier output is given by:

VMULT VCOMP 2.5

Vcs VCS_Ofst K M 2
VVFF

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Typical electrical performance L4984

4 Typical electrical performance

Figure 3. IC consumption vs. VCC Figure 4. IC consumption vs. Tj

100 10
Operating

10 Quiescent

Disabled or
1 during OVP
VCC=12V
1

Ic current (mA)
Co = 1nF
Co=1nF f =70kHz
Icc [mA]

f =70kHz
Tj = 25 C
Latched off
0.1
0.1

0.01 Before Start up

VccOFF
VccON

0.001 0.01
0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 150 175
Vcc [V] AM13219v1 Tj (C) AM13220v1

Figure 5. VCC Zener voltage vs. Tj Figure 6. Startup & UVLO vs. Tj

28 13

27 12 VCC-ON

11
26

10
VCC-OFF
25
V
V

24
8

23 7

6
22
-50 -25 0 25 50 75 100 125 150 175
-50 -25 0 25 50 75 100 125 150 175
Tj (C) AM13221v1 Tj (C) AM13222v1

Figure 7. Feedback reference vs. Tj Figure 8. E/A output clamp levels vs. Tj

2.6 7
Uper Clamp

6
VCC = 12V

2.55
5
VCC = 12V
VCOMP (V)

4
pin INV (V)

2.5
3
Lower Clamp

2
2.45

0
2.4 -50 -25 0 25 50 75 100 125 150 175
-50 -25 0 25 50 75 100 125 150 175
Tj (C)
Tj (C) AM13223v1 AM13224v1

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L4984 Typical electrical performance

Figure 9. UVLO saturation vs. Tj Figure 10. OVP levels vs. Tj

1 2.5

0.9
VCC = 0V 2.48
0.8 OVP Th
2.46
0.7

PFC_OK levels (V)

0.6 2.44

0.5
V

2.42
0.4

2.4
0.3
Restart Th
0.2 2.38

0.1
2.36
0 -50 -25 0 25 50 75 100 125 150 175
-50 -25 0 25 50 75 100 125 150 175 Tj (C)
Tj (C) AM13225v1 AM13226v1

Figure 11. Inductor saturation threshold vs. Tj Figure 12. Vcs clamp vs. Tj
0.9

1.9

VCC = V
1.8 0.89 VCOMP = Upper Clamp

1.7

1.6 0.88
Vcs clamp (V)
CS pin (V)

1.5

0.87
1.4

1.3

0.86
1.2

1.1
-50 -25 0 25 50 75 100 125 150 175 0.85
Tj (C) -50 -25 0 25 50 75 100 125 150 175
AM13227v1 Tj (C) AM13228v1

Figure 13. Timer pin charging current vs. Tj Figure 14. Brownout threshold (on VFF) vs. Tj
200

1
190

180
0.9 Enable

170

0.8
160
I TMER (uA)

Disable
150
0.7
V

140

0.6
130

120
0.5

110

100 0.4
-50 -25 0 25 50 75 100 125 150 175
-50 -25 0 25 50 75 100 125 150 175
Tj (C) AM13230v1
Tj (C) AM13229v1

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Typical electrical performance L4984

Figure 15. RFF discharge vs. Tj Figure 16. Line drop detection threshold vs. Tj

20 90

18 80

16
70

14
60
12
50
kOhm

mV
10
40
8
30
6

20
4

2 10

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tj (C) Tj (C)
AM13231v1 AM13232v1

Figure 17. VMULTpk - VVFF dropout vs. Tj Figure 18. PFC_OK enable threshold vs. Tj

2 0.4

1.5 0.35

1 0.3

0.5 0.25

ON
D (mV)

Th (V)

0 0.2

-0.5 0.15 OFF

-1 0.1

-1.5 0.05

-2 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tj (C) Tj (C)
AM13233v1 AM13234v1

Figure 19. FFD threshold vs. Tj

1.9

1.8
VINVD (V)

1.7

1.6

1.5

1.4
-50 -25 0 25 50 75 100 125 150 175
Tj(C) AM13235v1

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L4984 Typical electrical performance

Figure 20. Multiplier characteristics at VFF=1 V Figure 21. Multiplier characteristics at VFF=3 V
1.2 500
VCOMP VCOMP
1.1
450
VFF = 3 V
1.0
400
Upper voltage clamp
0.9 Upper voltage clamp
5.5 V
350
0.8
5.0 V 5.5 V
300
0.7

VCS (mV)
4.5 V
VCS (V)

5.0 V
0.6 250

0.5 4.0 V 4.5 V

200

0.4 4.0 V
3.5 V 150
0.3
3.5 V
100
0.2 3.0 V

50 3.0 V
0.1
2.6 V
2.6 V
0.0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 0.5 1 1.5 2 2.5 3 3.5

VMULT (V) AM13236v1 VMULT (V) AM13237v1

Figure 22. Multiplier gain vs. Tj Figure 23. Gate drive clamp vs. Tj
Multiplier Gain vs. Tj
12.9
0.5
VCC = 20V

12.85

0.4
12.8
Gain (1/V)

VCC = 12V
VCOMP = 4V
V

VMULT = VFF = 1V

12.75
0.3

12.7

0.2
12.65
-50 -25 0 25 50 75 100 125 150 175
-50 -25 0 25 50 75 100 125 150 175
Tj (C) Tj (C)
AM13238v1 AM13239v1

Figure 24. Gate drive output saturation vs. Tj Figure 25. Delay to output vs. Tj

12 300

High level
10
250

200
TD(H-L) (ns)

6 VCC = 12V
V

150

100
2 Low level

0 50
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tj (C) Tj (C)
AM13240v1 AM13241v1

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Application information L4984

5 Application information

5.1 Theory of operation

The L4984 implements conventional “peak” current mode control, where the on-time TON of
the external power switch is determined by the peak inductor current reaching the
programmed value. The off-time TOFF, instead, is determined by a special fixed-off-time
(FOT) modulator in such a way that the resulting switching period is constant as long as the
boost converter is operated in CCM (i.e. the current in the boost inductor remains greater
than zero in a switching cycle).
To understand how TOFF needs to be modulated to achieve a fixed switching frequency
independent of the instantaneous line voltage and the load, it is useful to consider the V·s
balance equation for the boost inductor under the assumption of CCM operation:

Equation 1

TON Vpk sinθ = TOFF ( Vout − Vpk sinθ)

where Vpk is the peak line voltage, Vout the regulated output voltage and θ the
instantaneous phase angle of the line voltage. Solving for TON, we get:

Equation 2
⎛ Vout ⎞
TON = ⎜⎜ − 1⎟⎟ TOFF
⎝ Vpk sinθ ⎠
then, the switching period TSW is:

Equation 3
⎛ Vout ⎞ Vout
Tsw = TON + TOFF = ⎜⎜ − 1⎟⎟ TOFF + TOFF = TOFF
⎝ Vpk sin θ ⎠ Vpk sin θ
In the end, if TOFF is changed proportionally to the instantaneous line voltage, i.e. if:

Equation 4

TOFF = K t Vpk sin θ

then TSW is equal to Kt·Vout and, since Vout is regulated by the voltage loop, also TSW (and
fSW = 1/TSW) is fixed. This result is based on the sole assumption that the instantaneous line
voltage and the output load are such that the boost inductor operates in CCM.

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L4984 Application information

Figure 26. Line-modulated fixed-off-time modulator: a) internal block diagram; b)

key waveforms
TIMER MULT

0
COMP MULT CS TOFF TON t
S
PWM
+ Comparator

- t
Multiplier R

- t
Q
ITimer S Q
+
GD
TIMER Driver
R
t
ON
PWM Latch GD
OFF
CT
t
Multiplier output
CS

a) b)
AM13242v1

With reference to the schematic and the relevant key waveforms in Figure 26, an off-time
proportional to the instantaneous line voltage is achieved by charging the capacitor CT with
a constant current ITIMER, accurately fixed internally and temperature compensated, while
the MOSFET is off and commanding MOSFET turn-on (and resetting CT at zero) as the
voltage across CT equals that on the MULT pin. The voltage on this pin is:

Equation 5

VMULT = K P Vpk sin θ

where KP is the divider ratio of the resistors biasing the MULT pin. As a result:

Equation 6
CT CT
TOFF = K P Vpk sinθ → Kt = KP
ITIMER ITIMER

and the switching frequency is:

Equation 7
1 ITIMER 1
fsw = = =
Tsw K P C T Vout K t Vout

The timing capacitor CT, therefore, is selected with the following design formula:

Equation 8
ITIMER
CT =
K P Vout fsw

Vout and fsw are design specifications, KP is chosen so that the voltage on the MULT pin is
within the multiplier linearity range (0 to 3 V) and ITIMER is specified in Section 3: Electrical
characteristics.

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Application information L4984

Along a line half-cycle, TOFF goes all the way from a minimum near the zero-crossing to a
maximum on the sinusoid peak. It is important to check that the off-time occurring on the
peak of the voltage sinusoid at minimum input voltage is greater then the minimum
programmable value:

Equation 9
CT
TOFF min = K P Vpk min > 1.45 μs
ITIMER
This constraint limits the maximum programmable frequency at:

Equation 10
Vpk min
fsw. max = 690 [kHz]
Vout
As the line RMS voltage is increased and/or the output load is decreased, the boost inductor
current tends to become discontinuous starting from the region around the zero-crossings.
As a result, the switching frequency is no longer constant and tends to increase. However,
the frequency rise is significantly lower as compared to that in a transition-mode (TM)
operated boost PFC stage, as illustrated in Figure 25. The switching frequency can exceed
fsw.max in the region where the inductor current is discontinuous.

Figure 27. Typical frequency change along a line half-cycle in a boost PFC operated
in LM-FOT (left) and TM (right)
LM -FOT operated PFC Transition -mode operated PFC
1.6 9

Vin = 264 Vac Vin = 230 Vac

8
1.4
Normalized switching frequency

Vin = 230 Vac 7

Normalized switching frequency

1.2 6

1
4
Vin = 88 Vac Vin = 115 Vac
0.8 3
Vin = 115 Vac
Vin = 88 Vac
2
0.6
1
Vin = 264 Vac
0.4 0
0 0.52 1.05 1.57 2.09 2.62 3.14 0 0.52 1.05 1.57 2.09 2.62 3.14

Line voltage phase angle (rad) Line voltage phase angle (rad)
AM13243v1

In this example the voltage ripple appearing across the output capacitor Cout has been
neglected. This ripple at twice the line frequency fL has peak amplitude ΔVout proportional
to the output current Iout:

Equation 11
Iout
ΔVout =
4 π fL Cout

As a consequence, fsw is not exactly constant but is modulated at 2fL, which spreads the
spectrum of the electrical noise injected back into the power line and facilitates the

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L4984 Application information

compliance with conducted EMI emission regulations. The relative frequency change due to
the output voltage ripple is:

Equation 12
ΔVout
Δfsw Vout
=
fsw ΔVout
1+
Vout

Figure 28. Line-modulated fixed-off-time-controlled boost PFC: current waveforms

Boost inductor
Vin = 88 Vac Line current current envelope
Vin = 88 Vac

Vin = 190 Vac

Vin = 264 Vac Vin = 264 Vac

Line current (A)

Vin = 230 Vac

Inductor current (A)

Line voltage phase angle (rad) Line voltage phase angle (rad)
AM13244v1

As a result of the operation of the circuit in Figure 26, the current that the boost PFC pre-
regulator draws from the power line is not exactly sinusoidal but is affected by distortion that
is lower as the current ripple in the boost inductor is smaller as compared to its peak value.
Figure 28 shows some theoretical waveforms, relevant to full load condition, in a line cycle
at different input voltages.
In the diagram on the left-hand side the line (input) current waveform is shown for different
line voltages, while on the right-hand side the envelope of the inductor current at minimum
and maximum line voltage is shown.
The input current waveform relevant to Vin = 88 Vac shows no visible sign of distortion; the
operation of the boost inductor is CCM throughout the entire line cycle as testified by the
inductor current envelope. The brown waveform is relevant to Vin = 190 Vac, which is the
condition where CCM operation no longer occurs at zero-crossings (this voltage value, for a
given power level, depends on the inductance value of the boost inductor); a certain degree
of distortion is already visible.

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Application information L4984

Figure 29. Line-modulated fixed-off-time-controlled boost PFC: input current

harmonic contents

(normalized to fundamental)
% Harmonic amplitude
Vin = 264Vac
THD = 17.7%

Harmonic order (n) AM13245v1

The waveform relevant to Vin = 264 Vac shows the highest degree of distortion and the
largest portion of the line cycle where boost inductor operates in discontinuous mode
(DCM). However, its harmonic content, shown in Figure 29, is still so low that it is not an
issue for EMC compliance. Almost all the distortion is concentrated in the third harmonic,
whose amplitude is 17% of the fundamental one, while the THD is 17.7%.

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L4984 Overvoltage protection (OVP)

6 Overvoltage protection (OVP)

Normally, the voltage control loop keeps the output voltage Vout of the PFC pre-regulator
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A
pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a
separate resistor divider (R3 high, R4 low, see Figure 30). This divider is selected so that
the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually
larger than the maximum Vout that can be expected.

Figure 30. Output voltage setting, OVP and FFD functions: internal block diagram
Vout

R3a
R3 L4984
R3b
0.23 V + Disable
0.27 V
6
-
2.5 V
PFC_OK 2.4 V
- OVP L_OVP
R1a
+
R1
R1b 1.66 V +
-
COMP
Frequency 2
compensation

-
1
INV 2.5 V + Error Amplifier
R4 R2

AM13246v1

Note: Example: Vout = 400 V, Voutx = 434 V.

Select: R3 = 8.8 M; then: R4 = 8.8 M ·2.5/(434-2.5) = 51 k.
When this function is triggered, the gate drive activity is immediately stopped until the
voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be
selected without any constraints. The unique criterion is that both dividers must sink a
current from the output bus which needs to be significantly higher than the bias current of
both pins INV and PFC_OK (< 1 μA).

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Feedback failure detection (FFD) L4984

7 Feedback failure detection (FFD)

The OVP function handles “normal” overvoltage conditions, i.e. those resulting from an
abrupt load/line change or occurring at startup. If the overvoltage is generated by a
feedback failure, for instance when the upper resistor of the output divider (R1) fails open,
eventually the error amplifier output (COMP) saturates high and the voltage on its inverting
input (INV) drops from its steady-sate value (2.5 V). An additional comparator monitors the
voltage on the INV pin, comparing it against a reference located at 1.66 V. When the voltage
on pin PFC_OK exceeds 2.5 V and, simultaneously, that on the INV pin falls below 1.66 V,
the FFD function is triggered: the gate drive activity is immediately stopped, the device is
shut down and its quiescent consumption reduced. This condition is latched and to restart
the IC it is necessary to recycle the input power, so that the VCC voltage goes below 6 V.
The pin PFC_OK doubles its function as a not-latched IC disable: a voltage below 0.23 V
shuts down the IC, reducing its consumption below 2 mA. To restart, simply let the voltage
on the pin go above 0.27 V. Note that these functions offer complete protection against not
only feedback loop failures or erroneous settings, but also against a failure of the protection
itself. Either resistor of the PFC_OK divider failing short or open or a pin PFC_OK floating
results in shutting down the IC and stopping the pre-regulator.

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L4984 Voltage feedforward

8 Voltage feedforward

The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. So does the crossover frequency fc of the overall open-loop gain because the gain
has a single pole characteristic. This leads to large trade-offs in the design.
For example, setting the gain of the error amplifier to get fc = 20 Hz at 264 Vac means having
fc = 4 Hz at 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control
loop causes large transient current flow during rapid line or load changes that are limited by
the dynamics of the multiplier output. This limit is considered when selecting the sense
resistor to let the full load power pass under minimum line voltage conditions, with some
margin. But a fixed current limit allows excessive power input at high line, whereas a fixed
power limit requires the current limit to vary inversely with the line voltage.
Input voltage feedforward compensates for the gain variation with the line voltage and allows
all of the above-mentioned issues to be minimized. It consists of deriving a voltage
proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit
(1/V2 corrector) and providing the resulting signal to the multiplier that generates the current
reference for the inner current control loop (see Figure 31).

Figure 31. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer
characteristic

Rectified mains
Vcsx
E/A output 2
current (V COMP ) L4984
reference
(Vcsx)
MULTIPLIER
1.5 V COMP=4V
"ideal" diode
Actual
- Ideal
2 3
1/V
+ 1
MULT
9.5V

MAINS DROP
DETECTOR 0.5

5
VFF
0
C FF 0 0.8 1 2 3 4
R FF
V FF=V MULT

AM13248v1

In this way, if the line voltage doubles the amplitude of the multiplier, output is halved and
vice versa, so that the current reference is adapted to the new operating conditions with
(ideally) no need to invoke the slow response of the error amplifier. Additionally, the loop
gain is constant throughout the input voltage range, which improves significantly dynamic
behavior at low line and simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small, the voltage generated is affected by a
considerable amount of ripple at twice the mains frequency that causes distortion of the
current reference (resulting in high THD and poor PF); if it is too large there is a
considerable delay in setting the right amount of feedforward, resulting in excessive
overshoot and undershoot of the pre-regulator output voltage in response to large line
voltage changes. Clearly, a trade-off is required.
The L4984 realizes a new voltage feedforward that, using just two external parts, strongly
minimizes this time constant trade-off issue whichever voltage change occurs on the mains,

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Voltage feedforward L4984

both surges and drops. A capacitor CFF and a resistor RFF, connected from the VFF pin to
ground, complete an internal peak-holding circuit that provides a DC voltage equal to the
peak of the voltage applied on the MULT pin. In this way, in case of sudden line voltage rise,
CFF is rapidly charged through the low impedance of the internal diode; in case of line
voltage drop, an internal “mains drop” detector enables a low impedance switch that
suddenly discharges CFF, therefore reducing the settling time needed to reach the new
voltage level. The discharge of CFF is stopped when either its voltage equals the voltage on
the MULT pin or the voltage on the VFF pin falls below 0.88 V, to prevent the “brownout
protection” function from being improperly activated (see Section 12: Power management
and housekeeping functions). With this functionality, an acceptably low steady-state ripple of
the VFF voltage (and, then, low current distortion) can be achieved with a limited undershoot
or overshoot on the pre-regulator output during line transients.
The twice-mains-frequency (2⋅ fL) ripple appearing across CFF is triangular with peak-to-
peak amplitude that, with good approximation, is given by:

Equation 13
2 VMULTpk
ΔVFF =
1 + 4fLRFF CFF
where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this
ripple, related to the amplitude of its 2⋅ fL component, is:

Equation 14
100
D3 % =
2π fLRFF CFF

Figure 32 shows a diagram that helps choose the time constant RFF·CFF based on the
amount of maximum desired 3rd harmonic distortion. Note, however, that there is a
minimum value for the time constant RFF·CFF below which improper activation of the VFF
fast discharge may occur. In fact, the twice-mains-frequency ripple across CFF under
steady-state conditions must be lower than the minimum line drop detection threshold
(ΔVVFF_min = 40 mV). Therefore:

Equation 15

VMULTpk _ max
2 −1
ΔVVFF _ min
RFF ⋅ CFF >
4 fL _ min

Always connect RFF and CFF to the pin; the IC does not work properly if the pin is left
floating or may be damaged if connected directly to ground.

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L4984 Voltage feedforward

Figure 32. RFF·CFF as a function of 3rd harmonic distortion introduced in the input
current
10

1
f L = 50 Hz
RFF · CFF [s]

0.1
f L= 60 Hz

0.01
0.1 1 10
D3 % AM13247v1

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Soft-start L4984

9 Soft-start

To reduce inrush energy at startup or after an auto-restart protection tripping, the L4984
uses soft-start. Please refer to Table 1 in Section 12: Power management and
housekeeping functions for more details of the events triggering soft-start.
The function is performed by internally pulling the voltage on the MULT pin towards an
asymptotic level located at about 4.1 V as the device wakes up. This has a twofold effect: on
the one hand, the output of the multiplier is lowered through the voltage feedforward
function, therefore programming a lower peak current; on the other hand, the off-time of the
power switch is considerably prolonged with respect to the normal values programmed by
the capacitor connected to the TIMER pin. In this way, both the current inrush and the risk of
saturating the boost inductor at startup are minimized.
After 300 μs from its activation, the pull-up is released. The voltage on the MULT pin decays
with the time constant determined by the resistor divider that biases the pin and the bypass
capacitor typically connected between the pin and ground to reduce noise pick-up. At the
same time, CFF is discharged by turning on the internal low impedance discharge switch
(see Section 8: Voltage feedforward).

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L4984 Inductor saturation detection

10 Inductor saturation detection

Boost inductor hard saturation may be a fatal event for a PFC pre-regulator: the current
upslope becomes so large (50-100 times steeper, see Figure 33) that, during the current
sense propagation delay, the current may reach abnormally high values. The voltage drop
caused by this abnormal current on the sense resistor reduces the gate-to-source voltage,
so that the MOSFET may work in the active region and dissipate a huge amount of power,
which leads to a catastrophic failure after few switching cycles.
However, even a well-designed boost inductor may occasionally saturate when the boost
stage recovers after a missing line cycle. This happens when the restart occurs at an
unfavorable line voltage phase, i.e. when the output voltage is lower than the rectified input
voltage as this reappears. As a result, in the boost inductor the inrush current coming from
the bridge rectifier and going to the output capacitor adds up to the switched current.
Furthermore, there is little or no voltage available for demagnetization.
To cope with a saturated inductor, the L4984 is provided with a second comparator on the
current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 0.88 V,
exceeds 1.7 V. After that, the IC is restarted by the internal starter circuitry; the starter
repetition time is low enough (300 μs typ.) to guarantee low stress for the inductor, the
Power MOSFET and the boost diode.

Figure 33. Effect of boost inductor saturation on MOSFET current and detection
method

Vcs Vcs Vcs

1.7V 1.7V 1.7V
DIL
Multiplier DIL Multiplier DIL Multiplier
Output Output Output

Tdelay t Tdelay t Tdelay t

Inductor not Inductor slightly Inductor saturating
saturating saturating hard

AM13249v1

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THD optimizer circuit L4984

11 THD optimizer circuit

The L4984 is provided with a special circuit that reduces the conduction dead-angle
occurring at the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (total harmonic distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the high-
frequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This results in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.

Figure 34. THD optimizer circuit

t t
t

2
1/V
COMP
VFF

+ to PWM
MULTIPLIER
MULT comparator
+

t
OFFSET t

GENERATOR

@ Vac1
@ Vac2 > Vac1 t

AM13250v1

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L4984 THD optimizer circuit

Figure 35. HD optimization: standard PFC controller

Figure 34 shows the internal block diagram of the THD optimizer circuit.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current - even with
an ideal energy transfer by the PFC pre-regulator - therefore reducing the effectiveness of
the optimizer circuit.
Essentially, the circuit artificially increases the on-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is
modulated by the voltage on the VFF pin (see Section 8: Voltage feedforward) so as to have
little offset at low line, where energy transfer at zero-crossings is typically quite good, and a
larger offset at high line where the energy transfer gets worse.
The effect of the circuit is shown in Figure 35, where the key waveforms of a standard PFC
controller are compared to those of this chip. Note the significant reduction in the region
around the zero-crossing where the drain voltage cannot reach the output voltage and how
switching frequency drops dramatically near the zero-crossing.

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Power management and housekeeping functions L4984

12 Power management and housekeeping functions

A communication line with the control IC of the cascaded DC-DC converter can be
established via the disable function included in the PFC_OK pin (see Section 7: Feedback
failure detection (FFD) for more details). Typically this line is used to allow the PWM
controller of the cascaded DC-DC converter to shut down the L4984 in case of light load and
to minimize the no-load input consumption. Should the residual consumption of the chip be
an issue, it is also possible to cut down the supply voltage. Interface circuits like those are
shown in Figure 36. Needless to say, this operation assumes that the cascaded DC-DC
converter stage works as the master and the PFC stage as the slave or, in other words, that
the DC-DC stage starts first; it powers both controllers and enables/disables the operation of
the PFC stage.

Figure 36. Interface circuits that let DC-DC converter controller IC disable the L4984

L6566A L4984
VCC 5 6 VCC_PFC VCC 10

PFC_OK 6
L6599A L4984
9 PFC_STOP

PFC_OK 6
L6591 L4984
8 PFC_STOP

AM13252v1

Another available function is brownout protection, which is basically a not-latched shutdown

function that is activated when a condition of mains undervoltage is detected. This condition
may cause overheating of the primary power section due to an excess of RMS current.
Brownout can also cause the PFC pre-regulator to work in open loop, which may be
dangerous to the PFC stage itself and the downstream converter, should the input voltage
return abruptly to its rated value. Another problem is the spurious restarts that may occur
during converter power-down and that cause the output voltage of the converter to not
decay to zero monotonically. For these reasons it is usually preferable to shut down the unit
in the case of brownout. The brownout threshold is internally fixed at 0.8 V and is sensed on
the VFF pin while the voltage is falling. An 80 mV hysteresis prevents rebounding at input
voltage turn-off.
In Table 6 it is possible to find a summary of all of the above mentioned working conditions
that cause the device to stop operating.

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L4984 Power management and housekeeping functions

Table 6. Summary of L4984 idle states

Restart Typical IC SS
Condition Caused or revealed by IC behavior
condition consumption activation

UVLO VCC < VCCOff Disabled VCC > VCCOn 65 µA Yes

Stop VPFC_OK >
Standby VPFC_OK < VPFC_OK_D 1.5 mA No
switching VPFC_OK_E
Stop
AC brownout VVFF < VDIS VVFF > VEN 1.5 mA Yes
switching
Stop VPFC_OK <
OVP VPFC_OK > VPFC_OK_S 2.2 mA No
switching VPFC_OK_R
VPFC_OK > VPFC_OK_S VCC < VCCrestart
Feedback
AND Latched-off then 180 µA Yes
failure
VINV < 1.66 V VCC > VCCOn
Low
V < 2.4 V Burst mode VCOMP > 2.4 V 1.8 mA No
consumption COMP
Saturated
Stop Auto restart
boost Vcs > VCS_th 4 mA No
switching after 300 ìs
inductor

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ECOPACK L4984

13 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.

Table 7. SSO10 mechanical data

Databook (mm)
Dim.
Typ. Min. Max.

A 1.75
A1 0.10 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 4.90 4.80 5
E 6 5.80 6.20
E1 3.90 3.80 4
e 1
h 0.25 0.50
L 0.40 0.90
K 0° 8°

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L4984 ECOPACK

Figure 37. SSO10 package dimensions

8140761 rev. A

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Revision history L4984

14 Revision history

Table 8. Document revision history

Date Revision Changes

20-Aug-2012 1 Initial release.

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L4984

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