Course Syllabus
Course Code / Course Name ESS 102 Digital Design
Course Instructor Name(s) G R Sinha
Hours Component
3 Lecture (1hr = 1 credit)
Credits (L: T:P)
1 Tutorial (1hr = 1 credit)
(Lecture: Tutorial: Practical)
0 Practical (2hrs = 1 credit)
L:T:P = [Link] Total Credits = 3
Grading Scheme X 4-point scale (A, A-, B+, B, B-, C+, C, D, F)
(Choose by placing X against
appropriate box) Satisfactory/Unsatisfactory (S / X)
Area of Specialization (if applicable)
(Choose by placing X in box against not more than two areas from the list)
Theory and Systems for Computing Networking and Communication
and Data
Artificial Intelligence and Machine Digital Society
Learning
VLSI Systems Cyber Security
General Elective
Programme / Branch Course is restricted to the following programmes / branch(es):
(Place X appropriately. More than one is okay)
Programme: Branch:
X iMTech X CSE
[Link] X ECE
[Link]. Digital Society
Course Category Select one from the following:
(Place X appropriately)
Basic Sciences
X CSE Core
X ECE Core
CSE Branch Elective
ECE Branch Elective
Engineering Science and Skills
HSS/M
General
Course Pre-Requisites (Where applicable, state exact course code/name)
None
Template Version 1.1
Template Date April 4, 2021
Additional Focus Areas
Yes /
Focus Area Details
No
Direct focus on employability Yes
Yes Students learn some basic design theory using
Focus on skill development Verilog HDL
Focus on entrepreneurship No
Provides value added / life skills Yes Through assignment
(Language, writing, communication, etc.)
Course Context and Overview
This course is a foundational course in for Computer Science and Engineering and Electronics &
Communication Engineering. Main course objectives are:
To understand how numbers are represented in digital computing systems and their importance
To understand the fundamentals of digital hardware using CMOS and VLSI technology
To apply simple design of combinational and sequential circuits required for computing systems.
Course Outcomes and Competencies
Course Outcome PO/ PSO CL KC Class Tut
(Hrs) (Hrs)
CO1 Describe number representation and its importance PO1, PSO1 U, R, C, A 6 2
Ap
CO2 Discuss the concept of 2’s complement and apply in PO1, PSO1 U, Ap C, Ap 3 1
simple operations
CO3 Explain Boolean logic theorems and apply in PO1, PO5, U, Ap C, A 6 2
solving logical expressions PSO1
CO4 Discuss Combinational and Sequential Circuits and PO1, PO5 U, Ap C, Ap, 12 4
apply them in designing basic building blocks such PSO1 A
as adders, counters, digital memory system.
CO5 Interpret concept of diode and CMO and use for PO1, PSO1 U, Ap C, Ap 9 3
deigning logic gates
CO6 Solve complex Boolean expressions using K-map PO1, PO5, R, U, C, An, 6 2
PSO1. Ap, Ap
PSO4 Ev
CO7 Define HDL Programming and its use for digital PO1, PSO1 U, Ap C, Ap 3 1
design
Total 45 15
Legend: PO/PSO: Programme Outcomes / Programme Specific Outcomes; CL: Cognitive Level (from Revised
Bloom’s Taxonomy); KC: Knowledge Category (from Revised Bloom’s Taxonomy); Class (Hrs): Number of hours
of instruction; Tut (Hrs): Number of hours of tutorial session (where applicable)
Template Version 1.1
Template Date April 4, 2021
Concept Map of the Course (Optional)
Course Content
Importance and Introduction the term “Digital”; Number representations in computing (binary, octal, BCD,
hexadecimal); 2’s complement representation, addition and subtraction; Boolean logic theorem;
Simplification of logic expressions; Truth Tables; Karnaugh map; SOP and POS forms; Combinational
logic circuits and their Representations; Adders; Fast adders, Multiplexers; Decoders; Programmable logic;
Sequential circuits; Flip-flops; Memory sub-systems; Counters; Moore & Mealy machines (FSM): Logic
Gates; Noise Margin, Glitches; Basics of Semiconductors; Operation of Diodes and MOSFET/CMOS;
NAND/NOR using CMOS; Introduction to HDL programming specifically Verilog
Instruction Schedule
Week Topics
1 Importance and Introduction the term “Digital”
2-3 Number representations, 2’s complement representation, addition and subtraction
4-5 Boolean logic theorem, Simplification of logic expressions
6-7 Truth Tables, Karnaugh map, SOP and POS forms
8-9 Combinational logic circuits, Adders, Fast adders, Multipliers, Multiplexers, Decoders,
Programmable logic
10-11 Sequential circuits; Flip-flops; Memory sub-systems, Counters
12 Moore & Mealy machines (FSM)
13-14 Logic Gates, Noise Margin, Glitches, Basics of Semiconductors, Operation of Diodes and
MOSFET/CMOS, NAND/NOR using CMOS
15 Introduction to HDL programming specifically Verilog
Learning Resources
1. David M. Harris, Sarah Harris, Digital Design & Computer Architecture, 2nd Edition, Elsevier, 2013.
2. Morris Mano, Michael D. Ciletti, Digital Design- With an Introduction to the Verilog HDL, 5th edition,
Pearson, 2013.
3. An online simulation tool [Link]
4. Lecture Power Point Slides
Template Version 1.1
Template Date April 4, 2021
Assessment Plan
Assessment Component Marks (Weightage) Remarks
Quizzes-03 25 (05+10+10)
Experiments and Writing Records of Results
**Structured Assignment 20
followed by Viva
Mid Semester Examination 20
Comprehensive Examination 35
Total: 100%
**Assignments are to be allotted to students in team of 2 students. Each team has to study, design,
implement, report and present the assignment. This shall be followed by Viva.
Assignments / Projects
S. No. Focus of Assignment / Project CO Mapping
1 Logic simplification using Boolean Theorems CO3, CO6
2 Logic simplification using Karnaugh Maps CO6
3 Designing Combinational and Sequential Systems CO4
4 Applications of Design using Simulation tool CO4, CO6, CO7
Evaluation Procedures
Provide details of how evaluations will be done, how students can look at the evaluations. Generic
evaluation procedures included below. Add additional evaluation procedures / criteria as needed.
The course uses one or more of the following evaluation procedures as part of the course:
Manual evaluation of design problems in assignments, quizzes and exams
Manual evaluation of Circuitverse assignments and project.
Students are provided the opportunity to view the evaluations done either in person or online.
Late Assignment Submission Policy
Late submissions are accepted with a penalty.
Make-up Exam/Submission Policy
As per institute policy
Template Version 1.1
Template Date April 4, 2021
Citation Policy for Papers (if applicable)
Not Applicable
Academic Dishonesty/Plagiarism
As per institute policy
Accommodation of Divyangs/Persons with Disabilities (PwDs)
As per institute policy
Template Version 1.1
Template Date April 4, 2021
