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0% found this document useful (0 votes)

315 views293 pages

HX8398 PDF

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Bayan Mashrequi

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Available Formats

Download as PDF, TXT or read online on Scribd

( DOC No.

HX8398-A-DS )

HX8398-A
1080RGB x 1920 dot, 16.7M
color, a-Si TFT Mobile Single
Chip Driver

Temporary Version 00.04 May, 2015

HX8398-A
1080RGB x 1920 dot, 16.7M color, a-Si TFT
Mobile Single Chip Driver

Revision History May, 2015

Version Date Description of Changes

00.01 2014/10/21 New setup
00.02 2015/01/05 RB2h NL function modify description
00.03 2015/01/30 Update OTP Program ALL sequence
(1) Modify RB2h Free-running mode pattern number
00.04 2015/05/19 (2) Modufy RB7h TEP[10:0] setting restriction
(3) Modify RD3h GIP_Mode & GIP EQ period setting

Himax Confidential - P.2-

List of Contents May, 2015

1. General Description ............................................................................................................................. 11

2. Features ................................................................................................................................................ 12
2.1 Display .......................................................................................................................................... 12
2.2 Display module.............................................................................................................................. 12
2.3 Support DC/DC booster: ............................................................................................................... 13
2.4 Display / Control interface ............................................................................................................. 13
2.5 Input power ................................................................................................................................... 13
2.6 Miscellaneous ............................................................................................................................... 13
3. Device Overview .................................................................................................................................. 14
3.1 Block diagram ............................................................................................................................... 14
3.2 Pin description............................................................................................................................... 15
4. Interface ................................................................................................................................................ 19
4.1 System interface ........................................................................................................................... 19
4.2 Serial data transfer interface (MIPI DBI-TypeC) ........................................................................... 20
4.2.1 Serial data write mode...................................................................................................... 20
4.2.2 Serial data read mode ...................................................................................................... 21
4.3 I2C interface .................................................................................................................................. 23
4.3.1 I2C protocol ...................................................................................................................... 23
4.3.2 I2C slave address............................................................................................................. 24
4.3.3 I2C interface write mode .................................................................................................. 25
4.3.4 I2C interface read mode ................................................................................................... 26
4.4 DSI system interface ..................................................................................................................... 27
4.4.1 DSI layer definitions ......................................................................................................... 28
4.4.2 DSI protocol...................................................................................................................... 39
4.4.3 Processor to peripheral direction packets data types ...................................................... 42
4.4.4 Peripheral to processor (reverse direction) ...................................................................... 49
5. Function Description .......................................................................................................................... 51
5.1 Tearing effect output line ............................................................................................................... 51
5.1.1 Tearing effect line timing................................................................................................... 53
5.2 Oscillator ....................................................................................................................................... 54
5.3 Source driver ................................................................................................................................. 55
5.4 LCD power generation scheme .................................................................................................... 59
5.5 DC/DC converter circuit ................................................................................................................ 61
5.5.1 Charge pump and step up circuit mode ........................................................................... 61
5.5.2 Use HX5186-C ................................................................................................................. 62
5.5.3 Use PFM DC/DC converter .............................................................................................. 63
5.5.4 Use external VSP and VSN circuit ................................................................................... 66
5.5.5 Use external VSP and VSN and VDD3 circuit ................................................................. 67
5.5.6 Use external VSP and VSN and VGH and VGL circuit .................................................... 68
5.6 Idle display .................................................................................................................................... 69
5.7 Gamma characteristic correction function .................................................................................... 70
5.7.1 Gamma-Characteristics adjustment register .................................................................... 72
5.7.2 Gray voltage generator for digital gamma correction ....................................................... 89
5.8 Characteristics of I/O .................................................................................................................... 91
5.8.1 Output or bi-directional (I/O) pins ..................................................................................... 91
5.8.2 Input pins .......................................................................................................................... 91
5.9 Sleep Out –command and self-diagnostic functions of the display module ................................. 92
5.9.1 Register loading detection ................................................................................................ 92
5.9.2 Functionality detection ..................................................................................................... 93
5.10 Power on/off sequence ................................................................................................................. 94

Himax Confidential - P.3-

List of Contents May, 2015

5.10.1 VDD3/VDD1 iput power(PCCS[2:0]=000, 001, 101) ........................................................ 95
5.10.2 VSP/VDD1 iput power(PCCS[2:0]=010) .......................................................................... 96
5.10.3 VSP/VSN/VDD1 iput power(PCCS[2:0]=011) .................................................................. 97
5.10.4 VDD3/VSP/VSN/VDD1 iput power(PCCS[2:0]=111) ........................................................ 98
5.10.5 VSP/VSN/VGH/VGL iput power(PCCS[2:0]=100) ........................................................... 99
5.11 Uncontrolled power off ................................................................................................................ 101
5.12 Content adaptive brightness control (CABC) function ................................................................ 102
5.12.1 Module architectures ...................................................................................................... 103
5.12.2 CABC block .................................................................................................................... 104
5.12.3 Brightness control block ................................................................................................. 105
5.12.4 Minimum brightness setting of CABC function ............................................................... 106
5.13 Temperature sensor .................................................................................................................... 107
5.14 Idle Mode GRAM Display............................................................................................................ 108
5.15 OTP programing.......................................................................................................................... 109
5.15.1 OTP table ....................................................................................................................... 109
5.15.2 OTP programming flow .................................................................................................. 120
5.15.3 Programming sequence ................................................................................................. 121
5.15.4 OTP Programming example of VCOM setting VCMC ................................................... 122
5.15.5 OTP Programming example of ID1, ID2, ID3 and ID4 ................................................... 123
5.15.6 OTP Programming all OTP Index(000h~2FFh) ............................................................. 124
5.15.7 Flexible OTP Index(300h~3FFh) Programming ............................................................. 125
5.15.8 Flexible OTP Index(300h~3FFh) Continuous Programming .......................................... 126
5.15.9 OTP read example of OTP Index 00h (ID1) ................................................................... 127
6. Command ........................................................................................................................................... 128
6.1 Command list .............................................................................................................................. 128
6.1.1 Standard command ........................................................................................................ 128
6.1.2 User define command list table ...................................................................................... 130
6.2 Command description ................................................................................................................. 141
6.2.1 NOP (00h) ...................................................................................................................... 141
6.2.2 Software reset (01h) ....................................................................................................... 142
6.2.3 Read Display Identification Information (04h) ................................................................ 143
6.2.4 RDNUMPE: Read number of the parity errors (05h) ..................................................... 144
6.2.5 Get_red_channel (06h) .................................................................................................. 145
6.2.6 Get_green_channel (07h) .............................................................................................. 146
6.2.7 Get_blue_channel (08h) ................................................................................................. 147
6.2.8 Read Display Status (09h) ............................................................................................. 148
6.2.9 Get_power_mode (0Ah) ................................................................................................. 152
6.2.10 Read display MADCTL (0Bh) ......................................................................................... 154
6.2.11 Get_pixel_format (0Ch) .................................................................................................. 156
6.2.12 Get_display_mode (0Dh) ............................................................................................... 158
6.2.13 Get_signal_mode (0Eh) ................................................................................................. 160
6.2.14 Get_diagnostic_result (0Fh) ........................................................................................... 162
6.2.15 Enter_sleep_mode (10h) ................................................................................................ 163
6.2.16 Exit_sleep_omde (11h)................................................................................................... 164
6.2.17 Enter_normal_mode (13h) ............................................................................................. 165
6.2.18 Exit_inversion_mode (20h) ............................................................................................ 166
6.2.19 Enter_inversion_mode (21h) .......................................................................................... 167
6.2.20 All_Pixel_Off (22h) ......................................................................................................... 168
6.2.21 All_Pixel_On (23h) ......................................................................................................... 169
6.2.22 Set_gamma_curve (26h) ................................................................................................ 170
6.2.23 Set_display_off (28h) ..................................................................................................... 171
6.2.24 Set_display_on (29h) ..................................................................................................... 172
6.2.25 Write_memory_start (2Ch) ............................................................................................. 173
6.2.26 Tearing effect line off (34h) ............................................................................................. 174
Himax Confidential - P.4-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGB x 1920 dot, 16.7M color, a-Si TFT
Mobile Single Chip Driver

List of Contents May, 2015

6.2.27 Set_tear_on (35h) .......................................................................................................... 175
6.2.28 Set_address_mode (36h) ............................................................................................... 176
6.2.29 Idle mode off (38h) ......................................................................................................... 179
6.2.30 Enter_Idle_mode (39h) .................................................................................................. 180
6.2.31 Set_pixel_format (3Ah) .................................................................................................. 181
6.2.32 Write_memory_contiune (3Ch) ...................................................................................... 182
6.2.33 Set tear scan lines (44h) ................................................................................................ 183
6.2.34 Get the current scanline(45h) ......................................................................................... 184
6.2.35 Write display brightness (51h) ........................................................................................ 185
6.2.36 Read display brightness value (52h) .............................................................................. 186
6.2.37 Write CTRL display (53h) ............................................................................................... 187
6.2.38 Read CTRL value display (54h) ..................................................................................... 188
6.2.39 Write content adaptive brightness control (55h) ............................................................ 189
6.2.40 Read content adaptive brightness control (56h) ............................................................ 190
6.2.41 Write CABC minimum brightness (5Eh) ......................................................................... 191
6.2.42 Read CABC minimum brightness (5Fh) ......................................................................... 192
6.2.43 Read automatic brightness control self-diagnostic result (68h) ..................................... 193
6.2.44 Write Idle Mode Color(80h) ............................................................................................ 194
6.2.45 Read Idle Mode Color(81h) ............................................................................................ 195
6.2.46 Read_DDB_start (A1h) .................................................................................................. 196
6.2.47 Read_DDB_continue (A8h) ............................................................................................ 198
6.2.48 Read ID1 (DAh) .............................................................................................................. 199
6.2.49 Read ID2 (DBh) .............................................................................................................. 200
6.2.50 Read ID3 (DCh).............................................................................................................. 201
6.3 User Define Command Description ............................................................................................ 202
6.3.1 SETPOWER: Set power (B1h) ....................................................................................... 202
6.3.2 SETDISP: Set display related register (B2h) ................................................................. 212
6.3.3 SETCYC: Set display waveform cycles (B4h) ............................................................... 216
6.3.4 SETVCOM: Set VCOM voltage (B6h) ............................................................................ 221
6.3.5 SETTE: Set internal TE function (B7h) .......................................................................... 223
6.3.6 SETSENSOR: Set temperature sensor (B8h) ............................................................... 224
6.3.7 SETEXTC: Set extension command (B9h) .................................................................... 228
6.3.8 SETMIPI: Set MIPI control (BAh) ................................................................................... 229
6.3.9 SETOTP: Set OTP (BBh) ............................................................................................... 230
6.3.10 SET_BANK: Set register bank (BDh) ............................................................................. 232
6.3.11 SETDGCLUT: Set DGC LUT (C1h) ................................................................................ 233
6.3.12 SETID: Set ID (C3h) ....................................................................................................... 237
6.3.13 SETDDB: Set DDB (C4h) ............................................................................................... 238
6.3.14 SETCABC: Set CABC control (C9h) .............................................................................. 239
6.3.15 SETPANEL (CCh) .......................................................................................................... 241
6.3.16 SETOFFSET (D2h) ........................................................................................................ 242
6.3.17 SETGIP0: Set GIP Option0 (D3h) .................................................................................. 243
6.3.18 SETGIP1: Set GIP Option1 (D5h) .................................................................................. 249
6.3.19 SETGIP2: Set GIP Option2 (D6h) .................................................................................. 252
6.3.20 SETGIP3: Set GIP Option3 (D8h) .................................................................................. 255
6.3.21 SETGPO (D9h) .............................................................................................................. 259
6.3.22 SETSCALING (DDh) ...................................................................................................... 260
6.3.23 SETIDLE (DFh) .............................................................................................................. 261
6.3.24 SETGAMMA: Set gamma curve related setting (E0h) ................................................... 265
6.3.25 SETCHEMODE_DYN (E4h) .......................................................................................... 267
6.3.26 SETI2C_SA: Set I2C Slave Address (E8h) .................................................................... 269
6.3.27 SETCNCD/GETCNCD (FDh) ......................................................................................... 270
6.3.28 SETREADINDEX: Set SPI Read Index (FEh) ............................................................... 271
6.3.29 GETSPIREAD: SPI Read Command Data (FFh) .......................................................... 272
7. Layout Recommendation ................................................................................................................. 273
Himax Confidential - P.5-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGB x 1920 dot, 16.7M color, a-Si TFT
Mobile Single Chip Driver

List of Contents May, 2015

7.1 Maximum layout resistance(include IC and FPC bonding) ......................................................... 273
7.2 External Components Connection .............................................................................................. 274
8. Electrical Characteristics ................................................................................................................. 278
8.1 Absolute maximum ratings .......................................................................................................... 278
8.2 DC characteristics ....................................................................................................................... 279
8.3 AC characteristics ....................................................................................................................... 280
8.3.1 I2C AC characteristics .................................................................................................... 280
8.3.2 DBI Type C interface characteristics .............................................................................. 281
8.3.3 DSI D-PHY electrical characteristics .............................................................................. 282
8.3.4 Timings for DSI Video mode .......................................................................................... 290
8.3.5 Reset input timing........................................................................................................... 292
9. Ordering Information ........................................................................................................................ 293

Himax Confidential - P.6-

List of Figures May, 2015

Figure 4.1: DBI Type C: Serial interface protocol 3-wire/4-wire, write mode ............................ 20
Figure 4.2: Type C:Serial interface protocol 3-wire/4-wire read mode ...................................... 21
Figure 4.3: Display module data transfer recovery ................................................................... 21
Figure 4.4: Break During Parameter ......................................................................................... 22
Figure 4.5: Display Module Data Transfer Pause ..................................................................... 22
Figure 4.6: I2C connection diagram .......................................................................................... 23
2
Figure 4.7: I C Signal timing...................................................................................................... 23
2
Figure 4.8: I C START/STOP .................................................................................................... 24
2
Figure 4.9: I C data transfer ...................................................................................................... 24
2
Figure 4.10: I C interface register write flow ............................................................................. 25
2
Figure 4.11: I C interface register read flow .............................................................................. 26
Figure 4.12: DSI transmitter and receiver interface .................................................................. 27
Figure 4.13: DSI transmitter and receiver interface .................................................................. 28
Figure 4.14: Clock Lane Mode State diagram ........................................................................... 30
Figure 4.15: Data Lane Mode State diagram ............................................................................ 32
Figure 4.16: Escape Mode State Machine ................................................................................ 33
Figure 4.17: Escape Mode timing sequence ............................................................................. 34
Figure 4.18: High Speed Data Transmission State Machine ..................................................... 35
Figure 4.19: High Speed Data Transmission timing sequence ................................................. 35
Figure 4.20: Switching the Clock Lane between Clock Transmission and LP Mode ................ 36
Figure 4.21: Turnaround State Machine .................................................................................... 38
Figure 4.22: Turnaround timing sequence ................................................................................ 38
Figure 4.23: Multiple HS transmission packets ......................................................................... 39
Figure 4.24: Structure of the short packet ................................................................................. 39
Figure 4.25: Structure of the long packet .................................................................................. 40
Figure 4.26: The format of data ID. ........................................................................................... 40
Figure 4.27: show Short- / Long-packet transmission command sequence ............................. 41
Figure 5.1: Tearing Effect Output signal mode 1 ...................................................................... 51
Figure 5.2: TE Delay Output...................................................................................................... 51
Figure 5.3: Tearing Effect Output signal mode 2 ...................................................................... 52
Figure 5.4: TE Output for TELINE setting ................................................................................. 52
Figure 5.5: Tearing Effect Output signal ................................................................................... 52
Figure 5.6: Tearing effect output line –tearing effect line timing ................................................ 53
Figure 5.7: Tearing effect output line–definition of tf, tr ............................................................. 53
Figure 5.8: OSC architecture..................................................................................................... 54
Figure 5.9: Inversion mode........................................................................................................ 56
Figure 5.10: Zig-Zag Inversion mode(ZZ_2PL=0) ..................................................................... 57
Figure 5.11: Zig-Zag2 Inversion mode(ZZ_2PL=1) ................................................................... 58
Figure 5.12: LCD power generation scheme for HX5186 and PFM mode ............................... 59
Figure 5.13: LCD power generation scheme for external power mode .................................... 59
Figure 5.14: DC/DC converter circuit of HX5186-C .................................................................. 62
Figure 5.15: DC/DC converter circuit (PFM Type A) ................................................................. 63
Figure 5.16: DC/DC converter circuit (PFM Type D) ................................................................. 64
Figure 5.17: DC/DC converter circuit (PFM Type C) ................................................................. 65
Figure 5.18: DC/DC converter circuit of external VSP/VSN ...................................................... 66
Figure 5.19: DC/DC converter circuit of external VDD3/VSP/VSN ........................................... 67
Figure 5.20: DC/DC converter circuit of external VSP/VSN/VGH/VGL .................................... 68
Figure 5.21: Idle mode grayscale control .................................................................................. 69
Figure 5.22: Gamma adjustments different of source driver with digital gamma correction ..... 70
Figure 5.23: Grayscale control .................................................................................................. 71
Figure 5.24: Gamma resister stream and gamma reference voltage ....................................... 74
Figure 5.25: Block diagram of digital gamma correction ........................................................... 89
Figure 5.26: Sleep out flow chart–command and self-diagnostic functions .............................. 92
Figure 5.27: Sleep out flow chart internal function detection .................................................... 93
Figure 5.28: Power on/off sequence ......................................................................................... 94
Himax Confidential - P.7-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGB x 1920 dot, 16.7M color, a-Si TFT
Mobile Single Chip Driver

List of Figures May, 2015

Figure 5.29: VDD3/VDD1 input power on sequence ................................................................ 95
Figure 5.30: VDD3/VDD1 input power off sequence................................................................. 95
Figure 5.31: VSP/VDD1 input power on sequence ................................................................... 96
Figure 5.32: VSP/VDD1 input power off sequence ................................................................... 96
Figure 5.33: VSP/VSN/VDD1 input power on sequence .......................................................... 97
Figure 5.34: VSP/VSN/VDD1 input power off sequence .......................................................... 97
Figure 5.35: VDD3/VSP/VSN/VDD1 input power on sequence ................................................ 98
Figure 5.36: VDD3/VSP/VSN/VDD1 input power off sequence ................................................ 98
Figure 5.37: VSP/VSN/VGH/VGL input power on sequence .................................................... 99
Figure 5.38: VSP/VSN/VGH/VGL input power off sequence .................................................. 100
Figure 5.39: CABC block diagram ........................................................................................... 102
Figure 5.40: Module architecture ............................................................................................ 103
Figure 5.41: CABC gain / CABC duty generation ................................................................... 104
Figure 5.42: CABC_PWM_OUT output duty ........................................................................... 105
Figure 5.43: Tempeture sensor diagram ................................................................................. 107
Figure 5.44: Idle Mode On/Off Sequence ............................................................................... 108
Figure 5.45: OTP programming sequence .............................................................................. 120
Figure 5.46: OTP programming VCOM sequence .................................................................. 122
Figure 5.47: OTP programming ID sequence ......................................................................... 123
Figure 5.48: OTP programming all Index sequence ............................................................... 124
Figure 5.49: Flexible OTP programming sequence ................................................................ 125
Figure 5.50: Flexible OTP continuous programming sequence .............................................. 126
Figure 5.51: OTP read sequence flow of Index 00h................................................................ 127
Figure 8.1 I2C timing ............................................................................................................... 280
Figure 8.2: DBI Type C interface characteristics ..................................................................... 281
Figure 8.3: Electrical functions of a fully D-PHY transceiver ................................................... 282
Figure 8.4: Shows both the HS and LP signal levels .............................................................. 282
Figure 8.5: Differential HS signals for HS receive ................................................................... 284
Figure 8.6: Input Glitch Rejections of Low-Power Receivers .................................................. 285
Figure 8.7: DDR Clock Definition ............................................................................................ 287
Figure 8.8: Data to Clock Timing Definitions ........................................................................... 288
Figure 8.9: Skew window of transmittor and receiver ............................................................. 289
Figure 8.10: Vertical Timings for RGB I/F ................................................................................ 290
Figure 8.11: Horizontal Timing for DSI Video mode I/F ........................................................... 291
Figure 8.12: Reset input timing ............................................................................................... 292

Himax Confidential - P.8-

List of Tables May, 2015

Table 4.1: Interface selection .................................................................................................... 19
Table 4.2: Pin connection based on different interface ............................................................. 19
2
Table 4.3: I C Slave Address table ............................................................................................ 24
Table 4.4: Global Operation Timing Parameters for Data Lane ................................................ 36
Table 4.5: Global Operation Timing Parameters for Clock Lane ............................................... 37
Table 4.6: Data types for processor-sourced packets ............................................................... 42
Table 4.7: Shows the error report bit definitions. ....................................................................... 50
Table 4.8: The complete set of peripheral-to-processor data types. ......................................... 50
Table 5.1: AC characteristics of tearing effect signal ................................................................ 53
Table 5.2: Source output for Panel resolution ........................................................................... 55
Table 5.3: Voltage configuration ................................................................................................ 60
Table 5.4: Power mode setting .................................................................................................. 61
Table 5.5: Gamma-Adjustment registers for normally white panel............................................ 72
Table 5.6: Gamma-Adjustment registers for normally black panel ........................................... 73
Table 5.7: Edge adjustment Resistance .................................................................................... 75
Table 5.8: Center adjustment Resistance ................................................................................. 75
Table 5.9: VinP/N0 ..................................................................................................................... 76
Table 5.10: VinP/N1................................................................................................................... 76
Table 5.11: VinP/N3 ................................................................................................................... 76
Table 5.12: VinP/N5................................................................................................................... 77
Table 5.13: VinP/N7................................................................................................................... 77
Table 5.14: VinP/N9................................................................................................................... 77
Table 5.15: VinP/N12................................................................................................................. 78
Table 5.16: VinP/N15................................................................................................................. 78
Table 5.17: VinP/N20................................................................................................................. 78
Table 5.18: VinP/N28................................................................................................................. 79
Table 5.19: VinP/N40................................................................................................................. 79
Table 5.20: VinP/N52................................................................................................................. 79
Table 5.21: VinP/N76................................................................................................................. 80
Table 5.22: VinP/N100............................................................................................................... 80
Table 5.23: VinP/N128............................................................................................................... 80
Table 5.24: VinP/N156............................................................................................................... 81
Table 5.25: VinP/N180............................................................................................................... 81
Table 5.26: VinP/N204............................................................................................................... 81
Table 5.27: VinP/N216............................................................................................................... 82
Table 5.28: VinP/N228............................................................................................................... 82
Table 5.29: VinP/N236............................................................................................................... 82
Table 5.30: VinP/N240............................................................................................................... 83
Table 5.31: VinP/N243............................................................................................................... 83
Table 5.32: VinP/N246............................................................................................................... 83
Table 5.33: VinP/N248............................................................................................................... 84
Table 5.34: VinP/N250............................................................................................................... 84
Table 5.35: VinP/N252............................................................................................................... 84
Table 5.36: VinP/N254............................................................................................................... 85
Table 5.37: VinP/N255............................................................................................................... 85
Table 5.38: Voltage calculation formula of 256-grayscale voltage (positive/negative polarity) . 88
Table 5.39: DGC Look-up table ................................................................................................. 90
Table 5.40: Characteristics of output or bi-directional (I/O) pins ............................................... 91
Table 5.41: Characteristics of input pins ................................................................................... 91
Table 5.42: CABC timing table ................................................................................................ 105
Table 5.43: OTP table ............................................................................................................... 119
Table 5.44: OTP Programming sequence ............................................................................... 121
Table 7.1: Maximum Layout Resistance(include IC and FPC bonding) .................................. 273
Table 7.2: HX5186-C mode external components .................................................................. 274
Table 7.3: PFM Type A mode external components ............................................................... 274
Himax Confidential - P.9-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGB x 1920 dot, 16.7M color, a-Si TFT
Mobile Single Chip Driver

List of Tables May, 2015

Table 7.4: PFM Type D mode external components ............................................................... 275
Table 7.5: PFM Type C mode external components ............................................................... 275
Table 7.6: External VSP/VSN mode external components ..................................................... 276
Table 7.7: External VDD3/VSP/VSN mode external components........................................... 276
Table 7.8: External VSP/VSN/VGH/VGL mode external components .................................... 277
Table 8.1: Absolute maximum rating ....................................................................................... 278
Table 8.2: DC characteristic .................................................................................................... 279
Table 8.3 I2C timing spec. ....................................................................................................... 280
Table 8.4: DBI Type C interface characteristics ...................................................................... 281
Table 8.5: LP Transmitter DC Specifications ........................................................................... 283
Table 8.6: LP Transmitter AC Specifications ........................................................................... 283
Table 8.7: HS Receiver DC Specifications .............................................................................. 284
Table 8.8: HS Receiver AC Specifications .............................................................................. 284
Table 8.9: LP Receiver DC Specifications ............................................................................... 285
Table 8.10: LP Receiver AC Specifications ............................................................................. 285
Table 8.11: Contention Detector DC Specifications ................................................................ 286
Table 8.12: HS Data Transmission Timing Parameters .......................................................... 288
Table 8.13: Data to Clock Timing Specifications ..................................................................... 289
Table 8.14: Vertical Timings for RGB I/F ................................................................................. 290
Table 8.15: Horizontal Timings for DSI Video mode I/F .......................................................... 291
Table 8.16: Reset timing .......................................................................................................... 292

Himax Confidential - P.10-

Temporary Version 00.02 May, 2015

1. General Description
HX8398-A supports Full HD resolution driving controller. The HX8398-A is designed
to provide a single-chip solution that combines a source driver, gate driver control,
power supply circuit to drive a a-Si TFT dot matrix LCD with 1080RGBx1920 dots at
maximum.

The HX8398-A can be operated in low-voltage condition for the interface and
integrated internal boosters that produce the liquid crystal voltage, breeder resistance
and the voltage follower circuit for liquid crystal driver. In addition, the HX8398-A also
supports various functions to reduce the power consumption of a LCD system via
software control.

The HX8398-A supports MIPI DSI (Display Serial Interface), DBI TypeC and I2C
interface. The interface mode is selected by the external hardware pins IM2~0.

The HX8398-A is suitable for any small portable battery-driven and long-term driving
products, such as cellular phones, tablet and other mobile devices.

Himax Confidential -P.11-

2. Features
2.1 Display

 Single chip solution for a Full HD a-Si TFT type LCD display
 Resolution:
 1080RGB x (528 + 8xNL)
 1024RGB x (528 + 8xNL)
 960RGB x (528 + 8xNL)
 900RGB x (528 + 8xNL)
 800RGB x (528 + 8xNL)
 720RGB x (528 + 8xNL)
Note: NL=0~254

 Display color modes

 Full color mode:
 16.7M colours (24-bit 8(R):8(G):8(B))
 Reduce color mode:
 262k colours (18-bit 6(R):6(G):6(B))
 65k colours (16-bit 5(R):6(G):5(B))
 8 colors (Idle mode on): 8 colors (3-bit binary mode)

2.2 Display module

 Support 3242 source channel outputs

 Internal level shifter for Gate Driver control
 Supports 1-dot / 2-dot / 2-dot-2 / 3-dot/ 4-dot / 8-dot / Column / Zig-Zag /
Zig-Zag2 inversion
 Gamma correction
 On module DC/DC converter
 Positive source output voltage level: VSPR=3.1V to 5.8V
 Negative source output voltage level: VSNR=-3.1V to -5.8V
 VGH=7.3V to 20V
 VGL=-5.3V to -18V (|VGH-VGL| < 30V)
 VGLO2=-7V to -18V (|VGH-VGLO2| < 30V)
 VCOM=-4V to +1V, a step=10mV

Himax Confidential -P.12-

 External charge Pump: Support HX5186-C mode

 PFM booster: Support typeA/C/D
 External Power mode support:
1. VSP + VSN + VDD1
2. VSP + VSN + VDD1 + VDD3
3. VSP + VSN + VGH + VGL + VDD1

2.4 Display / Control interface

 Display interface types supported

 MIPI-DSI (Display Serial Interface) interface
 Support DSI Version 1.01.00
 Support D-PHY Version 1.1
 Support DCS Command Version 1.01.00
 Support DSI 2, 3 or 4 data lanes.
 MIPI-DSI + I2C interface
 MIPI-DSI + DBI TypeC(Option1/Option3) interface

2.5 Input power

 I/O and Logic power supply (VDD1): 1.65V to 3.6V

 Analog power supply (VDD3): 2.5V to 3.6V
 High speed interface power supply (HS_VCC): 1.65V to 3.6V
 Positive source driver power (External input mode VSP): 4.5 to 6V
 Negative source driver power (External input mode VSN): -4.5 to -6V

2.6 Miscellaneous

 Software programmable color depth mode

 Oscillator for display clock generation
 GAS function for preventing image sticking when abnormal power off
 Support DC COM driving
 On-chip OTP program voltage generator
 OTP memory to store initialization register settings
 3 times MTP for VCOM and ID setting
 Support CABC (Content Adaptive Brightness Control) function
 Support Color Enhancement function
 Support DGC (Digital Gamma Correction) function
 Support Scaling function
 Support Free Running mode(Internal BIST pattern generator)
 Support Low Frame Rate Display
 Smart source EQ function for power saving
 Temperature Sensor
 Idle mode 1-bit GRAM display
 Operation temperature range: -40 to +85 °C

Himax Confidential -P.13-

3. Device Overview
3.1 Block diagram

TH1/TH0 CABC_PWM_OUT S1 ~ S3240, SD0, SD3241

internal VGH
VDD1
VGH to VPP
VDD3 Regulator

FRM
RESX VPP
IM2~0 3 ABC function
Source
driver
CSX OTP
DCX
SPI I/F
SCL
I2C I/F
SDI_SDA Tyemperature D/ A Converter
SDO Sensor circuit

DB23~0 24
VSYNC RGB I/F Digital
HSYNC Data Latch
24-bit Gamma
PCLK
for test Correction
DE
V0~255 VSOUT
PNSWAP Grayscale voltage
DSWAP1~0 generator HSOUT
2 Instruction
HS_CLKP Control GPO1~3
HS_CLKN 2 CABC function
HS_D0P TS7~0
HS_D0N 2
HS_D1P DSI I/F Gamma adjusting circuit VTESTOUTP /
HS_D1N 2 VTESTOUTN
HS_D2P
HS_D2N 2
TE
HS_D3P Timing
HS_D3N 2 Control TE1
HS_VCC
HS_VSS
LV_DETEC Gate CGOUTL_1~20
IMAGE_UPDATE Control CGOUTR_1~20
Generator 40
Unit
OSC RC OSC Timing
TEST2~0
PCCS2~0
VDD3 DC / DC Converter VCOM Voltage reference
Cricuit
VSSD_P_L/R
VSSA
VSSAC
VSSD
VREF
C42P/C42N
VCSW1
VCSW2

VDDD
VCOM

VSNR
VSN

C31P/C31N

C21P/C21N
C22P/C22N

VSPR
C41P/C41N
VSP

VGH

HS_LDO
VCI_REG
VGL

VGH1_L/R
VGH2_L/R
VGH1_RGND_L/R
VGH2_RGND_L/R
VGLO2

Himax Confidential -P.14-

Interface mode is selected as listed below:

IM2 IM1 IM0 interface mode DB pins
HS_D0P, HS_D0N,
HS_D1P, HS_D1N,
0 0 0 DSI Video mode + I2C HS_D2P, HS_D2N,
HS_D3P, HS_D3N,
SDA
0 0 1 Reserved Reserved
HS_D0P, HS_D0N,
HS_D1P, HS_D1N,
0 1 0 DSI Video mode + DBI TypeC Option1 HS_D2P, HS_D2N,
VDD1 / HS_D3P, HS_D3N,
IM2 ~ IM0 I 3
VSSD SDI, SDO
HS_D0P, HS_D0N,
HS_D1P, HS_D1N,
0 1 1 DSI Video mode + DBI TypeC Option3 HS_D2P, HS_D2N,
HS_D3P, HS_D3N,
SDI, SDO
1 0 0 Reserved Reserved

1 0 1 Reserved Reserved
HS_D0P, HS_D0N,
HS_D1P, HS_D1N,
1 1 0 DSI Video mode
HS_D2P, HS_D2N,
HS_D3P, HS_D3N
Pixel format (RGB565 / RGB666 / RGB888) is selected by DCS command (0x3Ah).
This pin is used for free running mode.
If not use, please connect it to VSSD.
FRM I 1 MPU FRM Free Running Mode
Low Disable
High Enable
These pins must be connected to VDD1 or VSSD to set 1 or 0.
PNSWAP and DSWAP1~0 are used for the combination of polarity swap and data
lane swap of DSI.
PNSWDSWAP HS_ HS_ HS_ HS_ HS_ HS_ HS_ HS_ HS_ HS_
AP [1:0] D2P D2N D1P D1N CKP CKN D0P D0N D3P D3N
PNSWAP, VDD1 / 00 D3- D3+ D2- D2+ CLK- CLK+ D1- D1+ D0- D0+
I 3 01 D3- D3+ D0- D0+ CLK- CLK+ D1- D1+ D2- D2+
DSWAP1~0 VSSD 0
10 D0- D0+ D1- D1+ CLK- CLK+ D2- D2+ D3- D3+
11 D2- D2+ D1- D1+ CLK- CLK+ D0- D0+ D3- D3+
00 D3+ D3- D2+ D2- CLK+ CLK- D1+ D1- D0+ D0-
01 D3+ D3- D0+ D0- CLK+ CLK- D1+ D1- D2+ D2-
1
10 D0+ D0- D1+ D1- CLK+ CLK- D2+ D2- D3+ D3-
11 D2+ D2- D1+ D1- CLK+ CLK- D0+ D0- D3+ D3-

Chip select pin.

Low: Chip can be accessed.
CSX I 1 MPU
High: Chip can not be accessed.
If not use, please connect it to VSSD or VDD1.
MPU or Reset pin. Setting either pin low initializes the LSI. Must be reset after
RESX I 1
reset circuit power is supplied (Must be connected to VSSD or VDD1).
Command/parameter selection for DBI TypeC Option3.
DCX I 1 MPU
If not use, please connect it to VSSD or VDD1.
Serves as serial clock in serial bus interface.
SCL I 1 MPU Serves as serial iput/output clock in I2C interface.
If not use, please connect it to VSSD or VDD1.
SDO O 1 MPU Serial data output pin.
If not used, let it open .
I 3 MPU SDI: Serial data input pin in serial bus interface.
SDI_SDA
SDA: Serial input/output data in I2C bus interface.
Himax Confidential -P.15-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
If not use, please connect it to VSSD or VDD1.
Only for internal test.
DB23~0 I 24 MPU
Let the unused pins open or connect it to VSSD or VDD1.
Only for internal test.
HSYNC I 1 MPU
Let the unused pins connect it to VSSD or VDD1.
Only for internal test.
DE I 1 MPU
Let the unused pins connect it to VSSD or VDD1.
Only for internal test.
VSYNC I 1 MPU
Let the unused pins connect it to VSSD or VDD1.
Only for internal test.
PCLK I 1 MPU
Let the unused pins connect it to VSSD or VDD1.
Low voltage detection input signal.
LV_DETEC I 1 MPU Input : VDD1 ~ VSSD
If not used, please connect to VSSD or open.
External Temperature Sensor input VSSD or VDD1.
TH0/TH1 I 3/3 MPU
If not used, please connect to VSSD or open.
Source driver output pins
Output voltages applied to the liquid crystal. If source output less than
3240, please let unused source pins open.
H_RES[2:0] Resolution Source channels
000 1080RGB x (528 + 8xNL) S1 ~ S3240
001 1024RGB xdot
(528 + 8xNL) S1 ~ S1536 , S1705 ~ S3240
S1 to S3240 O 3240 LCD dot
010 960RGB x (528 + 8xNL) S1 ~ S1440 , S1801 ~ S3240
dot
011 900RGB x (528 + 8xNL) S1 ~ S1350 , S1891 ~ S3240
dot
100 800RGB x (528 + 8xNL) S1 ~ S1200 , S2041 ~ S3240
dot
101 720RGB x (528 + 8xNL) S1 ~ S1080 , S2161 ~ S3240
dot
SD0 and SD3241 are used for Zig-Zag and Zig-Zag2 inversion.
SD0, SD3241 - 1,1 LCD
If not used, let it open.
Gate Driver control singal
These are pins are a-Si TFT control signal, the function can be selected by
CGOUTL_1~20,
O 20,20 LCD register setting.
CGOUTR_1~20
These pins output high/low level VGH/VGL.
GIP_RGNDG1_L, Discharge GIP discharge path. Connect a resistor to VSSD on FPC.
O 2
GIP_RGNDG2_R resistor If not use, please connect it to VSSA.
Power supply pins
Power
VDD1 I 21 A power supply for the I/O circuit and logic power. VDD1=1.65 to 3.6V
supply
Power
VDD3 I 18 A power supply for the analog power. VDD3=2.5V to 3.6V
supply
Power Analoge ground. VSSA=0V. When using the COG method, connect to
VSSA P 32
supply VSSD on the FPC to prevent noise.
Power
VSSAC P 5 Analoge ground. Must connect to VSSA on the FPC.
supply
Power Logic Ground. VSSD=0V. When using the COG method, connect to VSSA
VSSD P 24
supply on the FPC to prevent noise.
VSSD_P_L, 7, Power Charge pump gorund, VSSD_P=0V. When using the COG method,
P
VSSD_P_R 11 supply connect to VSSA on the FPC to prevent noise.
Power supply and Stabilization pins
Stabilizing
VSP I 43 Input voltage generated from HX5186, PFM or external (4.5V to 6.0V).
capacitor
Stabilizing
VSN I 43 Input voltage generated from HX5186, PFM or external (-4.5V to -6.0V).
capacitor
Stabilizing VCI_REG output pin.
VCI_REG O 46
capacitor Need to connect to a stabilizing capacitor.
VSPR O 1 Open Positive regulated voltage output (3.1V to 5.8V) for Gamma.

VSNR O 1 Open Negative regulated voltage output (-3.1V to -5.8V) for Gamma.
Stabilizing
VDDD O 24 Internal logic voltage output.
capacitor
Stabilizing Output voltage from the step-up circuit.
VGH O 15
capacitor Connect to a stabilizing capacitor between VSSA and VGH.

Himax Confidential -P.16-

Detail connection, please refer to DC/DC conveter circuit

CABC & General purpose output
Backlight on/fff control pin. If use CABC function, the pin can connect to
CABC_PWM_OUT O 1 LED driver
external LED driver IC. The output voltage range=0 to VDD1.
TE O 1 - Serves TE (Tearing Effect ) output pin.
TE1 O 1 - Serves TE (Tearing Effect ) pin of each scan line.
High speed interface parts
HS_D0P, MIPI-DSI Data differential signal input pins. (Data lane 0)
I/O 6,6 DSI Host
HS_D0N if not used , Please connected to VSSD or open..

HS_CLKP, MIPI-DSI CLOCK differential signal input pins.

I 6,6 DSI Host
HS_CLKN if not used , Please connected to VSSD or open..

HS_D1P, MIPI-DSI Data differential signal input pins. (Data lane 1)

I 6,6 DSI Host
HS_D1N if not used , Please connected to VSSD or open.

HS_D2P, MIPI-DSI Data differential signal input pins. (Data lane 2)

I 6,6 DSI Host
HS_D2N if not used , Please connected to VSSD or open..

Himax Confidential -P.17-

HSOUT O 1 Open A test pin. Disconnect it. This pin can output on FPC.

GPO1~3 O 3 Open A test pin. Disconnect it.

DUMMY1~122 - 122 Open Not used. Let it open.

Himax Confidential -P.18-

The HX8398-A supports I2C interface and MIPI interfaces: DBI (Display Bus
Interface), DSI (Display Serial Interface). Where DBI supports Serial interface (Type C
Option1 and Option3). The interface mode can be selected by IM2-0 pins setting as
show in Table 4.1.

IM2 IM1 IM0 interface mode DB pins Note

0 0 0 DSI Video mode + I2C SDA, HS_D0P/N~HS_D3P/N -
0 1 0 DSI Video mode + DBI TypeC Option1 SDI, SDO, HS_D0P/N~HS_D3P/N -
0 1 1 DSI Video mode + DBI TypeC Option3 SDI, SDO, HS_D0P/N~HS_D3P/N -
1 1 0 DSI Video mode HS_D0P/N~HS_D3P/N -
Other setting Reserved Reserved -
Table 4.1: Interface selection

Interface CSX SCL DCX

Input/Output pin
SDA,
HS_CLKP, HS_CLKN,
HS_D0P, HS_D0N,
DSI Video mode + I2C CSX SCL Unused
HS_D1P, HS_D1N,
HS_D2P, HS_D2N,
HS_D3P, HS_D3N
SDI, SDO,
HS_CLKP, HS_CLKN,
DSI Video mode + DBI TypeC HS_D0P, HS_D0N,
CSX SCL Unused
Option1 HS_D1P, HS_D1N,
HS_D2P, HS_D2N,
HS_D3P, HS_D3N
SDI, SDO,
HS_CLKP, HS_CLKN,
DSI Video mode + DBI TypeC HS_D0P, HS_D0N,
CSX SCL DCX
Option3 HS_D1P, HS_D1N,
HS_D2P, HS_D2N,
HS_D3P, HS_D3N
HS_CLKP, HS_CLKN,
HS_D0P, HS_D0N,
DSI Video mode Unused Unused Unused HS_D1P, HS_D1N,
HS_D2P, HS_D2N,
HS_D3P, HS_D3N
Table 4.2: Pin connection based on different interface

Himax Confidential -P.19-

The HX8398-A supports two type serial data transfer interface, the interface selection
by setting IM2-0 pins. The IM2-0 set “010” is select 3-wire Option1 serial bus. The
IM2-0 is set “011” when select 4-wire Option3 serial bus.

The 3-wire serial bus is use: chip select line (CSX), serial input/output data (SDI and
SDO) and the serial transfer clock line (SCL).The 4-wire serial bus is use: chip select
line (CSX), data/command select (DCX), serial input/output data (SDI and SDO) and
the serial transfer clock line (SCL).

4.2.1 Serial data write mode

The 3-pin serial data packet contains a control bit D/CX and a transmission byte and
in 4-pin serial case, data packet contains just transmission byte and control signal
D/CX is transferred by DCX pin. If DCX is low, the transmission byte is command byte.
If D/CX is high, the transmission byte is stored in to command register. The MSB is
transmitted first. The serial interface is initialized when CSX is high. In this state, SCL
clock pulse or serial input/output data (SDI and SDO) have no effect. A falling edge on
CSX enables the serial interface and indicates the start of data transmission.

DBI Type C: Interface protocol–Option 1 (3-wire)

CSX

SCL

SDI 0 D7 D6 D5 D4 D3 D2 D1 D0 D/CX D7 D6 D5 D4 D3 D2 D1 D0

Command Command / parameter

DBI Type C: Interface protocol Option 3 (4-wire)

CSX

SCL

SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Command parameter
DCX

Figure 4.1: DBI Type C: Serial interface protocol 3-wire/4-wire, write mode

Himax Confidential -P.20-

The micro-controller first has to send a command and then the following byte is
transmitted in the opposite direction. The 3-wire serial read data format which just
needs 8-bit.

DBI Type C: Interface protocol–Option 1 (3-wire)

CSX

SCL

0 D7 D6 D5 D4 D3 D2 D1 D0
SDI
Command

D7 D6 D5 D4 D3 D2 D1 D0
SDO
READ DATA

DBI Type-C Interface Protocol – Option 3 (4 wire)

CSX

SCL

DCX

SDI D7 D6 D5 D4 D3 D2 D1 D0

Command
SDO D7 D6 D5 D4 D3 D2 D1 D0

READ DATA

Figure 4.2: Type C:Serial interface protocol 3-wire/4-wire read mode

If there is a break on data transmission when transmit a command before a whole byte
has been completed, then the display module will have reset the interface such that it
will be ready to receive the same byte re-transmitted when the chip select line (CSX) is
next activated. See the following figure.

Break
Command /Parameter Command / Parameter
CSX

Host D\CX D7 D6 D5 D4 D\CX D7 D6 D5 D4 D3 D2 D1 D0

SDI

SCL

Figure 4.3: Display module data transfer recovery

If one or more parameter command is being sent and a break occurs while sending
any parameter before the last one and if the host then sends a new command rather
than retransmit the parameter that was interrupted, then the parameters that were
successfully sent are stored and the parameter where the break occurred is rejected.
The interface is ready to receive next byte as shown:
Himax Confidential -P.21-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
1. Middle of frame Break

Parameter 2
Parameter 1 (The old value is
Command 1 Command 2
(Stored to register) kept on the
register)

2. Between frame
Without break

Parameter 1 Parameter 2 Parameter 3

Command 1
(Stored to register) (Stored to register) (Stored to register)

With break
Parameter 2 Parameter 3
Parameter 1
Command 1 (The old value is kept (The old value is
(Stored to register)
on the register) kept on the register)

Break Parameter 1 of
Command 2 Command 2

Figure 4.4: Break During Parameter

The host processor can pause a write sequence by pulling the CSX signal high
between command or data bytes. The display module shall wait for the host
processor to drive CSX low before continuing the write sequence at the point where
the sequence was paused.

Pause
Command /Parameter Command / Parameter
CSX

Host D4 D3 D2 D1 D0 D\CX D7 D6 D5 D4 D3 D2 D1 D0
SDI

SCL

Figure 4.5: Display Module Data Transfer Pause

There are 4 cases where there is possible to see this kind of pause:

1. Command – Pause – Command

2. Command – Pause – Parameter

3. Parameter – Pause – Command

4. Parameter – Pause – Parameter

Himax Confidential -P.22-

The HX8398-A supports I2C interface, the interface selection by setting IM[2:0] pins.
The IM[2:0] set “000” is select I2C interface.

I2C interface 2 hardware pin – serial data (SDA) and serial clock (SCL), carry
information between the devices connected to the bus. Each device is recognized by
a unique address — whether it’s a microcontroller, LCD driver, memory or keyboard
interface — and can operate as either a transmitter or receiver, depending on the
function of the device. Both SDA and SCL are needed connected to a positive supply
voltage via a pull-up resistor. The pull-up resistor should connect to VDD1. When the
bus is free, both lines are HIGH.

MICRO- LCD STATIC

CONTROLLER DRIVER RAM OR
A EEPROM

SDA

SCL

MICRO-
GATE CONTROLLER
ARRAY ADC B

Figure 4.6: I2C connection diagram

4.3.1 I2C protocol

The data on the SDA line must be stable during the HIGH period of the clock. The
HIGH or LOW state of the data line can only change when the clock signal on the SCL
line is LOW.

SDA

SCL
DATA LINE CHANGE
STABLE: OF DATA
DATA VALID ALLOWED

2
Figure 4.7: I C Signal timing

Within the procedure of the I2C-bus, unique situations arise which are defined as
START and STOP conditions. A HIGH to LOW transition on the SDA line while SCL is
HIGH is one such unique case. This situation indicates a START condition. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START
and STOP conditions are always generated by the master. The I 2C bus is considered
to be busy after the START condition. The I2C bus is considered to be free again a
certain time after the STOP condition.

Himax Confidential -P.23-

SDA

SCL
S P
START STOP
CONDITION CONDITION

2
Figure 4.8: I C START/STOP

Every byte put on the SDA line must be 8-bits long. The number of bytes that can be
transmitted per transfer is unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant bit (MSB) first.

SDA
MSB ACKNOWLEDGEMENT ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER SIGNAL FROM RECEIVER

SCL 1 2 7 8 9 1 2 3-8 9
S P
ACK
START STOP
BYTE COMPLETE, CLOCK LINE HELD LOW
CONDITION CONDITION
INTERRUPT WITHIN RECEIVER WHILE INTERRUPTS ARE SERVICED

2
Figure 4.9: I C data transfer

4.3.2 I2C slave address

HX8398-A support many slave address could be select by register setting in RE8h.
The slave address is defined a follow table.

I2C_SA[6 :0] Slave address (A6-A0)

000_0000 000_0000
000_0001~000_0111 Reserved
000_1000 000_1000
: :
111_0110 111_0110
111_0111 111_0111
111_1xxx Reserved
2
Table 4.3: I C Slave Address table

Himax Confidential -P.24-

HX8398-A support I2C to write data to register. The write flow is described as below
1. Send Start condition followed by I2C 7 bits slave address and 1 bit ‘0’(write flag)
2. Sned High byte of 16bits address, then IC feedback Ack.
3. Sned Low byte of 16bits address, then IC feedback Ack.
4. Sned 8bits register data, MSB first , ADD[7] send first, the IC feedback Ack
5. Send Stop condition

S la v e A D D [1 5 ]… A D D [7 ]…
S R /W A A A D [7 ]... D [0 ] A P
A d d re s s A D D [8 ] A D D [0 ]
[6 ..0 ]
‘0 ’( W r ite )

F r o m m a s te r to s la v e r A = A c k n o w le d g e ( S D A = L o w )

A = N o t a c k n o w le d g e ( S D A = H ig h )
F r o m s la v e r to m a s te r
S = S ta r t c o n d itio n

M a s te r e x : M P U ,D S P ...c o n tr o l c h ip P = S to p c o n d itio n

S la v e a d d r e s s R /W A6 A5 A4 A3 A2 A1 A0 R /W

7 b it fo r a d d r e s s + 1 b it fo r R /W

r e g is te r a d d r e s s AD15 AD 14 AD13 AD12 AD11 AD 10 AD 9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

1 6 b it fo r r e g is te r a d d r e s s

r e g is te r s e ttin g D7 D6 D5 D4 D3 D2 D1 D0

8 b it fo r r e g is te r s e ttin g

Start Stop
ACK ACK ACK ACK

SCL
SA SA ADD ADD ADD ADD D D
W
[6] [0] [15] [8] [7] [0] [7] [0]
SDA Slave Address Register Address Register Address Register
High Byte Low Byte Parameter

2
Figure 4.10: I C interface register write flow

Himax Confidential -P.25-

HX8398-A also support I2C to read data from register. The write flow is described as
below
1. Send Start condition followed by I2C 7 bits slave address and 1 bit ‘0’(write flag)
2. Sned High byte of 16bits address, then IC feedback Ack.
3. Sned Low byte of 16bits address, then IC feedback Ack.
4. Send restart condition followed by I2C 7 bits slave address and 1 bit ‘1’(read flag)
5. IC send register data to baseband, and followed by an non-ack.
6. Send Stop condition

S la v e A D D [1 5 ]… A D D [7 ]… S la v e
S 0 A A A Sr 1 A R e a d D a ta A P
A d d re s s A D D [8 ] A D D [0 ] A d d re s s

A = A c k n o w le d g e ( S D A = L o w )
F r o m m a s te r to s la v e r
A = N o t a c k n o w le d g e ( S D A = H ig h )
F r o m s la v e r to m a s te r
S = S ta r t c o n d itio n
M a s te r ? e x : M P U ,D S P ...c o n tr o l c h ip
P = S to p c o n d itio n
S r = R e S ta r t

S la v e a d d r e s s R /W A6 A5 A4 A3 A2 A1 A0 R /W

7 b it fo r a d d r e s s + 1 b it fo r R /W

r e g is te r a d d r e s s AD 15 AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

1 6 b it fo r r e g is te r a d d r e s s

ReStart
Start Stop
ACK ACK ACK ACK

SCL
SA SA ADD ADD ADD SA SA D D
W [15] ADD R
[6] [0] [8] [7] [0] [6] [0] [7] [0]
SDA
Slave Address Register Address Register Address Slave Address Readback Data
High Byte Low Byte

N-ACK

2
Figure 4.11: I C interface register read flow

Himax Confidential -P.26-

4.4 DSI system interface

The DSI specifies the interface between a host processor and a peripheral such as a
display module. Figure 4.12 shows a simplified DSI interface. From a conceptual
viewpoint, a DSI-compliant interface also sends pixels or commands to the peripheral,
and can read back status or pixel information from the peripheral. The main difference
is that DSI serializes all pixel data, commands, and events that. DSI-compliant
peripherals support Command Mode. Which mode is used depends on the
architecture and capabilities of the peripheral. The mode definitions reflect the
primary intended use of DSI for display.

Command Mode refers to operation in which transactions primarily take the form of
sending Commands and data to a peripheral, such as a display module, that
incorporates a display controller. Systems using Command Mode write to, and read
from, the registers. The host processor indirectly controls activity at the peripheral by
sending commands, parameters and data to the display controller. The host
processor can also read display module status information. Command Mode
operation requires a bidirectional interface.

Host Device, e.g. an Application Peripheral, e.g. a Display containing the

Processor or Baseband Processor DSI receiver
containing DSI Transmitter
Bi-directional High
DSI Transmitter Speed Data Links DSI Receiver
D0P D0P
D0N D0N

D1P D1P
D1N D1N
D2P D2P
D2N D2N
D3P D3P
D3N D3N
CLKP CLKP
CLKN CLKN

Figure 4.12: DSI transmitter and receiver interface

Please refer to “DRAFT MIPI Alliance Standard for DSI” for DSI detailed specifications.
The data lane number select by internal register(RBAh).

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According Figure 4.13 DSI transmitter and Receiver interface to understand simple
interface block diagram. Then under diagram is internal block for DSI which include
four types: PHY Layer, Lane Management Layer, Low level protocol and Application
Layer.

The PHY Layer specifies the characteristics of transmission medium and electrical
parameters for signaling the timing relationship between clock and Data Lanes.

The Lane Management Layer specifies DSI is Lane-scalable for increased

performance. The data signals maybe transmission through one or more channel
depending on the bandwidth requirements of the application.

The Protocol Layer specifies at the lowest level, DSI protocol specifies the sequence
and value of bits and bytes traversing the interface. It specifies how bytes are
organized into defined groups called packets.

The Application Layer describes higher-level encoding and interpretation of data

contained in the data stream. The DSI specification describes the mapping of pixel
values, commands and command’s parameters to bytes in the packet assembly.

Transmitter Side Receiver Side

Pixel to Byte Packing Formats Application
Application Command Generation / Interpretation
Pixel Control Control Pixel

Data Control Control Data

Packet Based Protocol
Low Level Protocol ECC and Checksum Generation and Testing
Low Level Protocol
Data Control Control Data
8-bits 8-bits
TX: Distribute data to 1, 2, 3 or 4 lanes
Lane Management Layer Lane Distribution and Merging Lane Management Layer

8-bits 8-bits
Data0 Control Start of Packet / End of Pack Control
Serializer / Desserializer
PHY Layer Colock Management (DDR) PHY Layer
Electrical Layer (SLVS)
D-PHY interface High Speed Unidirectional Clock
module (DIM)
-
Lane 0 High Speed Unidirectional Data (optionally Bidirectional in LP Mode)
Lane 1 High Speed Unidirectional Data
Lane 2 High Speed Unidirectional Data
Lane 3 High Speed Unidirectional Data

Figure 4.13: DSI transmitter and receiver interface

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The HX8398-A uses Data Lane and Clock Lane differential pairs for DSI. Both
differential lane pairs can be driven LP (Low Power) or HS (High Speed) mode.

LP mode means each line of the differential pairs are used in independently and
single-ended. In LP mode differential receiver is disable( termination resistor of the
receiver is disable). In LP mode there are four possible Low-Power Lane states
(LP-00, LP-01, LP-10, LP-11).

HS mode means the differential pairs are not used in single-end and termination
resistor of the receiver is enable. There are different modes and protocol in each
mode when transfer display data frim MCU to the display module.

The state code of HS and LP Lane pair are defined as below:

Line Voltage Levels High-Speed Low-Power

State Code
Dp-Line Dn-Line Burst Mode Control Mode Escape Mode
HS-0 HS Low HS High Differential-0 Note1 Note1
HS-1 HS High HS Low Differential-1 Note1 Note1
LP-00 LP Low LP Low N/A Bridge Space
LP-01 LP Low LP High N/A HS-Rqst Mark-0
LP-10 LP High LP Low N/A LP-Rqst Mark-1
LP-11 LP High LP High N/A Stop Note2
Note1: During High-Speed transmission the Low-Power Receivers observe LP-00 on the
Lines.
Note2: If LP-11 occurs during Escape mode the Lane returns to Stop state (Control Mode
LP-11)

Himax Confidential -P.29-

Figure 4.14 shows the state diagram for Clock Lane Mode. The Clock Lane has three
different power modes: Low Power Stop State, Ultra Low Power State(ULPS) and
High Speed clock transmission.

Enter LP Stop State:

Init Master or Slave
Master or Slave
Enter ULPS:

Enter HS transmission mode:

ULPS
BRIDGE HS-REQ Stop BRIDGE
ENTER
LP-00 LP-01 LP-11 LP-00
LP-10

CLOCK ULPS
EXIT ULPS
HS-0 HS-1 TRAIL
LP-10 LP-00
HS-0

HS CLOCK
transmission
Figure 4.14: Clock Lane Mode State diagram

Clock Lane can be driven LP-11 to enter Low Power Stop State. There are three ways
to enter Lower Power Stop State:

(1) After Initial state(HW reset, SW reset, Power on sequence).

(2) Leaving ULPS: ULPS LP-00 -> LP-10 -> Low Power Stop State LP-11.

Twakeup HS_CLKP
HS_CLKN

ULPS LP-10 LP Stop

LP-00 LP-11

(3) Leaving HS clock transmission mode: HS mode (HS-0 or HS-1) -> HS-0 -> Low
Power Stop State LP-11.

LP Stop
LP-11
TCLK-TRAIL HS_CLKP
HS transmission
HS_CLKN
HS-0 or HS-1 HS-0

Himax Confidential -P.30-

HS_CLKP
HS_CLKN

LP Stop ULPS
LP-10
LP-11 LP-00

Clock Lane can be High Speed Clock transmission State from Low Power Stop State.
The flow is Low Power Stop State LP-11 -> LP-01 -> LP-00 -> HS-0/1.

TLPX

TCLK-ZERO HS clock
transmission HS_CLKP
TCLK-TERMEN
HS-0 HS_CLKN
HS-0 or HS-1

LP Stop
LP-01 LP-00
LP-11

Himax Confidential -P.31-

Figure 4.15 shows the operational flow diagram for Data Lane Mode. There are three
operating modes in Data Lane: Escape mode, High-Speed transmission mode and
Turnaround.

TX Trigger
Init Master Escape
ULP
LPDT Mode

LP-00>01>00

HS-Prpr HS-Rqst STOP LP-Rqst

LP-00 LP-01 LP-11 LP-10

Turnaround
SoT HST EoT
LP-00>10>00>10

RX Trigger
Init Master Escape
ULP
Wait Mode
LPDT
LP-00>01>00

HS-Prpr HS-Rqst STOP LP-Rqst

LP-00 LP-01 LP-11 LP-10

Turnaround
SoT HST EoT
LP-00>10>00>10

Figure 4.15: Data Lane Mode State diagram

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Data Lane0 is used in Escape Mode when data lane in LP mode. Data Lane shall
enter Escape mode via LP-11 -> LP-10 -> LP-00 -> LP-01 -> LP-00 and exit Escape
mode via LP-10 -> LP-11.

TX Stop LP-11 RX Stop

TX LP-Rqst LP-10 RX LP-Rqst

TX LP-Yield LP-00 RX LP-Yield

TX Esc-Rqst LP-01 RX Esc-Rqst

TX Esc-Go LP-00 RX Esc-Go

TX Esc-Cmd Command RX Esc-Cmd

TX Triggers RX Triggers

LP-10 TX Mark RX Wait

TX ULPS LP-00 RX ULPS

TX LPDT LP-Data RX LPDT

Figure 4.16: Escape Mode State Machine

Once Escape mode is entered, the transmitter shall send an 8-bit entry code to
indicate the requested action. The Entry Code as follows:

(1) Trigger (Reset-Trigger(46h), Tearing effect(BAh), Acknowledge(84h))

(2) Drive Data Lane to Ultra Low Power State(78h)
(3) Send Low Power Data Transmission(87h)

Himax Confidential -P.33-

HS_DP
HS_DN

LP-11 LP-10 LP-00 LP-01 LP-00 LP-00 LP-10 LP-11

Escape Entry Code

ULPS(78h)

LPDT(87h)

Reset-Trigger(46h)

Tearing Effect
(BAh)

Acknowledge(84h)

Figure 4.17: Escape Mode timing sequence

Himax Confidential -P.34-

The display module can enter High Speed Data Transimission when Clock Lane in the
High Speed Clock Mode. All Data Lane enter High Speed Data Tranmission
synchronously but may end at different time. Data Lane enter High Speed Data
Transmission flow: LP-11 -> LP-01 -> LP-00 -> SoT(0001_1101). And exit High Speed
Data Transmission flow: Toggles differential state immediately after last payload data
bit and keeps that state for a time T HS  TRAIL .

TX Stop LP-11 RX Stop

TX HS-Rqst LP-01 RX HS-Rqst

RX HS-Prpr
TX HS-Prpr LP-00
RX HS-Term

TX HS-Run
HS-0 RX HS-Run
Sub-state TX HS-Go
Sub-state
machine
machine

TX HS-Sync HS-00011101 RX HS-Sync

TX HS-0 TX HS-1 HS-0 HS-1 RX HS-0 RX HS-0

TX HS-1 TX HS-0 HS-1 HS-0

Figure 4.18: High Speed Data Transmission State Machine

CLK

D(0~3)p/
TLPX THS- THS-ZERO THS-SYNC
D(0~3)n PREPARE

HS-00011101 Disconnect
Terminator
VIH(min)

VIL(max) HSDT HS-0 or HS-1

HS-0
Capture
LP-11 LP-01 LP-00 1st Data Bit
TEOT LP-11
THS-TRAIL THS-EXIT

Figure 4.19: High Speed Data Transmission timing sequence

Himax Confidential -P.35-

Parameter Description Min. Typ. Max. Unit

Time that the transmitter drives the Data

Lane LP-00 Line state immediately
THS-PREPARE 40+4*UI - 85+6*UI ns
before the HS-0 Line state starting the
HS transmission.
THS-PREPARE + time that the
THS-PREPARE+ transmitter drives the HS-0 state prior to 145+10*UI - - ns
THS-ZERO transmitting the Sync sequence.
Transmitted time interval from the start of
TEOT THS-TRAIL or TCLK-TRAIL, to the start - - 105ns+12*UI ns
of the LP-11 state following a HS burst.
Time that the transmitter drives the
THS-TRAIL flipped differential state after last payload 60ns+4*UI - - ns
data bit of a HS transmission burst.
Time that the transmitter drives LP-11
THS-EXIT following a HS burst. 100 - - ns

Table 4.4: Global Operation Timing Parameters for Data Lane

Clock Lane Disconnect

CLKp/CLKn Terminator
TCLK-POST TEOT
VIH(min)

VIL(max)

TCLK-TRAIL THS-EXIT TLPX TCLK-ZERO TCLK-

TCLK-
PRE
PREPAR THS-
E TLPX PREPAR
Disconnect E
Data Lane Terminator
D(0~3)p/D(0~3)n
VIH(min)

VIL(max)

Figure 4.20: Switching the Clock Lane between Clock Transmission and LP Mode

Parameter Description Min. Typ. Max. Unit

Time that the transmitter continues to

send HS clock after the last associated
TCLK-POST 60+52*UI - - ns
Data Lane has transitioned to LP Mode.

Time that the transmitter drives the

TCLK-TRAIL flipped differential state after last payload 60 - - ns
data bit of a HS transmission burst.

Time that the HS clock shall be driven by

the transmitter prior to any associated
TCLK-PREPARE 38 - 95 ns
Data Lane beginning the transition from
LP to HS mode.

Himax Confidential -P.36-

Himax Confidential -P.37-

The transmission direction od a bi-directional Data Lane can be swapped by means of

a Link Turnaround procedure. This procedure enables information transfer in the
opposite direction of the current direction. The procedure is the same for either a
change from Forward-to-Reverse direction or Reverse-to-Forward direction.

TX Stop LP-11 RX Stop

TX LP-Rqst LP-10 RX LP-Rqst

TX LP-Yield LP-00 RX LP-Yield

TX TA-Rqst LP-10 RX TA-Rqst

TX TA-Go LP-00 RX TA-Wait

LP-00 RX TA-Get

RX TA-Look LP-00

RX TA-Ack LP-10 TX TA-Ack

RX StopT LP-11 TX Stop

Figure 4.21: Turnaround State Machine

HS_DP
Master Drive HS_DN
4TLPX
TLPX TLPX TLPX TTA-GO

Drive
overlap
2~3TLPX

LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 LP-00 LP-10 LP-11

TTA-SURE TTA-GET TLPX TLPX
5TLPX
1~2TLPX Slave Drive
Note: TLPX(Master)/TLPX(Slave) between 2/3~3/2
Figure 4.22: Turnaround timing sequence

Himax Confidential -P.38-

The protocol layer appends packet-protocol information and headers. The receiver
side of a DSI Link performs the converse of the transmitter side, decomposing the
packet into parallel data, signal events and commands. The DSI protocol permits
multiple packets which is useful for events such as peripheral initialization, where
many registers may be loaded separate write commands at system startup. Figure
4.23 illustrates multiple HS Transmission packets.

LPS SOT SP EOT LPS SOT SP EOT LPS SOT LP EOT LPS

LPS：Low power state

SOT：Start of Transmission
SP：Short Packet
LP：Long Packet
EOT：End of Transmission

Figure 4.23: Multiple HS transmission packets

The packet includes two types which are Long packet and short packet. The first byte
of the packet, the Data Identifier (DI), includes information specifying the length of the
packet.

Short packets shall contain an 8-bit Data ID followed by two command or data bytes
and an 8-bit ECC; a Packet Footer shall not be present. Short packets shall be four
bytes in length. Figure 4.24 shows the structure of the Short packet.
Data ID
Data 0
Data 1

Data 5
Data 6
ECC

LPS SOT EOT LPS

Packet Header
(PH)
DI(Data ID)：Contain Virtual Channel Identifier and Data Type.
ECC(Error Correction Code)：The Error Correction Code allows single-bit errors to
be corrected and 2-bit errors to be detected in the Packet Header.

Figure 4.24: Structure of the short packet

Himax Confidential -P.39-

Where 65,541 bytes = (216-1) + 4 bytes PH + 2 bytes PF

Word count

Data Wc-2

Data Wc-1

Checksum
Data ID

Data 0

Data 1

16-bit
(WC)

LPS SOT ECC EOT LPS

Packet Packet Data Packet Footer

Header (Payload) (PF)
(PH)

DI (Data ID)：Contain Virtual Channel Identifier and Data Type.

WC (Word Count)：The receiver use WC to define packet end.
ECC (Error Correction Code)：The Error Correction Code allows single-bit errors to
be corrected and 2-bit errors to be detected in the Packet Header.
PF(Packet Footer)：Mean 16-bit Checksum.

Figure 4.25: Structure of the long packet

According to packet form, basic elements include DI and ECC. Figure 4.26 the shows
format of Data ID.

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

VC (Virtual Channel) DT (Data Type)

DI[7:6]  These two bits identify the data as directed to one of four virtual channels.
DI[5:0]: These six bits specify the Data Type, which specifies the size, format and, in
some cases, the interpretation of the packet contents.

Figure 4.26: The format of data ID.

Himax Confidential -P.40-

Long packet write Command / Parameters / Pixel Datas

PH
LPS DCS WR CMD / CMD + PAs LPS
SOT DI WC ECC PF EOT
/ CMD+ Pixel DATA

DI  Write suitable Data type.

WC  Write number of Payload Data.
Ex: One CMD write, WC setting as 1.
CMD + PAs write, WC setting as number of (CMD+PAs).
CMD + DATA write, WC setting as number of (CMD + Pixel DATA).

Short packet write Command / Parameters

LPS SOT DI DCS WR CMD / CMD + PAs ECC EOT LPS

DI  Write suitable Data type.

Ex: One CMD write, DI + DCS WR CMD
CMD + PAs write, DI + DCS WR CMD + PAs

Figure 4.27: show Short- / Long-packet transmission command sequence

Himax Confidential -P.41-

The set of transaction types sent from the host processor to a peripheral, such as a
display module, are shown in Table 4.6 Data Types for Processor-sourced Packets.

Data type, hex Data type, binary Description packet Size

01h 00 0001 Sync Event, V Sync Start Short
11h 01 0001 Sync Event, V Sync End Short
21h 10 0001 Sync Event, H Sync Start Short
31h 11 0001 Sync Event, H Sync End Short
08h 00 1000 End of Transmission packet(EoTp) Short
22h 10 0010 Shut Down Peripheral Command Short
32h 11 0010 Turn On Peripheral Command Short
05h 000101 DCS WRITE, no parameter Short
15h 010101 DCS WRITE, 1 parameter Short
06h 00 0110 DCS READ, no parameters Short
37h 11 0111 Set Maximum Return Packet Size Short
09h 00 1001 Null Packet, no data Long
19h 01 1001 Blanking Packet, no data Long
39h 11 1001 DCS Long Write/write_LUT Command Packet Long
0Eh 00 1110 Packed Pixel Stream, 16-bit RGB, 5-6-5 Format Long
1Eh 01 1110 Packed Pixel Stream, 18-bit RGB, 6-6-6 Format Long
Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
2Eh 10 1110 Long
Format
3Eh 11 1110 Packed Pixel Stream, 24-bit RGB, 8-8-8 Format Long
xx 0000 DO NOT USE
X0h and XFh, unspecified -
xx 1111 All unspecified codes are reserved

Table 4.6: Data types for processor-sourced packets

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Sync event (H start, H end, V start, V end), data type=xx 0001 (x1h)
Data type, hex Function description Number of bytes
01h V Sync start, Start of VSA pulse.
11h V Sync End, End of VSA pulse. 4 bytes
21h H Sync Start, Start of HSA pulse. (DI+Data0+Data1+ECC)
31h H Sync End, End of HSA pulse.
Note: V Sync Start and V Sync End event represents the start and end of the VSA, respectively. Similarly H Sync Start
and H Sync End event represents the start and end of the HSA, respectively.

EoT Packet
Data type, hex Function description Number of bytes
08h End of Transmission Packet (EoTp) (08,0F,0F,01)
4 bytes
(DI+Data0+Data1+ECC)

Note: The main objective of the EoTp is to enhance overall robustness of the system during HS transmission mode.
Therefore, DSI transmitters should not generate an EoTp when transmitting in LP mode.

Color Mode Off /On Command

Data type, hex Function description Number of bytes
02h Color Mode Off Packet (02,00,00,0B) 4 bytes
12h Color Mode On Packet (12,00,00,18) (DI+Data0+Data1+ECC)
Note: Color Mode Off is a Short packet command that returns a Video Mode display module from low-color mode to normal
display operation. Color Mode On is a Short packet command that switches a Video Mode display module to a
low-color mode for power saving.

Display status (shutdown command, turn-on command )

Data type, hex Function description Number of bytes
Shutdown Peripheral command that turns off the display in a
22h
Video Mode display for power saving. 4 bytes
Turn On Peripheral command that turns on the display in Video (DI+Data0+Data1+ECC)
32h
Mode display for normal display.
Note: When use shutdown command, interface shall remain powered in order to receive the turn-on, or wake-up, command.

Color mode status (Color Mode On, Color Mode Off)

Data type, hex Function description Number of bytes
05h and 15h DCS Short Write command, 0 or 1 parameter, Data Types = 00 4 bytes
0101(05h), 01 0101 (15h), Respectively. (DI+Data0+Data1+ECC)
NOTE: (1) For write part, If DCS Short Write command, followed by BTA, the peripheral shall respond with ACK when
without error was detected in the transmission (Host  Slave). Unless an error was detected, the peripheral
shall respond with Acknowledge with Error Report.

For example: 05h DCS WRITE for no parameter command set.

05h CMD 0 ECC Ex. 05h, 29h, 00, 1Ch ─ Display On(29h)
For example: 15h DCS WRITE for only one parameter command set.
15h CMD Par ECC Ex. 15h, 36h, 08h, 11h ─ MADCTL(36h)-BGR bit=1

DCS command setting

Data type, hex Function description Number of bytes
DCS Read command, the returned data may be of Short or 4 bytes
06h
Long packet format. (DI+Data0+Data1+ECC)
DCS Long Write/ Write _ LUT Command is used to send larger Up to 65541 bytes
39h blocks of data to a display module that implements the Display ( DI + WC + ECC
Command Set. + DCS CMD.
Himax Confidential -P.43-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
+ Payload DATA + PF )
NOTE: (1) When use DCS Read Command, the Set Max Return Packet Size command will limit the size of returning
packets.
(2) The peripheral shall respond to DCS Read Command Request in one of the following ways:
◆ If an error was detected by the peripheral, it shall send Acknowledge with Error Report. So the peripheral
shall transmit the requested READ data packet with suitable ECC in the same transmission.
◆ If no error was detected by the peripheral, it shall send the requested READ packet (Short or Long) with
appropriate ECC and Checksum, if either or both features are enabled.
WC
(3) One byte <= Length of payload DATA <= 2 -1

Himax Confidential -P.44-

Return packet size setting

Data type, hex Function description Number of bytes
Set Maximum Return Packet Size that specifies the maximum
4 bytes
37h size of the payload in a Long packet transmitted from peripheral
(DI + WC + ECC)
back to the host processor.
Note: The two-byte value is transmitted with LS byte first. And during a power-on or Reset sequence, the Maximum Return
Packet Size shall be set by the peripheral to a default value of one.

Variable data packet

Data type, hex Function description Number of bytes
Null Packet is a mechanism for keeping the serial Data Lane(s) Up to 65541 bytes
09h
in High-Speed mode while sending dummy data. ( DI + WC + ECC
+ DCS CMD.
Blanking packet is used to convey blanking timing information
19h + Payload DATA +
in a Long packet.
PF )
Note: (1) When Null Packet, the Payload Data belong “null” Data, actual data values sent are irrelevant because the
peripheral does not capture or store the data.
(2) When Blanking packet, the packet represents a period between active scan lines of a Video Mode display,

Data stream format

Data type, hex Function description Number of bytes
Packed Pixel Stream 16-Bit Format is used to transmit image Up to 65541 bytes
data formatted as 16-bit pixels to a Video Mode display ( DI + WC + ECC
0Eh
module. Pixel format is “(5 bits) red, (6 bits) green and (5 bits) + DCS CMD.
blue”. + Payload DATA + PF )

1 b y te 1 b y te
D0 D7D0 D7
R0 R4 G0 G5 B0 B4

5b 6b 5b

P ix e l 1

1 b y te 2 b y te s 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 2 b y te s
5b 6b 5b 5b 6b 5b
V ir tu a l C h a n n e l

D a ta T y p e

W o rd C o u n t ECC C hecksum

P ix e l 1 P ix e l n

P H (P a c k e t H e a d e r) V a r ia b le P a y lo a d d a ta P F ( P a c k e t F o o te r )

Note: Within a color component, the “LSB is sent first, the MSB last “.

Himax Confidential -P.45-

Data stream format

Data type, hex Function description Number of bytes
Packed Pixel Stream 18-Bit Format is used to transmit image Up to 65541 bytes
data formatted as 18-bit pixels to a Video Mode display ( DI + WC + ECC
1Eh
module. Pixel format is “(6 bits) red, (6 bits) green and (6 bits) + DCS CMD.
blue”. + Payload DATA + PF )

1 b y te 1 b y te
D0 D7 D0 D7
R0 R5 G0 G5 B0 B5

6b 6b 6b

P ix e l 1

1 b y te 2 b y te s 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te
6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b
V ir tu a l C h a n n e l

D a ta T y p e

W o rd C o u n t ECC

P ix e l 1 P ix e l 2 P ix e l 3 P ix e l 4

P H (P a c k e t H e a d e r) V a r ia b le P a y lo a d D a ta ( F ir s t 4 p ix e ls p a c k e d a t 9 b y te s )

1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 2 b y te s
6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

C hecksum

P ix e l n - 3 P ix e l n - 2 P ix e l n - 1 P ix e l n

V a r ia b le P a y lo a d D a ta ( F ir s t 4 p ix e ls p a c k e d a t 9 b y te s ) P F ( P a c k e t F o o te r )

Note: Within a color component, the LSB is sent first and the MSB last and pixel boundaries only line up with byte
boundaries every four pixels (nine bytes). Preferably, display modules employing this format have a horizontal extent
(width in pixels) evenly divisible by four, so no partial bytes remain at the end of the display line data. It is possible to
send pixel data that represent a line width that is not a multiple of four pixels, but display logic on the receiver end
shall dispose of the extra bits of the partial byte at the end of active display and ensure a “clean start” for the next line.

Himax Confidential -P.46-

Data stream format

Data type, hex Function description Number of bytes
Packed Pixel Stream 18-Bit Format, each R, G, or B color Up to 65541 bytes
component is one byte form, but the valid pixel bits occupy bits ( DI + WC + ECC
2Eh
[7:2] and bits [1:0] of are ignored. Pixel format is “(6 bits) red, + DCS CMD.
(6 bits) green and (6 bits) blue”. + Payload DATA + PF )

1 b y te 1 b y te 1 b y te
D0 D7 D0 D7 D0 D7

R0 R5 G0 G5 B0 B5

6b 6b 6b

P ix e l 1

1 b y te 2 b y te s 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 2 b y te s
6b 6b 6b 6b 6b 6b
V ir tu a l C h a n n e l

D a ta T y p e

W o rd C o u n t ECC C hecksum

P ix e l 1 P ix e l n

P H (P a c k e t H e a d e r) V a r ia b le P a y lo a d D a ta P F ( P a c k e t F o o te r )

Note: Within a color component, the LSB is sent first, the MSB last and With this format, pixel boundaries line up with byte
boundaries every three bytes.

Himax Confidential -P.47-

Packed pixel stream, 24-bit format

Data type, hex Function description Number of bytes
Packed Pixel Stream 24-Bit Format is used to transmit image Up to 65541 bytes
data formatted as 24-bit pixels to a Video Mode display ( DI + WC + ECC
3Eh
module. Pixel format is (8 bits) red, (8 bits) green and (8 bits) + DCS CMD.
blue. + Payload DATA + PF )

1 b y te 1 b y te 1 b y te
D0 D7 D0 D7D0 D7
R0 R 7G 0 G 7B 0 B7

8b 8b 8b

P ix e l 1

1 b y te 2 b y te s 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 1 b y te 2 b y te s
8b 8b 8b 8b 8b 8b
V ir tu a l C h a n n e l

D a ta T y p e

W o rd C o u n t ECC C hecksum

P ix e l 1 P ix e l n

P H (P a c k e t H e a d e r) V a r ia b le P a y lo a d D a ta P F ( P a c k e t F o o te r )

Note: Within a color component, the LSB is sent first, the MSB last and With this format, pixel boundaries line up with byte
boundaries every three bytes.

Himax Confidential -P.48-

HX8398-A has the bidirectional capability for returning READ data, ACK or error
information to the host processor. The packet structure for peripheral-to-processor
transactions is the same as that for the processor-to-peripheral direction.

Peripheral-to-processor transactions are of four basic types:

A. Tearing Effect is a Trigger message sent to convey display timing information to

the host processor. Trigger messages ate signal byte packets sent by a
peripheral’s PHY layer in response to a signal form the DSI protocol layer.
B. Acknowledge is a Trigger Message sent when the current transmission, as well as
all preceding transmissions since the last peripheral to host communication.
C. Acknowledge and Error Report is a Short packet sent if any errors were detected
in preceding transmission from the host processor. Once reported, accumulated
errors in the error register are cleared.
D. Response to Read Request may be Short or Long packet that returns data
requested by the preceding READ command from the processor.

In general, if the host processor completes a transmission to the peripheral with BTA
asserted, the peripheral shall respond with one or more appropriate packet(s), and
then return bus ownership to the host processor. If BTA is not asserted following a
transmission from the host processor, the peripheral shall not communicate an
Acknowledge or other error information back to the host processor.

The processor-to-peripheral transactions with BTA asserted, can contain under form.

A. Following a non-Read command in which no error was detected, the peripheral

shall respond with Acknowledge.
B. Following a Read request in which no error was detected, the peripheral shall
send the requested READ data.
C. Following a Read request in which the ECC error was detected and corrected,
the Peripheral shall send the requested READ data in a Long or Short packet,
followed by a 4-byte (Acknowledge with Error Report) packet in the same LP
transmission. The Error Report shall have the ECC Error flag set.
D. Following a non-Read command in which the ECC error was detected and
corrected, the peripheral shall proceed to execute the command, and shall
respond to BTA by sending a 4-byte (Acknowledge with Error Report) packet, the
Error Report shall have the ECC Error flag set.
E. Following any command in which SoT Error, SoT Sync Error, EoT Sync Error,
LP Transmit Sync Error, checksum error or DSI VC ID Invalid was detected,
or the DSI command was not recognized, the peripheral shall send a 4-byte
Acknowledge with Error Report response, with the appropriate error flags set in
the two-byte error field. Only the ACK/Error Report packet shall be transmitted; no
read or write accesses shall take place on the peripheral in response.

Which,

A. “Acknowledge” includes 2 bytes which are DI (VC + Acknowledge Data Type)

and ECC.
Himax Confidential -P.49-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
B. “Acknowledge with Error Report” include 4 bytes which are DI, 2 bytes Error
report and ECC.
C. “Response to Read Request” contains 2 types which are Short packet and long
packet.

An error report is comprised of two bytes following the DI byte, with an ECC byte
following the error report bytes. Table 4.7 shows the Error Report Bit Definitions. And
Table 4.8 list complete set of peripheral-to-processor Data Types.

Bit Description
0 SoT Error
1 SoT Sync Error
2 reserved
3 Escape Mode Entry Command Error
4 Low-Power Transmit Sync Error
5 LP-TX Timeout Error
6 reserved
7 reserved
8 ECC Error, single-bit (detected and corrected)
9 ECC Error, multi-bit (detected, not corrected)
10 Checksum Error (long packet only)
11 DSI Data Type Not Recognized
12 DSI VC ID Invalid
13 reserved
14 reserved
15 reserved
Table 4.7: Shows the error report bit definitions.

Data type,
Data type, hex Description packet Size
binary
02h 00 0010 Acknowledge with Error Report Short
1Ch 01 1100 DCS Long READ Response Long
Others (00h3Fh) Reserved -
Table 4.8: The complete set of peripheral-to-processor data types.

Acknowledge types
Data type, hex Function description Number of bytes
Get Acknowledge with Error report when Error occurs
02 4 bytes
from processor transmission.
Note:When processor transmits complete Payload, following signal by BTA, peripheral must respond to processor.
With errorAcknowledge with error report, Without error Acknowledge.

DCS Read types

Data type, hex Function description Number of bytes
Up to 65541 bytes
This is the long-packet response to DCS Long Read ( DI + WC + ECC + DCS
1Ch
Request. CMD. + Payload DATA +
PF )
Note: If the peripheral is Checksum capable, is shall return a calculated two-byte Checksum appended to the N-byte
payload data. If the peripheral does not support Checksum, it shall return 0000h.
If the DCS command itself is possibly corrupt, due to an uncorrectable ECC error, SoT or SoT Sync error, the
requested READ data packet shall not be sent after the Acknowledge with Error Report packet be sent.

Himax Confidential -P.50-

The Tearing Effect output line supplies to the MPU a Panel synchronization signal.
This signal can be enabled or disabled by the Tearing Effect Line Off & On commands.
The mode of the Tearing Effect signal is defined by the parameter of the Tearing
Effect Line On command.

Tearing Effect Line Modes

Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:

tvdl tvdh

Figure 5.1: Tearing Effect Output signal mode 1

Under Mode1, the TE output timing will be defined by TEP[10:0] setting.

Ex: 1. VFB + VS + VBP= 6 line .

TEP[10:0]=0, then TE signal will output after last line finished.

TEP[10:0]=7, then TE signal will output at second line start.

1920th Line

Invisible
Line

1st Line

2nd Line

TE (Mode 1) tvdh
@TEP[10:0]=0

VFP + VS + VBP = 6 lines

TE (Mode 1)
TEP = 7 lines tvdh
@TEP[10:0]=7

Figure 5.2: TE Delay Output

Himax Confidential -P.51-

V-Sync V-Sync

Invisible Line 1st Line 2nd Line 1919th Line 1920th Line

Figure 5.3: Tearing Effect Output signal mode 2

thdh= The LCD display is not updated
thdl= The LCD display is updated

Under Mode2, the H-sync pulses output amount will be defined by TESL[15:0] setting.

Ex: 1. TESL[15:0]=0, then TE signal will like TE mode 1.

TESL[15:0]=1, then TE signal will output 1920 H-sync.

Internal TE
mode2 V-Sync V-Sync
signal

Invisible Line 1st Line 2nd Line 1919th Line 1920th Line
@TE mode 2
TESL=0 V-Sync V-Sync

@TE mode 2
TESL=1 V-Sync V-Sync

Invisible Line 1st Line 2nd Line 1919th Line 1920th Line

@TE mode 2
TESL=2 V-Sync V-Sync

2nd Line 1919th Line 1920th Line

Figure 5.4: TE Output for TELINE setting

1920th Line

Invisible Line

1st Line

2nd Line

TE (Mode 2)

TE (Mode 1) tvdh

Figure 5.5: Tearing Effect Output signal

Note: During Sleep In Mode, the Tearing Output Pin is active Low

Himax Confidential -P.52-

The Tearing Effect signal is described below:

tv d l tvdh

V e rtic a l T im in g

H o r iz o n t a l T i m in g

thd l thdh

Figure 5.6: Tearing effect output line –tearing effect line timing

Resolution 1080x1920 RGB, Frame Rate = 60 Hz

Symbol Parameter Min. Max. Unit
tvdl Vertical Timing Low Duration 15 - ms
tvdh Vertical Timing High Duration 1000 - us
thdl Horizontal Timing Low Duration 18 - us
thdh Horizontal Timing High Duration 0.13 500 us
tr Rise time - 15 ns
tf Fall time - 15 ns

Table 5.1: AC characteristics of tearing effect signal

The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

tr tf

0 .8 *V D D 1 0 .8*V D D 1

0.2*V D D 1 0 .2 * V D D 1

Figure 5.7: Tearing effect output line–definition of tf, tr

Himax Confidential -P.53-

The HX8398-A can oscillate an internal R-C oscillator with an internal oscillation
resistor (Rf). The oscillation frequency is changed according to the UADJ[4:0] internal
register. Please refer to OSC control register. The default frequency is 88MHz. The
oscillation frequency tolerance is ±5%.

D is p la y
C o n tr o lle r

F re q u e n c y
S te p u p C ir c u it
D iv id e r 1
( fo r V S P )
F S 0 [3 :0 ]

F re q u e n c y
S te p u p C ir c u it
D iv id e r 2
( fo r V G H /V G L )
F S 1 [3 :0 ]

88M H z fo s c F re q u e n c y
O s c illa to r S te p u p C ir c u it
U A D J [4 :0 ] D iv id e r 3
C lo c k ( fo r V C I_ R E G )
F S 2 [3 :0 ]

C ABC _PW M _C LK
( fo r B a c k lig h t C A B C )
Figure 5.8: OSC architecture

Himax Confidential -P.54-

The HX8398-A contains a 3242 channels of source driver (normal S1~S3240; Zig-zag
with SD0 or SD3241) which is used for driving the source line of a-Si TFT LCD panel.
The source driver converts the input digital data into the analog voltage for 3242
channels and generates corresponding gray scale voltage output, which can realize a
16.7M colors display simultaneously. Since the output circuit of this source driver
incorporates an operational amplifier, a positive and a negative voltage can be
alternately outputted from each channel.

H_RES[2:0] Horizontal Resolution Source channels

000 1080RGB S1 ~ S3240
001 1024RGB S1 ~ S1536 , S1705 ~ S3240
010 960RGB S1 ~ S1440 , S1801 ~ S3240
011 900RGB S1 ~ S1350 , S1891 ~ S3240
100 800RGB S1 ~ S1200 , S2041 ~ S3240
101 720RGB S1 ~ S1080 , S2161 ~ S3240
Table 5.2: Source output for Panel resolution

Himax Confidential -P.55-

G1920 G1920 G1920

- + - + - + + - + + - + - + - - + - - + - + - + + - +

S1 S2 S3240 S1 S2 S3240 S1 S2 S3240

3-dot inversion 4-dot inversion 8-dot inversion

G1 G1 G1
+ - + - + - - + - + - + - + - - + - + - + - + - - + -
G2 G2 G2
+ - + - + - - + - + - + - + - - + - + - + - + - - + -
G3 G3 G3
+ - + - + - - + - - + - + - + + - + + - + - + - - + -
G4 G4 G4
- + - + - + + - + - + - + - + + - + + - + - + - - + -
G5 G5 G5
- + - + - + + - + - + - + - + + - + - + - + - + + - +
G6 G6 G6
- + - + - + + - + - + - + - + + - + - + - + - + + - +
G7 G7 G7
+ - + - + - - + - + - + - + - - + - - + - + - + + - +
G8
- + - + - + + - +
G9
- + - + - + + - +
G1920 G1920 G10
- + - + - + + - + - + - + - + + - + - + - + - + + - +
G11
- + - + - + + - +
S1 S2 S3240 S1 S2 S3240 G12
- + - + - + + - +
Column inversion G13
+ - + - + - - + -
G1
+ - + - + - - + -
G2
+ - + - + - - + -
G3 G1920
+ - + - + - - + - - + - + - + + - +
G4
+ - + - + - - + - S1 S2 S3240
G5
+ - + - + - - + -
G6
+ - + - + - - + -
G7
+ - + - + - - + -

G1920
+ - + - + - - + -

S1 S2 S3240

Figure 5.9: Inversion mode

Himax Confidential -P.56-

G1920 G1920
- + - + - + - + - + - + - + - + + - +

S1 S3240 S1 S3240
SD0 S2 S2 SD3241

ZZ_EO=1
ZZ_LR=0 ZZ_LR=1
G1 G1
+ - + - + - + - + - + - + - + - - + -
G2 G2
- + - + - + - - + - + - + - + - +
G3 G3
+ - + - + - + - + - + - + - + - - + -
G4 G4
- + - + - + - - + - + - + - + - +
G5 G5
+ - + - + - + - + - + - + - + - - + -
G6 G6
- + - + - + - - + - + - + - + - +
G7 G7
+ - + - + - + - + - + - + - + - - + -

G1920 G1920
- + - + - + - - + - + - + - + - +

S1 S3240
S1 S3240
S2 SD3241
SD0 S2

Figure 5.10: Zig-Zag Inversion mode(ZZ_2PL=0)

Himax Confidential -P.57-

G1920 G1920
- + - + - + - + - + - + - + - + + - +

S1 S3240 S1 S3240
SL1 S2 S2 SR1

ZZ_EO=1
ZZ_LR=0 ZZ_LR=1
G1 G1
+ - + - + - + - + - + - + - + - - + -
G2 G2
+ - + - + - + - + - + - + - + - - + -
G3 G3
- + - + - + - - + - + - + - + - +
G4 G4
- + - + - + - - + - + - + - + - +
G5 G5
+ - + - + - + - + - + - + - + - - + -
G6 G6
+ - + - + - + - + - + - + - + - - + -
G7 G7
- + - + - + - - + - + - + - + - +

G1920 G1920
- + - + - + - - + - + - + - + - +

S1 S3240
S1 S3240
S2 SR1
SL1 S2

Figure 5.11: Zig-Zag2 Inversion mode(ZZ_2PL=1)

Himax Confidential -P.58-

VGH (7.3V~ 20V)

VSP (3.0V ~ 6.0V)

VSPR(3.1V ~5.8V)

VCI_REG(0.5*VSP or VDD3)

VDD3 (2.5V ~ 3.6V)

VDD1 (1.65V ~ 3.6V) HS_VCC (1.65V ~ 3.6V)

VDDD (1.5V) HS_LDO (1.55V)

VSSD,VSSA

VCOM(-4V ~ 1V)

VSNR (-3.1V ~ -5.8V)

VSN (-3.0V ~ -6.0V)

VGL(-5.3V~ -18V)

Figure 5.12: LCD power generation scheme for HX5186 and PFM mode

VGH (7.3V~ 20V)

VSP (3.0V ~ 6.0V)

VSPR(3.1V ~5.8V)
External-1 mode,
External-3 mode
VCI_REG(0.5*VSP or VDD3)

VDD3

VDD1 (1.65V ~ 3.6V) HS_VCC (1.65V ~ 3.6V)

VDDD (1.5V) HS_LDO (1.55V)

VSSD,VSSA

VCOM(-4V ~ 1V)

VSNR (-3.1V ~ -5.8V)

VSN (-3.0V ~ -6.0V)

VGL(-5.3V~ -18V)

Figure 5.13: LCD power generation scheme for external power mode

Himax Confidential -P.59-

Name Function Set up value Note

VSPR Reference voltage for gamma circuit 3.1V ~ 5.8V -
VSNR Reference voltage for gamma circuit -3.1V ~ -5.8V -
VDDD Logic power supply 1.5V
VGH DC/DC converter circuit output 7.3V ~ 20V -
VGL DC/DC converter circuit output -5.3V ~ -18V -
VGLO2 Negative gate driver output voltage level 2 -7V ~ -18V -
VCI_REG DC/DC converter circuit output 0.5*VSP or VDD3 -
VCOM VCOM DC voltage -4V ~ 1V -
HS_LDO Analog power for High speed interface circuit 1.55V -
Table 5.3: Voltage configuration

Himax Confidential -P.60-

5.5.1 Charge pump and step up circuit mode

HX8398-A supports various kinds of power generation mode, including PFM Type A, PFM
Type B, PFM Type C and external HX5186 and external VSP&VSN and external
VSP&VSN&VDD3 and external VSP&VSN&VGH&VGL . All power power mode can be set by
hardware pins PCCS[2:0] as below:

PCCS2 PCCS1 PCCS0 Power source Driving Mode

0 0 0 VDD3 / VDD1 PFM Type C
0 0 1 VDD3 /VDD1 HX5186- C
0 1 0 VSP /VDD1 PFM Type D(for VSN)
0 1 1 VSP / VSN / VDD1 External-1
1 0 0 VSP / VSN / VGH / VGL / VDD1 External-3
1 0 1 VDD3 / VDD1 PFM Type A
1 1 1 VDD3 / VSP / VSN / VDD1 External-2
Others Reserved Reserved
Table 5.4: Power mode setting

Himax Confidential -P.61-

5.5.2 Use HX5186-C

The HX5186-C is highly efficient switching voltage generator circuits that generate the
high voltage level VSP/VSN required for source drivers. HX8398-A contains Charge
Pump Controller for HX5186-C, including a comparator for VSP/VSN feedback control.
HX5186-C can provide maximum efficiency and use minimum number of external
components. The output voltage of the boost converter can be set from 3V to 6V
(VSP) and -3V to -6V (VSN)

C41P

C41N

DC/DC C42P
Pumping
C42N

VCI_REG

C21P

C21N C12

C22P

C22N C13

DC/DC C31P
C3 Pumping C14
VDD3 C31N
D1

C1 VGL C10
VDD1
VGH C9

C2
HS_VCC
VREF

VCOM C8
Voltage
Reference VSNR
VSPR

VDDD C4
HS_LDO C5 VDD3
o

VSP VSP C3P

C19
C6 VSN C3N
VREF
Charge GND C2P
Pump C18
Controller VSN C7
CTRL_A C2N

VCSW1 CTRL_B C1P

C17
VCSW2 VIN C1N
HX5186-C
HX8398-A

Figure 5.14: DC/DC converter circuit of HX5186-C

Himax Confidential -P.62-

5.5.3 Use PFM DC/DC converter

The PFM DC-DC converter generates the high voltage level VSP/VSN required for
source drivers. HX8398-A contains sub-circuits of the PFM boost converter, including
a precision 1.8V reference voltage, comparator, PFM controlling logic, and the output
buffer. The boost converter uses a external power transistor to provide maximum
efficiency and to minimize the number of external components. The output voltage of
the boost converter can be set from 3V to 6 V (VSP) and -3 to -6V (VSN)

C41P

C41N

DC/DC C42P
Pumping
C42N

VCI_REG

C21P

C21N C12

C22P

C22N C13

DC/DC C31P
C3 Pumping C14
VDD3 C31N
D1

C1 VGL C10
VDD1
VGH C9

C2
HS_VCC
VREF

VCOM C8
Voltage
Reference VSNR
VSPR

VDDD C4
HS_LDO C5
VDD3

VCSW2
o SW2

VSN
C6
VREF D3
PFM L1
Controller D2

VSP C7

SW1
VCSW1

HX8398-A

Figure 5.15: DC/DC converter circuit (PFM Type A)

Himax Confidential -P.63-

C41P

C41N

DC/DC C42P
Pumping
C42N

VCI_REG

C21P

C21N C12

C22P

C22N C13

DC/DC C31P
C3 Pumping C14
VDD3 C31N
D1

C1 VGL C10
VDD1
VGH C9

C2
HS_VCC
VREF

VCOM C8
Voltage
Reference VSNR
VSPR

VDDD C4
HS_LDO C5
VSP

VCSW2
o SW2

VSN
C6
PFM VREF D3
L1
Controller

VSP C7

VCSW1

HX8398-A
Figure 5.16: DC/DC converter circuit (PFM Type D)

Himax Confidential -P.64-

C41P

C41N

DC/DC C42P
Pumping
C42N

VCI_REG

C21P

C21N C12

C22P

C22N C13

DC/DC C31P
C3 Pumping C14
VDD3 C31N
D1

C1 VGL C10
VDD1
VGH C9

C2
HS_VCC
VREF

VCOM C8
Voltage
Reference VSNR
VSPR

VDDD C4
HS_LDO C5

VDD3
VCSW2

D3
VSN
C6
PFM VREF L1
Controller D2 C20
VSP C7
D4
VCSW1 SW1

HX8398-A

Figure 5.17: DC/DC converter circuit (PFM Type C)

Himax Confidential -P.65-

5.5.4 Use external VSP and VSN circuit

VDD3 is generated from VSP by [Link] input voltage range of VSP is from 4.5V ~ 6V.
The input voltage range of VSN is from -4.5V ~ -6 V.

C3
VDD3

C41P
C15
C41N

DC/DC C42P Optional

C6 Pumping
VSP C16
Regulator C42N
C11
VCI_REG

C21P

C21N C12
C7
VSN C22P

C22N C13

DC/DC C31P
Pumping C14
C31N
D1
VSN

VGL C10
C1 VGH C9
VDD1

C2 VREF
HS_VCC
VCOM C8
Voltage
Reference VSNR
VSPR

VDDD C4
HS_LDO C5
HX8398-A

Figure 5.18: DC/DC converter circuit of external VSP/VSN

Himax Confidential -P.66-

The input voltage range of VDD3 is from 2.5V ~ [Link] input voltage range of VSP is from
4.5V ~ 6 V. The input voltage range of VSN is from -4.5V ~ -6V.

C41P

C41N

DC/DC C42P
C6 Pumping
VSP C42N

VCI_REG

C21P

C21N C12
C7
VSN C22P

C22N C13

DC/DC C31P
Pumping C14
C31N
D1
VSN

VGL C10
C1 VGH C9
VDD1

C2 VREF
HS_VCC
VCOM C8
Voltage
Reference VSNR
C3 VSPR
VDD3
VDDD C4
HS_LDO C5
HX8398-A

Figure 5.19: DC/DC converter circuit of external VDD3/VSP/VSN

Himax Confidential -P.67-

The input voltage range of VSP is from 4.5V ~ 6 V. The input voltage range of VSN is from
-4.5V ~ -6V.

C3
VDD3

C41P
C15
C41N

DC/DC C42P Optional

C6 Pumping
VSP C16
Regulator C42N
C11
VCI_REG

C7 C21P
VSN
C21N C12

C22P

C22N C13
C9
VGH DC/DC C31P
Pumping C14
C31N
C10
VGL

C1
VDD1

C2 VREF
HS_VCC
VCOM C8
Voltage
Reference VSNR
VSPR

VDDD C4
HS_LDO C5
HX8398-A

Figure 5.20: DC/DC converter circuit of external VSP/VSN/VGH/VGL

Himax Confidential -P.68-

The HX8398-A supports an idle display mode. The grayscale level to be used is 0 and
255 with R7, G7, B7 decoding. In idle display mode, the Gamma-micro-adjustment
registers are invalid and only the upper bits of RGB are used for display.

Graphics
(Input data)

R R R R R R R R G G G G G G GG B B B B B B B B
76543210 76543210 76 543210

1 1 1

Positive Polarity Register

VHP0[6:0]
V0P/V0N VLP7[6:0]
8- bit Grayscale 8- bit Grayscale 8- bit Grayscale
D/ A Converter D/ A Converter
V1P/V1N Grayscale
D/ A Converter
< R> < G> Voltage
V255P/V255N Generator
Output Output Output Negative Polarity Register
Driver Driver Driver
VHN0[6:0]
VLN7[6:0]

R G B
LCD

Figure 5.21: Idle mode grayscale control

Himax Confidential -P.69-

The HX8398-A offers two kinds of Gamma adjustment. One kind is through Source Driver
directly, another one is adjusted by the digital gamma correction. The Gamma adjustment
way is selected by internal register DGC_EN bit.

A) Gamma adjustment of Source Driver

luminance of R

luminance of White
Gary-scale of R Source
Driver
8
luminance of G

Gary-scale of White

Gary-scale of G
luminance of B

Gamma
register

Gary-scale of B

B) Gamma adjustment of Digital Gamma Correction

luminance of R

R,G,B
Gary-scale of R Gamma Source Gary-scale of R
Dithering
correction Driver
8 10 8
luminance of G

(LUT)
luminance of G

Gary-scale of G Gary-scale of G
luminance of B

luminance of B

Gamma
register

Gary-scale of B Gary-scale of B

Figure 5.22: Gamma adjustments different of source driver with digital gamma correction

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Graphics
(Input data)

Positive Polarity Register

R R R R R R R R G G G G G G GG B B B B B B B B VHP0[6:0], VHP1[6:0]
76543210 76543210 76 543210 VHP2[6:0], VHP3[6:0]
VHP4[6:0], VHP5[6:0]
VHP6[6:0], VHP7[6:0]
VMP0[7:0], VMP1[7:0]
VMP2[7:0], VMP3[7:0]
VMP4[7:0], VMP5[7:0]
VMP6[7:0], VMP7[7:0]
VMP8[7:0], VMP9[7:0]
VMP10[7:0], VMP11[7:0]
8 8 8
VMP12[7:0], VLP0[6:0]
VLP1[6:0], VLP2[6:0]
VLP3[6:0], VLP4[6:0]
VLP5[6:0], VLP6[6:0]
V0P/V0N
VLP7[6:0]
V1P/V1N Grayscale
Negative Polarity Register
Voltage
8- bit Grayscale 8- bit Grayscale 8- bit Grayscale VHN0[6:0], VHN1[6:0]
D/ A Converter D/ A Converter D/ A Converter V255P/V255N Generator
VHN2[6:0], VHN3[6:0]
< R> < G> 
VHN4[6:0], VHN5[6:0]

Output Output Output VHN6[6:0], VHN7[6:0]

Driver Driver Driver VMN0[7:0], VMN1[7:0]
VMN2[7:0], VMN3[7:0]
VMN4[7:0], VMN5[7:0]
VMN6[7:0], VMN7[7:0]
VMN8[7:0], VMN9[7:0]
VMN10[7:0], VMN11[7:0]
VMN12[7:0], VLN0[6:0]
VLN1[6:0], VLN2[6:0]

R G B VLN3[6:0], VLN4[6:0]
VLN5[6:0], VLN6[6:0]
VLN7[6:0]
LCD

Figure 5.23: Grayscale control

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The HX8398-A has register groups for specifying a series grayscale voltage that meets
the Gamma-characteristics for the LCD panel used. These registers are divided into two
groups, which correspond to the gradient, amplitude, and macro adjustment of the
voltage for the grayscale characteristics. The polarity of each register can be specified
independently.

(1) Center adjustment registers

This gamma adjustment registers are used to adjust the reference gamma voltage for
center grayscale level. This function is implemented by controlling the 256-to-1 selector
in the gamma resister stream for reference gamma voltage generation. These registers
are available for both positive and negative polarities.

(2) Edge adjustment registers

This gamma adjustment registers are used to adjust the reference gamma voltage for
both edge grayscale level. This function is implemented by controlling the 128-to-1
selector in the gamma resister stream for reference gamma voltage generation. These
registers are available for both positive and negative polarities.

Register Positive Negative

Description
Groups Polarity Polarity
VHP0 6-0 VHN0 6-0 128-to-1 selector (voltage level of grayscale 0)
VHP1 6-0 VHN1 6-0 128-to-1 selector (voltage level of grayscale 1)
VHP2 6-0 VHN2 6-0 128-to-1 selector (voltage level of grayscale 3)
Up Edge VHP3 6-0 VHN3 6-0 128-to-1 selector (voltage level of grayscale 5)
adjustment VHP4 6-0 VHN4 6-0 128-to-1 selector (voltage level of grayscale 7)
VHP5 6-0 VHN5 6-0 128-to-1 selector (voltage level of grayscale 9)
VHP6 6-0 VHN6 6-0 128-to-1 selector (voltage level of grayscale 12)
VHP7 6-0 VHN7 6-0 128-to-1 selector (voltage level of grayscale 15)
VMP0 7-0 VMN0 7-0 255-to-1 selector (voltage level of grayscale 20)
VMP1 7-0 VMN1 7-0 255-to-1 selector (voltage level of grayscale 28)
VMP2 7-0 VMN2 7-0 255-to-1 selector (voltage level of grayscale 40)
VMP3 7-0 VMN3 7-0 255-to-1 selector (voltage level of grayscale 52)
VMP4 7-0 VMN4 7-0 255-to-1 selector (voltage level of grayscale 76)
VMP5 7-0 VMN5 7-0 255-to-1 selector (voltage level of grayscale 100)
Center
VMP6 7-0 VMN6 7-0 255-to-1 selector (voltage level of grayscale 128)
adjustment
VMP7 7-0 VMN7 7-0 255-to-1 selector (voltage level of grayscale 156)
VMP8 7-0 VMN8 7-0 255-to-1 selector (voltage level of grayscale 180)
VMP9 7-0 VMN9 7-0 255-to-1 selector (voltage level of grayscale 204)
VMP10 7-0 VMN10 7-0 255-to-1 selector (voltage level of grayscale 216)
VMP11 7-0 VMN11 7-0 255-to-1 selector (voltage level of grayscale 228)
VMP12 7-0 VMN12 7-0 255-to-1 selector (voltage level of grayscale 236)
VLP0 6-0 VLN0 6-0 128-to-1 selector (voltage level of grayscale 240)
VLP1 6-0 VLN1 6-0 128-to-1 selector (voltage level of grayscale 243)
VLP2 6-0 VLN2 6-0 128-to-1 selector (voltage level of grayscale 246)
Down Edge VLP3 6-0 VLN3 6-0 128-to-1 selector (voltage level of grayscale 248)
adjustment VLP4 6-0 VLN4 6-0 128-to-1 selector (voltage level of grayscale 250)
VLP5 6-0 VLN5 6-0 128-to-1 selector (voltage level of grayscale 252)
VLP6 6-0 VLN6 6-0 128-to-1 selector (voltage level of grayscale 254)
VLP7 6-0 VLN7 6-0 128-to-1 selector (voltage level of grayscale 255)
Table 5.5: Gamma-Adjustment registers for normally white panel

Himax Confidential -P.72-

Himax Confidential -P.73-

VMP(N)5
VHP(N)7
VHP(N)0

VHP(N)1

VMP(N)0
VSPR/
7 7 7
VSNR 8 8
0 VinP/N0

128 to 1 1 VinP/N1
selector
2 VinP/N3

128 to 1 3 VinP/N5
selector
4 VinP/N7

5 VinP/N9

128 to 1
6 VinP/N12
selector
7 VinP/N15

256 to 1 8 VinP/N20
selector

9 VinP/N28

10 VinP/N40

11 VinP/N52

12 VinP/N76

256 to 1
selector 13 VinP/N100

256 to 1 14 VinP/N128
selector

15 VinP/N156

16 VinP/N180

17 VinP/N204

18 VinP/N216

19 VinP/N228
256 to 1
selector
20 VinP/N236

128 to 1 21 VinP/N240
selector
22 VinP/N243

23 VinP/N246

128 to 1
24 VinP/N248
selector
25 VinP/N250

128 to 1 26 VinP/N252
selector

VSSA 27 VinP/N254

28 VinP/N255
7 7 7 8 8
VMP(N)12

VMP(N)6
VLP(N)6
VLP(N)7

VLP(N)0

Amplitude Adjustment register

Figure 5.24: Gamma resister stream and gamma reference voltage

Himax Confidential -P.74-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04

Variable resister
There are two types of variable resistors, one is for center adjustment and the other is for
edge adjustment. The resistances are decided by setting values in the center adjustment
and edge adjustment registers. Their relationships are shown below.

Value in Register Resistance Value in Register Resistance

VH(P/N)0~7 [6:0] VH(P/N) 0~7 VL(P/N)0~7 [6:0] VL(P/N) 0~7
000_0000 0R 000_0000 0R
000_0001 2R 000_0001 2R
000_0010 4R 000_0010 4R
000_0011 6R 000_0011 6R
: : : :
011_1101 122R 011_1101 122R
011_1110 124R 011_1110 124R
011_1111 126R 011_1111 126R
100_0000 128R 100_0000 128R
100_0001 130R 100_0001 130R
100_0010 132R 100_0010 132R
: : : :
111_1101 250R 111_1101 250R
111_1110 252R 111_1110 252R
111_1111 254R 111_1111 254R

Table 5.7: Edge adjustment Resistance

Value in Register Resistance

VM(P/N)0~12 [7:0] VM(P/N)0~12
0000_0000 0R
0000_0001 1R
0000_0010 2R
: :
0101_0101 85R
0101_0110 86R
0101_0111 87R
: :
1101_0101 213R
1101_0110 214R
1101_0111 215R
: :
1111_1101 253R
1111_1110 254R
1111_1111 255R

Table 5.8: Center adjustment Resistance

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Reference
Macro adjustment value VinP/N1 formula
voltage
VHP1 [6:0] = 000_0000 (596R / 600R) * VSP/NR
VHP1 [6:0] = 000_0001 ((596R – 2R ) / 600R) * VSP/NR
VHP1 [6:0] = 000_0010 ((596R – 4R ) / 600R) * VSP/NR
VHP1 [6:0] = 000_0011 ((596R – 6R ) / 600R) * VSP/NR
VHP1 [6:0] = 000_0100 ((596R – 8R ) / 600R) * VSP/NR
VHP1 [6:0] = 000_0101 ((596R – 10R ) / 600R) * VSP/NR
: :
VHP1 [6:0] = 100_0001 ((596R – 130R ) / 600R) * VSP/NR
VHP1 [6:0] = 100_0010 ((596R – 132R ) / 600R) * VSP/NR
VinP/N1
VHP1 [6:0] = 100_0011 ((596R – 134R ) / 600R) * VSP/NR
VHP1 [6:0] = 100_0100 ((596R – 136R ) / 600R) * VSP/NR
VHP1 [6:0] = 100_0101 ((596R – 138R ) / 600R) * VSP/NR
: :
VHP1 [6:0] = 111_1011 ((596R – 246R ) / 600R) * VSP/NR
VHP1 [6:0] = 111_1100 ((596R – 248R ) / 600R) * VSP/NR
VHP1 [6:0] = 111_1101 ((596R – 250R ) / 600R) * VSP/NR
VHP1 [6:0] = 111_1110 ((596R – 252R ) / 600R) * VSP/NR
VHP1 [6:0] = 111_1111 ((596R – 254R ) / 600R) * VSP/NR
Table 5.10: VinP/N1

Reference
Macro adjustment value VinP/N3 formula
voltage
VHP2 [6:0] = 000_0000 (592R / 600R) * VSP/NR
VHP2 [6:0] = 000_0001 ((592R – 2R ) / 600R) * VSP/NR
VHP2 [6:0] = 000_0010 ((592R – 4R ) / 600R) * VSP/NR
VHP2 [6:0] = 000_0011 ((592R – 6R ) / 600R) * VSP/NR
VHP2 [6:0] = 000_0100 ((592R – 8R ) / 600R) * VSP/NR
VHP2 [6:0] = 000_0101 ((592R – 10R ) / 600R) * VSP/NR
: :
VHP2 [6:0] = 100_0001 ((592R – 130R ) / 600R) * VSP/NR
VHP2 [6:0] = 100_0010 ((592R – 132R ) / 600R) * VSP/NR
VinP/N3
VHP2 [6:0] = 100_0011 ((592R – 134R ) / 600R) * VSP/NR
VHP2 [6:0] = 100_0100 ((592R – 136R ) / 600R) * VSP/NR
VHP2 [6:0] = 100_0101 ((592R – 138R ) / 600R) * VSP/NR
: :
VHP2 [6:0] = 111_1011 ((592R – 246R ) / 600R) * VSP/NR
VHP2 [6:0] = 111_1100 ((592R – 248R ) / 600R) * VSP/NR
VHP2 [6:0] = 111_1101 ((592R – 250R ) / 600R) * VSP/NR
VHP2 [6:0] = 111_1110 ((592R – 252R ) / 600R) * VSP/NR
VHP2 [6:0] = 111_1111 ((592R – 254R ) / 600R) * VSP/NR
Table 5.11: VinP/N3

Himax Confidential -P.76-

Reference
Macro adjustment value VinP/N7 formula
voltage
VHP4 [6:0] = 000_0000 (580R / 600R) * VSP/NR
VHP4 [6:0] = 000_0001 ((580R – 2R ) / 600R) * VSP/NR
VHP4 [6:0] = 000_0010 ((580R – 4R ) / 600R) * VSP/NR
VHP4 [6:0] = 000_0011 ((580R – 6R ) / 600R) * VSP/NR
VHP4 [6:0] = 000_0100 ((580R – 8R ) / 600R) * VSP/NR
VHP4 [6:0] = 000_0101 ((580R – 10R ) / 600R) * VSP/NR
: :
VHP4 [6:0] = 100_0001 ((580R – 130R ) / 600R) * VSP/NR
VHP4 [6:0] = 100_0010 ((580R – 132R ) / 600R) * VSP/NR
VinP/N7
VHP4 [6:0] = 100_0011 ((580R – 134R ) / 600R) * VSP/NR
VHP4 [6:0] = 100_0100 ((580R – 136R ) / 600R) * VSP/NR
VHP4 [6:0] = 100_0101 ((580R – 138R ) / 600R) * VSP/NR
: :
VHP4 [6:0] = 111_1011 ((580R – 246R ) / 600R) * VSP/NR
VHP4 [6:0] = 111_1100 ((580R – 248R ) / 600R) * VSP/NR
VHP4 [6:0] = 111_1101 ((580R – 250R ) / 600R) * VSP/NR
VHP4 [6:0] = 111_1110 ((580R – 252R ) / 600R) * VSP/NR
VHP4 [6:0] = 111_1111 ((580R – 254R ) / 600R) * VSP/NR
Table 5.13: VinP/N7

Reference
Macro adjustment value VinP/N9 formula
voltage
VHP5 [6:0] = 000_0000 (576R / 600R) * VSP/NR
VHP5 [6:0] = 000_0001 ((576R – 2R ) / 600R) * VSP/NR
VHP5 [6:0] = 000_0010 ((576R – 4R ) / 600R) * VSP/NR
VHP5 [6:0] = 000_0011 ((576R – 6R ) / 600R) * VSP/NR
VHP5 [6:0] = 000_0100 ((576R – 8R ) / 600R) * VSP/NR
VHP5 [6:0] = 000_0101 ((576R – 10R ) / 600R) * VSP/NR
: :
VHP5 [6:0] = 100_0001 ((576R – 130R ) / 600R) * VSP/NR
VHP5 [6:0] = 100_0010 ((576R – 132R ) / 600R) * VSP/NR
VinP/N9
VHP5 [6:0] = 100_0011 ((576R – 134R ) / 600R) * VSP/NR
VHP5 [6:0] = 100_0100 ((576R – 136R ) / 600R) * VSP/NR
VHP5 [6:0] = 100_0101 ((576R – 138R ) / 600R) * VSP/NR
: :
VHP5 [6:0] = 111_1011 ((576R – 246R ) / 600R) * VSP/NR
VHP5 [6:0] = 111_1100 ((576R – 248R ) / 600R) * VSP/NR
VHP5 [6:0] = 111_1101 ((576R – 250R ) / 600R) * VSP/NR
VHP5 [6:0] = 111_1110 ((576R – 252R ) / 600R) * VSP/NR
VHP5 [6:0] = 111_1111 ((576R – 254R ) / 600R) * VSP/NR
Table 5.14: VinP/N9

Himax Confidential -P.77-

Reference
Macro adjustment value VinP/N15 formula
voltage
VHP7 [6:0] = 000_0000 (552R / 600R) * VSP/NR
VHP7 [6:0] = 000_0001 ((552R – 2R ) / 600R) * VSP/NR
VHP7 [6:0] = 000_0010 ((552R – 4R ) / 600R) * VSP/NR
VHP7 [6:0] = 000_0011 ((552R – 6R ) / 600R) * VSP/NR
VHP7 [6:0] = 000_0100 ((552R – 8R ) / 600R) * VSP/NR
VHP7 [6:0] = 000_0101 ((552R – 10R ) / 600R) * VSP/NR
: :
VHP7 [6:0] = 100_0001 ((552R – 130R ) / 600R) * VSP/NR
VHP7 [6:0] = 100_0010 ((552R – 132R ) / 600R) * VSP/NR
VinP/N15
VHP7 [6:0] = 100_0011 ((552R – 134R ) / 600R) * VSP/NR
VHP7 [6:0] = 100_0100 ((552R – 136R ) / 600R) * VSP/NR
VHP7 [6:0] = 100_0101 ((552R – 138R ) / 600R) * VSP/NR
: :
VHP7 [6:0] = 111_1011 ((552R – 246R ) / 600R) * VSP/NR
VHP7 [6:0] = 111_1100 ((552R – 248R ) / 600R) * VSP/NR
VHP7 [6:0] = 111_1101 ((552R – 250R ) / 600R) * VSP/NR
VHP7 [6:0] = 111_1110 ((552R – 252R ) / 600R) * VSP/NR
VHP7 [6:0] = 111_1111 ((552R – 254R ) / 600R) * VSP/NR
Table 5.16: VinP/N15

Reference
Macro adjustment value VinP/N20 formula
voltage
VMP0 [7:0] = 0000_0000 (536R / 600R) * VSP/NR
VMP0 [7:0] = 0000_0001 ((536R – 1R ) / 600R) * VSP/NR
VMP0 [7:0] = 0000_0010 ((536R – 2R ) / 600R) * VSP/NR
VMP0 [7:0] = 0000_0011 ((536R – 3R ) / 600R) * VSP/NR
VMP0 [7:0] = 0000_0100 ((536R – 4R ) / 600R) * VSP/NR
VMP0 [7:0] = 0000_0101 ((536R – 5R ) / 600R) * VSP/NR
: :
VMP0 [7:0] = 1000_0001 ((536R – 129R ) / 600R) * VSP/NR
VMP0 [7:0] = 1000_0010 ((536R – 130R ) / 600R) * VSP/NR
VinP/N20
VMP0 [7:0] = 1000_0011 ((536R – 131R ) / 600R) * VSP/NR
VMP0 [7:0] = 1000_0100 ((536R – 132R ) / 600R) * VSP/NR
VMP0 [7:0] = 1000_0101 ((536R – 133R ) / 600R) * VSP/NR
: :
VMP0 [7:0] = 1111_1011 ((536R – 251R ) / 600R) * VSP/NR
VMP0 [7:0] = 1111_1100 ((536R – 252R ) / 600R) * VSP/NR
VMP0 [7:0] = 1111_1101 ((536R – 253R ) / 600R) * VSP/NR
VMP0 [7:0] = 1111_1110 ((536R – 254R ) / 600R) * VSP/NR
VMP0 [7:0] = 1111_1111 ((536R – 255R ) / 600R) * VSP/NR
Table 5.17: VinP/N20

Himax Confidential -P.78-

Reference
Macro adjustment value VinP/N40 formula
voltage
VMP2 [7:0] = 0000_0000 (516R / 600R) * VSP/NR
VMP2 [7:0] = 0000_0001 ((516R – 1R ) / 600R) * VSP/NR
VMP2 [7:0] = 0000_0010 ((516R – 2R ) / 600R) * VSP/NR
VMP2 [7:0] = 0000_0011 ((516R – 3R ) / 600R) * VSP/NR
VMP2 [7:0] = 0000_0100 ((516R – 4R ) / 600R) * VSP/NR
VMP2 [7:0] = 0000_0101 ((516R – 5R ) / 600R) * VSP/NR
: :
VMP2 [7:0] = 1000_0001 ((516R – 129R ) / 600R) * VSP/NR
VMP2 [7:0] = 1000_0010 ((516R – 130R ) / 600R) * VSP/NR
VinP/N40
VMP2 [7:0] = 1000_0011 ((516R – 131R ) / 600R) * VSP/NR
VMP2 [7:0] = 1000_0100 ((516R – 132R ) / 600R) * VSP/NR
VMP2 [7:0] = 1000_0101 ((516R – 133R ) / 600R) * VSP/NR
: :
VMP2 [7:0] = 1111_1011 ((516R – 251R ) / 600R) * VSP/NR
VMP2 [7:0] = 1111_1100 ((516R – 252R ) / 600R) * VSP/NR
VMP2 [7:0] = 1111_1101 ((516R – 253R ) / 600R) * VSP/NR
VMP2 [7:0] = 1111_1110 ((516R – 254R ) / 600R) * VSP/NR
VMP2 [7:0] = 1111_1111 ((516R – 255R ) / 600R) * VSP/NR
Table 5.19: VinP/N40

Reference
Macro adjustment value VinP/N52 formula
voltage
VMP3 [7:0] = 0000_0000 (492R / 600R) * VSP/NR
VMP3 [7:0] = 0000_0001 ((492R – 1R ) / 600R) * VSP/NR
VMP3 [7:0] = 0000_0010 ((492R – 2R ) / 600R) * VSP/NR
VMP3 [7:0] = 0000_0011 ((492R – 3R ) / 600R) * VSP/NR
VMP3 [7:0] = 0000_0100 ((492R – 4R ) / 600R) * VSP/NR
VMP3 [7:0] = 0000_0101 ((492R – 5R ) / 600R) * VSP/NR
: :
VMP3 [7:0] = 1000_0001 ((492R – 129R ) / 600R) * VSP/NR
VMP3 [7:0] = 1000_0010 ((492R – 130R ) / 600R) * VSP/NR
VinP/N52
VMP3 [7:0] = 1000_0011 ((492R – 131R ) / 600R) * VSP/NR
VMP3 [7:0] = 1000_0100 ((492R – 132R ) / 600R) * VSP/NR
VMP3 [7:0] = 1000_0101 ((492R – 133R ) / 600R) * VSP/NR
: :
VMP3 [7:0] = 1111_1011 ((492R – 251R ) / 600R) * VSP/NR
VMP3 [7:0] = 1111_1100 ((492R – 252R ) / 600R) * VSP/NR
VMP3 [7:0] = 1111_1101 ((492R – 253R ) / 600R) * VSP/NR
VMP3 [7:0] = 1111_1110 ((492R – 254R ) / 600R) * VSP/NR
VMP3 [7:0] = 1111_1111 ((492R – 255R ) / 600R) * VSP/NR
Table 5.20: VinP/N52

Himax Confidential -P.79-

Reference
Macro adjustment value VinP/N100 formula
voltage
VMP5 [7:0] = 0000_0000 (452R / 600R) * VSP/NR
VMP5 [7:0] = 0000_0001 ((452R – 1R ) / 600R) * VSP/NR
VMP5 [7:0] = 0000_0010 ((452R – 2R ) / 600R) * VSP/NR
VMP5 [7:0] = 0000_0011 ((452R – 3R ) / 600R) * VSP/NR
VMP5 [7:0] = 0000_0100 ((452R – 4R ) / 600R) * VSP/NR
VMP5 [7:0] = 0000_0101 ((452R – 5R ) / 600R) * VSP/NR
: :
VMP5 [7:0] = 1000_0001 ((452R – 129R ) / 600R) * VSP/NR
VMP5 [7:0] = 1000_0010 ((452R – 130R ) / 600R) * VSP/NR
VinP/N100
VMP5 [7:0] = 1000_0011 ((452R – 131R ) / 600R) * VSP/NR
VMP5 [7:0] = 1000_0100 ((452R – 132R ) / 600R) * VSP/NR
VMP5 [7:0] = 1000_0101 ((452R – 133R ) / 600R) * VSP/NR
: :
VMP5 [7:0] = 1111_1011 ((452R – 251R ) / 600R) * VSP/NR
VMP5 [7:0] = 1111_1100 ((452R – 252R ) / 600R) * VSP/NR
VMP5 [7:0] = 1111_1101 ((452R – 253R ) / 600R) * VSP/NR
VMP5 [7:0] = 1111_1110 ((452R – 254R ) / 600R) * VSP/NR
VMP5 [7:0] = 1111_1111 ((452R – 255R ) / 600R) * VSP/NR
Table 5.22: VinP/N100

Reference
Macro adjustment value VinP/N128 formula
voltage
VMP6 [7:0] = 0000_0000 (427R / 600R) * VSP/NR
VMP6 [7:0] = 0000_0001 ((427R – 1R ) / 600R) * VSP/NR
VMP6 [7:0] = 0000_0010 ((427R – 2R ) / 600R) * VSP/NR
VMP6 [7:0] = 0000_0011 ((427R – 3R ) / 600R) * VSP/NR
VMP6 [7:0] = 0000_0100 ((427R – 4R ) / 600R) * VSP/NR
VMP6 [7:0] = 0000_0101 ((427R – 5R ) / 600R) * VSP/NR
: :
VMP6 [7:0] = 1000_0001 ((427R – 129R ) / 600R) * VSP/NR
VMP6 [7:0] = 1000_0010 ((427R – 130R ) / 600R) * VSP/NR
VinP/N128
VMP6 [7:0] = 1000_0011 ((427R – 131R ) / 600R) * VSP/NR
VMP6 [7:0] = 1000_0100 ((427R – 132R ) / 600R) * VSP/NR
VMP6 [7:0] = 1000_0101 ((427R – 133R ) / 600R) * VSP/NR
: :
VMP6 [7:0] = 1111_1011 ((427R – 251R ) / 600R) * VSP/NR
VMP6 [7:0] = 1111_1100 ((427R – 252R ) / 600R) * VSP/NR
VMP6 [7:0] = 1111_1101 ((427R – 253R ) / 600R) * VSP/NR
VMP6 [7:0] = 1111_1110 ((427R – 254R ) / 600R) * VSP/NR
VMP6 [7:0] = 1111_1111 ((427R – 255R ) / 600R) * VSP/NR
Table 5.23: VinP/N128

Himax Confidential -P.80-

Reference
Macro adjustment value VinP/N180 formula
voltage
VMP8 [7:0] = 0000_0000 (391R / 600R) * VSP/NR
VMP8 [7:0] = 0000_0001 ((391R – 1R ) / 600R) * VSP/NR
VMP8 [7:0] = 0000_0010 ((391R – 2R ) / 600R) * VSP/NR
VMP8 [7:0] = 0000_0011 ((391R – 3R ) / 600R) * VSP/NR
VMP8 [7:0] = 0000_0100 ((391R – 4R ) / 600R) * VSP/NR
VMP8 [7:0] = 0000_0101 ((391R – 5R ) / 600R) * VSP/NR
: :
VMP8 [7:0] = 1000_0001 ((391R – 129R ) / 600R) * VSP/NR
VMP8 [7:0] = 1000_0010 ((391R – 130R ) / 600R) * VSP/NR
VinP/N180
VMP8 [7:0] = 1000_0011 ((391R – 131R ) / 600R) * VSP/NR
VMP8 [7:0] = 1000_0100 ((391R – 132R ) / 600R) * VSP/NR
VMP8 [7:0] = 1000_0101 ((391R – 133R ) / 600R) * VSP/NR
: :
VMP8 [7:0] = 1111_1011 ((391R – 251R ) / 600R) * VSP/NR
VMP8 [7:0] = 1111_1100 ((391R – 252R ) / 600R) * VSP/NR
VMP8 [7:0] = 1111_1101 ((391R – 253R ) / 600R) * VSP/NR
VMP8 [7:0] = 1111_1110 ((391R – 254R ) / 600R) * VSP/NR
VMP8 [7:0] = 1111_1111 ((391R – 255R ) / 600R) * VSP/NR
Table 5.25: VinP/N180

Reference
Macro adjustment value VinP/N204 formula
voltage
VMP9 [7:0] = 0000_0000 (363R / 600R) * VSP/NR
VMP9 [7:0] = 0000_0001 ((363R – 1R ) / 600R) * VSP/NR
VMP9 [7:0] = 0000_0010 ((363R – 2R ) / 600R) * VSP/NR
VMP9 [7:0] = 0000_0011 ((363R – 3R ) / 600R) * VSP/NR
VMP9 [7:0] = 0000_0100 ((363R – 4R ) / 600R) * VSP/NR
VMP9 [7:0] = 0000_0101 ((363R – 5R ) / 600R) * VSP/NR
: :
VMP9 [7:0] = 1000_0001 ((363R – 129R ) / 600R) * VSP/NR
VMP9 [7:0] = 1000_0010 ((363R – 130R ) / 600R) * VSP/NR
VinP/N204
VMP9 [7:0] = 1000_0011 ((363R – 131R ) / 600R) * VSP/NR
VMP9 [7:0] = 1000_0100 ((363R – 132R ) / 600R) * VSP/NR
VMP9 [7:0] = 1000_0101 ((363R – 133R ) / 600R) * VSP/NR
: :
VMP9 [7:0] = 1111_1011 ((363R – 251R ) / 600R) * VSP/NR
VMP9 [7:0] = 1111_1100 ((363R – 252R ) / 600R) * VSP/NR
VMP9 [7:0] = 1111_1101 ((363R – 253R ) / 600R) * VSP/NR
VMP9 [7:0] = 1111_1110 ((363R – 254R ) / 600R) * VSP/NR
VMP9 [7:0] = 1111_1111 ((363R – 255R ) / 600R) * VSP/NR
Table 5.26: VinP/N204

Himax Confidential -P.81-

Reference
Macro adjustment value VinP/N228 formula
voltage
VMP11 [7:0] = 0000_0000 (327R / 600R) * VSP/NR
VMP11 [7:0] = 0000_0001 ((327R – 1R ) / 600R) * VSP/NR
VMP11 [7:0] = 0000_0010 ((327R – 2R ) / 600R) * VSP/NR
VMP11 [7:0] = 0000_0011 ((327R – 3R ) / 600R) * VSP/NR
VMP11 [7:0] = 0000_0100 ((327R – 4R ) / 600R) * VSP/NR
VMP11 [7:0] = 0000_0101 ((327R – 5R ) / 600R) * VSP/NR
: :
VMP11 [7:0] = 1000_0001 ((327R – 129R ) / 600R) * VSP/NR
VMP11 [7:0] = 1000_0010 ((327R – 130R ) / 600R) * VSP/NR
VinP/N228
VMP11 [7:0] = 1000_0011 ((327R – 131R ) / 600R) * VSP/NR
VMP11 [7:0] = 1000_0100 ((327R – 132R ) / 600R) * VSP/NR
VMP11 [7:0] = 1000_0101 ((327R – 133R ) / 600R) * VSP/NR
: :
VMP11 [7:0] = 1111_1011 ((327R – 251R ) / 600R) * VSP/NR
VMP11 [7:0] = 1111_1100 ((327R – 252R ) / 600R) * VSP/NR
VMP11 [7:0] = 1111_1101 ((327R – 253R ) / 600R) * VSP/NR
VMP11 [7:0] = 1111_1110 ((327R – 254R ) / 600R) * VSP/NR
VMP11 [7:0] = 1111_1111 ((327R – 255R ) / 600R) * VSP/NR
Table 5.28: VinP/N228

Reference
Macro adjustment value VinP/N236 formula
voltage
VMP12 [7:0] = 0000_0000 (319R / 600R) * VSP/NR
VMP12 [7:0] = 0000_0001 ((319R – 1R ) / 600R) * VSP/NR
VMP12 [7:0] = 0000_0010 ((319R – 2R ) / 600R) * VSP/NR
VMP12 [7:0] = 0000_0011 ((319R – 3R ) / 600R) * VSP/NR
VMP12 [7:0] = 0000_0100 ((319R – 4R ) / 600R) * VSP/NR
VMP12 [7:0] = 0000_0101 ((319R – 5R ) / 600R) * VSP/NR
: :
VMP12 [7:0] = 1000_0001 ((319R – 129R ) / 600R) * VSP/NR
VMP12 [7:0] = 1000_0010 ((319R – 130R ) / 600R) * VSP/NR
VinP/N236
VMP12 [7:0] = 1000_0011 ((319R – 131R ) / 600R) * VSP/NR
VMP12 [7:0] = 1000_0100 ((319R – 132R ) / 600R) * VSP/NR
VMP12 [7:0] = 1000_0101 ((319R – 133R ) / 600R) * VSP/NR
: :
VMP12 [7:0] = 1111_1011 ((319R – 251R ) / 600R) * VSP/NR
VMP12 [7:0] = 1111_1100 ((319R – 252R ) / 600R) * VSP/NR
VMP12 [7:0] = 1111_1101 ((319R – 253R ) / 600R) * VSP/NR
VMP12 [7:0] = 1111_1110 ((319R – 254R ) / 600R) * VSP/NR
VMP12 [7:0] = 1111_1111 ((319R – 255R ) / 600R) * VSP/NR
Table 5.29: VinP/N236

Himax Confidential -P.82-

Reference
Macro adjustment value VinP/N243 formula
voltage
VLP1 [6:0] = 000_0000 (286R / 600R) * VSP/NR
VLP1 [6:0] = 000_0001 ((286R – 2R ) / 600R) * VSP/NR
VLP1 [6:0] = 000_0010 ((286R – 4R ) / 600R) * VSP/NR
VLP1 [6:0] = 000_0011 ((286R – 6R ) / 600R) * VSP/NR
VLP1 [6:0] = 000_0100 ((286R – 8R ) / 600R) * VSP/NR
VLP1 [6:0] = 000_0101 ((286R – 10R ) / 600R) * VSP/NR
: :
VLP1 [6:0] = 100_0001 ((286R – 130R ) / 600R) * VSP/NR
VLP1 [6:0] = 100_0010 ((286R – 132R ) / 600R) * VSP/NR
VinP/N243
VLP1 [6:0] = 100_0011 ((286R – 134R ) / 600R) * VSP/NR
VLP1 [6:0] = 100_0100 ((286R – 136R ) / 600R) * VSP/NR
VLP1 [6:0] = 100_0101 ((286R – 138R ) / 600R) * VSP/NR
: :
VLP1 [6:0] = 111_1011 ((286R – 246R ) / 600R) * VSP/NR
VLP1 [6:0] = 111_1100 ((286R – 248R ) / 600R) * VSP/NR
VLP1 [6:0] = 111_1101 ((286R – 250R ) / 600R) * VSP/NR
VLP1 [6:0] = 111_1110 ((286R – 252R ) / 600R) * VSP/NR
VLP1 [6:0] = 111_1111 ((286R – 254R ) / 600R) * VSP/NR
Table 5.31: VinP/N243

Reference
Macro adjustment value VinP/N246 formula
voltage
VLP2 [6:0] = 000_0000 (278R / 600R) * VSP/NR
VLP2 [6:0] = 000_0001 ((278R – 2R ) / 600R) * VSP/NR
VLP2 [6:0] = 000_0010 ((278R – 4R ) / 600R) * VSP/NR
VLP2 [6:0] = 000_0011 ((278R – 6R ) / 600R) * VSP/NR
VLP2 [6:0] = 000_0100 ((278R – 8R ) / 600R) * VSP/NR
VLP2 [6:0] = 000_0101 ((278R – 10R ) / 600R) * VSP/NR
: :
VLP2 [6:0] = 100_0001 ((278R – 130R ) / 600R) * VSP/NR
VLP2 [6:0] = 100_0010 ((278R – 132R ) / 600R) * VSP/NR
VinP/N246
VLP2 [6:0] = 100_0011 ((278R – 134R ) / 600R) * VSP/NR
VLP2 [6:0] = 100_0100 ((278R – 136R ) / 600R) * VSP/NR
VLP2 [6:0] = 100_0101 ((278R – 138R ) / 600R) * VSP/NR
: :
VLP2 [6:0] = 111_1011 ((278R – 246R ) / 600R) * VSP/NR
VLP2 [6:0] = 111_1100 ((278R – 248R ) / 600R) * VSP/NR
VLP2 [6:0] = 111_1101 ((278R – 250R ) / 600R) * VSP/NR
VLP2 [6:0] = 111_1110 ((278R – 252R ) / 600R) * VSP/NR
VLP2 [6:0] = 111_1111 ((278R – 254R ) / 600R) * VSP/NR
Table 5.32: VinP/N246

Himax Confidential -P.83-

Reference
Macro adjustment value VinP/N250 formula
voltage
VLP4 [6:0] = 000_0000 (266R / 600R) * VSP/NR
VLP4 [6:0] = 000_0001 ((266R – 2R ) / 600R) * VSP/NR
VLP4 [6:0] = 000_0010 ((266R – 4R ) / 600R) * VSP/NR
VLP4 [6:0] = 000_0011 ((266R – 6R ) / 600R) * VSP/NR
VLP4 [6:0] = 000_0100 ((266R – 8R ) / 600R) * VSP/NR
VLP4 [6:0] = 000_0101 ((266R – 10R ) / 600R) * VSP/NR
: :
VLP4 [6:0] = 100_0001 ((266R – 130R ) / 600R) * VSP/NR
VLP4 [6:0] = 100_0010 ((266R – 132R ) / 600R) * VSP/NR
VinP/N250
VLP4 [6:0] = 100_0011 ((266R – 134R ) / 600R) * VSP/NR
VLP4 [6:0] = 100_0100 ((266R – 136R ) / 600R) * VSP/NR
VLP4 [6:0] = 100_0101 ((266R – 138R ) / 600R) * VSP/NR
: :
VLP4 [6:0] = 111_1011 ((266R – 246R ) / 600R) * VSP/NR
VLP4 [6:0] = 111_1100 ((266R – 248R ) / 600R) * VSP/NR
VLP4 [6:0] = 111_1101 ((266R – 250R ) / 600R) * VSP/NR
VLP4 [6:0] = 111_1110 ((266R – 252R ) / 600R) * VSP/NR
VLP4 [6:0] = 111_1111 ((266R – 254R ) / 600R) * VSP/NR
Table 5.34: VinP/N250

Reference
Macro adjustment value VinP/N252 formula
voltage
VLP5 [6:0] = 000_0000 (262R / 600R) * VSP/NR
VLP5 [6:0] = 000_0001 ((262R – 2R ) / 600R) * VSP/NR
VLP5 [6:0] = 000_0010 ((262R – 4R ) / 600R) * VSP/NR
VLP5 [6:0] = 000_0011 ((262R – 6R ) / 600R) * VSP/NR
VLP5 [6:0] = 000_0100 ((262R – 8R ) / 600R) * VSP/NR
VLP5 [6:0] = 000_0101 ((262R – 10R ) / 600R) * VSP/NR
: :
VLP5 [6:0] = 100_0001 ((262R – 130R ) / 600R) * VSP/NR
VLP5 [6:0] = 100_0010 ((262R – 132R ) / 600R) * VSP/NR
VinP/N252
VLP5 [6:0] = 100_0011 ((262R – 134R ) / 600R) * VSP/NR
VLP5 [6:0] = 100_0100 ((262R – 136R ) / 600R) * VSP/NR
VLP5 [6:0] = 100_0101 ((262R – 138R ) / 600R) * VSP/NR
: :
VLP5 [6:0] = 111_1011 ((262R – 246R ) / 600R) * VSP/NR
VLP5 [6:0] = 111_1100 ((262R – 248R ) / 600R) * VSP/NR
VLP5 [6:0] = 111_1101 ((262R – 250R ) / 600R) * VSP/NR
VLP5 [6:0] = 111_1110 ((262R – 252R ) / 600R) * VSP/NR
VLP5 [6:0] = 111_1111 ((262R – 254R ) / 600R) * VSP/NR
Table 5.35: VinP/N252

Himax Confidential -P.84-

Reference
Macro adjustment value VinP/N255 formula
voltage
VLP7 [6:0] = 000_0000 (254R / 600R) * VSP/NR
VLP7 [6:0] = 000_0001 ((254R – 2R ) / 600R) * VSP/NR
VLP7 [6:0] = 000_0010 ((254R – 4R ) / 600R) * VSP/NR
VLP7 [6:0] = 000_0011 ((254R – 6R ) / 600R) * VSP/NR
VLP7 [6:0] = 000_0100 ((254R – 8R ) / 600R) * VSP/NR
VLP7 [6:0] = 000_0101 ((254R – 10R ) / 600R) * VSP/NR
: :
VLP7 [6:0] = 100_0001 ((254R – 130R ) / 600R) * VSP/NR
VLP7 [6:0] = 100_0010 ((254R – 132R ) / 600R) * VSP/NR
VinP/N255
VLP7 [6:0] = 100_0011 ((254R – 134R ) / 600R) * VSP/NR
VLP7 [6:0] = 100_0100 ((254R – 136R ) / 600R) * VSP/NR
VLP7 [6:0] = 100_0101 ((254R – 138R ) / 600R) * VSP/NR
: :
VLP7 [6:0] = 111_1011 ((254R – 246R ) / 600R) * VSP/NR
VLP7 [6:0] = 111_1100 ((254R – 248R ) / 600R) * VSP/NR
VLP7 [6:0] = 111_1101 ((254R – 250R ) / 600R) * VSP/NR
VLP7 [6:0] = 111_1110 ((254R – 252R ) / 600R) * VSP/NR
VLP7 [6:0] = 111_1111 ((254R – 254R ) / 600R) * VSP/NR
Table 5.37: VinP/N255

Himax Confidential -P.85-

Grayscale Grayscale
voltage Formula voltage Formula
(NW/NB) (NW/NB)
V0/V255 VinP/N0 V44/V211 VinP/N40 - (VinP/N40 - VinP/N52)*(4R/12R)
V1/V254 VinP/N1 V45/V210 VinP/N40 - (VinP/N40 - VinP/N52)*(5R/12R)
V2/V253 VinP/N0 - (VinP/N0 - VinP/N1)*(R/2R) V46/V209 VinP/N40 - (VinP/N40 - VinP/N52)*(6R/12R)
V3/V252 VinP/N3 V47/V208 VinP/N40 - (VinP/N40 - VinP/N52)*(7R/12R)
V4/V251 VinP/N3 - (VinP/N3 - VinP/N5)*(1R/2R) V48/V207 VinP/N40 - (VinP/N40 - VinP/N52)*(8R/12R)
V5/V250 VinP/N5 V49/V206 VinP/N40 - (VinP/N40 - VinP/N52)*(9R/12R)
V6/V249 VinP/N5 - (VinP/N5 - VinP/N7)*(1R/2R) V50/V205 VinP/N40 - (VinP/N40 - VinP/N52)*(10R/12R)
V7/V248 VinP/N7 V51/V204 VinP/N40 - (VinP/N40 - VinP/N52)*(11R/12R)
V8/V247 VinP/N7 - (VinP/N7 - VinP/N9)*(1R/2R) V52/V203 VinP/N52
V9/V246 VinP/N9 V53/V202 VinP/N52 - (VinP/N52 - VinP/N76)*(1R/24R)
V10/V245 VinP/N9 - (VinP/N9 - VinP/N12)*(1R/3R) V54/V201 VinP/N52 - (VinP/N52 - VinP/N76)*(2R/24R)
V11/V244 VinP/N9 - (VinP/N9 - VinP/N12)*(2R/3R) V55/V200 VinP/N52 - (VinP/N52 - VinP/N76)*(3R/24R)
V12/V243 VinP/N12 V56/V199 VinP/N52 - (VinP/N52 - VinP/N76)*(4R/24R)
V13/V242 VinP/N12 - (VinP/N12 - VinP/N15)*(1R/3R) V57/V198 VinP/N52 - (VinP/N52 - VinP/N76)*(5R/24R)
V14/V241 VinP/N12 - (VinP/N12 - VinP/N15)*(2R/3R) V58/V197 VinP/N52 - (VinP/N52 - VinP/N76)*(6R/24R)
V15/V240 VinP/N15 V59/V196 VinP/N52 - (VinP/N52 - VinP/N76)*(7R/24R)
V16/V239 VinP/N15 - (VinP/N15 - VinP/N20)*(1R/5R) V60/V195 VinP/N52 - (VinP/N52 - VinP/N76)*(8R/24R)
V17/V238 VinP/N15 - (VinP/N15 - VinP/N20)*(2R/5R) V61/V194 VinP/N52 - (VinP/N52 - VinP/N76)*(9R/24R)
V18/V237 VinP/N15 - (VinP/N15 - VinP/N20)*(3R/5R) V62/V193 VinP/N52 - (VinP/N52 - VinP/N76)*(10R/24R)
V19/V236 VinP/N15 - (VinP/N15 - VinP/N20)*(4R/5R) V63/V192 VinP/N52 - (VinP/N52 - VinP/N76)*(11R/24R)
V20/V235 VinP/N20 V64/V191 VinP/N52 - (VinP/N52 - VinP/N76)*(12R/24R)
V21/V234 VinP/N20 - (VinP/N20 - VinP/N28)*(1R/8R) V65/V190 VinP/N52 - (VinP/N52 - VinP/N76)*(13R/24R)
V22/V233 VinP/N20 - (VinP/N20 - VinP/N28)*(2R/8R) V66/V189 VinP/N52 - (VinP/N52 - VinP/N76)*(14R/24R)
V23/V232 VinP/N20 - (VinP/N20 - VinP/N28)*(3R/8R) V67/V188 VinP/N52 - (VinP/N52 - VinP/N76)*(15R/24R)
V24/V231 VinP/N20 - (VinP/N20 - VinP/N28)*(4R/8R) V68/V187 VinP/N52 - (VinP/N52 - VinP/N76)*(16R/24R)
V25/V230 VinP/N20 - (VinP/N20 - VinP/N28)*(5R/8R) V69/V186 VinP/N52 - (VinP/N52 - VinP/N76)*(17R/24R)
V26/V229 VinP/N20 - (VinP/N20 - VinP/N28)*(6R/8R) V70/V185 VinP/N52 - (VinP/N52 - VinP/N76)*(18R/24R)
V27/V228 VinP/N20 - (VinP/N20 - VinP/N28)*(7R/8R) V71/V184 VinP/N52 - (VinP/N52 - VinP/N76)*(19R/24R)
V28/V227 VinP/N28 V72/V183 VinP/N52 - (VinP/N52 - VinP/N76)*(20R/24R)
V29/V226 VinP/N28 - (VinP/N28 - VinP/N40)*(1R/12R) V73/V182 VinP/N52 - (VinP/N52 - VinP/N76)*(21R/24R)
V30/V225 VinP/N28 - (VinP/N28 - VinP/N40)*(2R/12R) V74/V181 VinP/N52 - (VinP/N52 - VinP/N76)*(22R/24R)
V31/V224 VinP/N28 - (VinP/N28 - VinP/N40)*(3R/12R) V75/V180 VinP/N52 - (VinP/N52 - VinP/N76)*(23R/24R)
V32/V223 VinP/N28 - (VinP/N28 - VinP/N40)*(4R/12R) V76/V179 VinP/N76
V33/V222 VinP/N28 - (VinP/N28 - VinP/N40)*(5R/12R) V77/V178 VinP/N76 - (VinP/N76 - VinP/N100)*(1R/24R)
V34/V221 VinP/N28 - (VinP/N28 - VinP/N40)*(6R/12R) V78/V177 VinP/N76 - (VinP/N76 - VinP/N100)*(2R/24R)
V35/V220 VinP/N28 - (VinP/N28 - VinP/N40)*(7R/12R) V79/V176 VinP/N76 - (VinP/N76 - VinP/N100)*(3R/24R)
V36/V219 VinP/N28 - (VinP/N28 - VinP/N40)*(8R/12R) V80/V175 VinP/N76 - (VinP/N76 - VinP/N100)*(4R/24R)
V37/V218 VinP/N28 - (VinP/N28 - VinP/N40)*(9R/12R) V81/V174 VinP/N76 - (VinP/N76 - VinP/N100)*(5R/24R)
V38/V217 VinP/N28 - (VinP/N28 - VinP/N40)*(10R/12R) V82/V173 VinP/N76 - (VinP/N76 - VinP/N100)*(6R/24R)
V39/V216 VinP/N28 - (VinP/N28 - VinP/N40)*(11R/12R) V83/V172 VinP/N76 - (VinP/N76 - VinP/N100)*(7R/24R)
V40/V215 VinP/N40 V84/V171 VinP/N76 - (VinP/N76 - VinP/N100)*(8R/24R)
V41/V214 VinP/N40 - (VinP/N40 - VinP/N52)*(1R/12R) V85/V170 VinP/N76 - (VinP/N76 - VinP/N100)*(9R/24R)
V42/V213 VinP/N40 - (VinP/N40 - VinP/N52)*(2R/12R) V86/V169 VinP/N76 - (VinP/N76 - VinP/N100)*(10R/24R)
V43/V212 VinP/N40 - (VinP/N40 - VinP/N52)*(3R/12R) V87/V168 VinP/N76 - (VinP/N76 - VinP/N100)*(11R/24R)

Himax Confidential -P.86-

Grayscale Grayscale
voltage Formula voltage Formula
(NW/NB) (NW/NB)
V88/V167 VinP/N76 - (VinP/N76 - VinP/N100)*(12R/24R) V132/V123 VinP/N128 - (VinP/N128 - VinP/N156)*(4R/28R)
V89/V166 VinP/N76 - (VinP/N76 - VinP/N100)*(13R/24R) V133/V122 VinP/N128 - (VinP/N128 - VinP/N156)*(5R/28R)
V90/V165 VinP/N76 - (VinP/N76 - VinP/N100)*(14R/24R) V134/V121 VinP/N128 - (VinP/N128 - VinP/N156)*(6R/28R)
V91/V164 VinP/N76 - (VinP/N76 - VinP/N100)*(15R/24R) V135/V120 VinP/N128 - (VinP/N128 - VinP/N156)*(7R/28R)
V92/V163 VinP/N76 - (VinP/N76 - VinP/N100)*(16R/24R) V136/V119 VinP/N128 - (VinP/N128 - VinP/N156)*(8R/28R)
V93/V162 VinP/N76 - (VinP/N76 - VinP/N100)*(17R/24R) V137/V118 VinP/N128 - (VinP/N128 - VinP/N156)*(9R/28R)
V94/V161 VinP/N76 - (VinP/N76 - VinP/N100)*(18R/24R) V138/V117 VinP/N128 - (VinP/N128 - VinP/N156)*(10R/28R)
V95/V160 VinP/N76 - (VinP/N76 - VinP/N100)*(19R/24R) V139/V116 VinP/N128 - (VinP/N128 - VinP/N156)*(11R/28R)
V96/V159 VinP/N76 - (VinP/N76 - VinP/N100)*(20R/24R) V140/V115 VinP/N128 - (VinP/N128 - VinP/N156)*(12R/28R)
V97/V158 VinP/N76 - (VinP/N76 - VinP/N100)*(21R/24R) V141/V114 VinP/N128 - (VinP/N128 - VinP/N156)*(13R/28R)
V98/V157 VinP/N76 - (VinP/N76 - VinP/N100)*(22R/24R) V142/V113 VinP/N128 - (VinP/N128 - VinP/N156)*(14R/28R)
V99/V156 VinP/N76 - (VinP/N76 - VinP/N100)*(23R/24R) V143/V112 VinP/N128 - (VinP/N128 - VinP/N156)*(15R/28R)
V100/V155 VinP/N100 V144/V111 VinP/N128 - (VinP/N128 - VinP/N156)*(16R/28R)
V101/V154 VinP/N100 - (VinP/N100 - VinP/N128)*(1R/28R) V145/V110 VinP/N128 - (VinP/N128 - VinP/N156)*(17R/28R)
V102/V153 VinP/N100 - (VinP/N100 - VinP/N128)*(2R/28R) V146/V109 VinP/N128 - (VinP/N128 - VinP/N156)*(18R/28R)
V103/V152 VinP/N100 - (VinP/N100 - VinP/N128)*(3R/28R) V147/V108 VinP/N128 - (VinP/N128 - VinP/N156)*(19R/28R)
V104/V151 VinP/N100 - (VinP/N100 - VinP/N128)*(4R/28R) V148/V107 VinP/N128 - (VinP/N128 - VinP/N156)*(20R/28R)
V105/V150 VinP/N100 - (VinP/N100 - VinP/N128)*(5R/28R) V149/V106 VinP/N128 - (VinP/N128 - VinP/N156)*(21R/28R)
V106/V149 VinP/N100 - (VinP/N100 - VinP/N128)*(6R/28R) V150/V105 VinP/N128 - (VinP/N128 - VinP/N156)*(22R/28R)
V107/V148 VinP/N100 - (VinP/N100 - VinP/N128)*(7R/28R) V151/V104 VinP/N128 - (VinP/N128 - VinP/N156)*(23R/28R)
V108/V147 VinP/N100 - (VinP/N100 - VinP/N128)*(8R/28R) V152/V103 VinP/N128 - (VinP/N128 - VinP/N156)*(24R/28R)
V109/V146 VinP/N100 - (VinP/N100 - VinP/N128)*(9R/28R) V153/V102 VinP/N128 - (VinP/N128 - VinP/N156)*(25R/28R)
V110/V145 VinP/N100 - (VinP/N100 - VinP/N128)*(10R/28R) V154/V101 VinP/N128 - (VinP/N128 - VinP/N156)*(26R/28R)
V111/V144 VinP/N100 - (VinP/N100 - VinP/N128)*(11R/28R) V155/V100 VinP/N128 - (VinP/N128 - VinP/N156)*(27R/28R)
V112/V143 VinP/N100 - (VinP/N100 - VinP/N128)*(12R/28R) V156/V99 VinP/N156
V113/V142 VinP/N100 - (VinP/N100 - VinP/N128)*(13R/28R) V157/V98 VinP/N156 - (VinP/N156 - VinP/N180)*(1R/24R)
V114/V141 VinP/N100 - (VinP/N100 - VinP/N128)*(14R/28R) V158/V97 VinP/N156 - (VinP/N156 - VinP/N180)*(2R/24R)
V115/V140 VinP/N100 - (VinP/N100 - VinP/N128)*(15R/28R) V159/V96 VinP/N156 - (VinP/N156 - VinP/N180)*(3R/24R)
V116/V139 VinP/N100 - (VinP/N100 - VinP/N128)*(16R/28R) V160/V95 VinP/N156 - (VinP/N156 - VinP/N180)*(4R/24R)
V117/V138 VinP/N100 - (VinP/N100 - VinP/N128)*(17R/28R) V161/V94 VinP/N156 - (VinP/N156 - VinP/N180)*(5R/24R)
V118/V137 VinP/N100 - (VinP/N100 - VinP/N128)*(18R/28R) V162/V93 VinP/N156 - (VinP/N156 - VinP/N180)*(6R/24R)
V119/V136 VinP/N100 - (VinP/N100 - VinP/N128)*(19R/28R) V163/V92 VinP/N156 - (VinP/N156 - VinP/N180)*(7R/24R)
V120/V135 VinP/N100 - (VinP/N100 - VinP/N128)*(20R/28R) V164/V91 VinP/N156 - (VinP/N156 - VinP/N180)*(8R/24R)
V121/V134 VinP/N100 - (VinP/N100 - VinP/N128)*(21R/28R) V165/V90 VinP/N156 - (VinP/N156 - VinP/N180)*(9R/24R)
V122/V133 VinP/N100 - (VinP/N100 - VinP/N128)*(22R/28R) V166/V89 VinP/N156 - (VinP/N156 - VinP/N180)*(10R/24R)
V123/V132 VinP/N100 - (VinP/N100 - VinP/N128)*(23R/28R) V167/V88 VinP/N156 - (VinP/N156 - VinP/N180)*(11R/24R)
V124/V131 VinP/N100 - (VinP/N100 - VinP/N128)*(24R/28R) V168/V87 VinP/N156 - (VinP/N156 - VinP/N180)*(12R/24R)
V125/V130 VinP/N100 - (VinP/N100 - VinP/N128)*(25R/28R) V169/V86 VinP/N156 - (VinP/N156 - VinP/N180)*(13R/24R)
V12V129 VinP/N100 - (VinP/N100 - VinP/N128)*(26R/28R) V170/V85 VinP/N156 - (VinP/N156 - VinP/N180)*(14R/24R)
V127/V128 VinP/N100 - (VinP/N100 - VinP/N128)*(27R/28R) V171/V84 VinP/N156 - (VinP/N156 - VinP/N180)*(15R/24R)
V128/V127 VinP/N128 V172/V83 VinP/N156 - (VinP/N156 - VinP/N180)*(16R/24R)
V129/V126 VinP/N128 - (VinP/N128 - VinP/N156)*(1R/28R) V173/V82 VinP/N156 - (VinP/N156 - VinP/N180)*(17R/24R)
V130/V125 VinP/N128 - (VinP/N128 - VinP/N156)*(2R/28R) V174/V81 VinP/N156 - (VinP/N156 - VinP/N180)*(18R/24R)
V131/V124 VinP/N128 - (VinP/N128 - VinP/N156)*(3R/28R) V175/V80 VinP/N156 - (VinP/N156 - VinP/N180)*(19R/24R)

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Grayscale Grayscale
voltage Formula voltage Formula
(NW/NB) (NW/NB)
V176/V79 VinP/N156 - (VinP/N156 - VinP/N180)*(20R/24R) V216/V39 VinP/N216
V177/V78 VinP/N156 - (VinP/N156 - VinP/N180)*(21R/24R) V217/V38 VinP/N216 - (VinP/N216 - VinP/N228)*(1R/12R)
V178/V77 VinP/N156 - (VinP/N156 - VinP/N180)*(22R/24R) V218/V37 VinP/N216 - (VinP/N216 - VinP/N228)*(2R/12R)
V179/V76 VinP/N156 - (VinP/N156 - VinP/N180)*(23R/24R) V219/V36 VinP/N216 - (VinP/N216 - VinP/N228)*(3R/12R)
V180/V75 VinP/N180 V220/V35 VinP/N216 - (VinP/N216 - VinP/N228)*(4R/12R)
V181/V74 VinP/N180 - (VinP/N180 - VinP/N204)*(1R/24R) V221/V34 VinP/N216 - (VinP/N216 - VinP/N228)*(5R/12R)
V182/V73 VinP/N180 - (VinP/N180 - VinP/N204)*(2R/24R) V222/V33 VinP/N216 - (VinP/N216 - VinP/N228)*(6R/12R)
V183/V72 VinP/N180 - (VinP/N180 - VinP/N204)*(3R/24R) V223/V32 VinP/N216 - (VinP/N216 - VinP/N228)*(7R/12R)
V184/V71 VinP/N180 - (VinP/N180 - VinP/N204)*(4R/24R) V224/V31 VinP/N216 - (VinP/N216 - VinP/N228)*(8R/12R)
V185/V70 VinP/N180 - (VinP/N180 - VinP/N204)*(5R/24R) V225/V30 VinP/N216 - (VinP/N216 - VinP/N228)*(9R/12R)
V186/V69 VinP/N180 - (VinP/N180 - VinP/N204)*(6R/24R) V226/V29 VinP/N216 - (VinP/N216 - VinP/N228)*(10R/12R)
V187/V68 VinP/N180 - (VinP/N180 - VinP/N204)*(7R/24R) V227/V28 VinP/N216 - (VinP/N216 - VinP/N228)*(11R/12R)
V188/V67 VinP/N180 - (VinP/N180 - VinP/N204)*(8R/24R) V228/V27 VinP/N228
V189/V66 VinP/N180 - (VinP/N180 - VinP/N204)*(9R/24R) V229/V26 VinP/N228 - (VinP/N228 - VinP/N236)*(1R/8R)
V190/V65 VinP/N180 - (VinP/N180 - VinP/N204)*(10R/24R) V230/V25 VinP/N228 - (VinP/N228 - VinP/N236)*(2R/8R)
V191/V64 VinP/N180 - (VinP/N180 - VinP/N204)*(11R/24R) V231/V24 VinP/N228 - (VinP/N228 - VinP/N236)*(3R/8R)
V192/V63 VinP/N180 - (VinP/N180 - VinP/N204)*(12R/24R) V232/V23 VinP/N228 - (VinP/N228 - VinP/N236)*(4R/8R)
V193/V62 VinP/N180 - (VinP/N180 - VinP/N204)*(13R/24R) V233/V22 VinP/N228 - (VinP/N228 - VinP/N236)*(5R/8R)
V194/V61 VinP/N180 - (VinP/N180 - VinP/N204)*(14R/24R) V234/V21 VinP/N228 - (VinP/N228 - VinP/N236)*(6R/8R)
V195/V60 VinP/N180 - (VinP/N180 - VinP/N204)*(15R/24R) V235/V20 VinP/N228 - (VinP/N228 - VinP/N236)*(7R/8R)
V196/V59 VinP/N180 - (VinP/N180 - VinP/N204)*(16R/24R) V236/V19 VinP/N236
V197/V58 VinP/N180 - (VinP/N180 - VinP/N204)*(17R/24R) V237/V18 VinP/N236 - (VinP/N236 - VinP/N240)*(1R/4R)
V198/V57 VinP/N180 - (VinP/N180 - VinP/N204)*(18R/24R) V238/V17 VinP/N236 - (VinP/N236 - VinP/N240)*(2R/4R)
V199/V56 VinP/N180 - (VinP/N180 - VinP/N204)*(19R/24R) V239/V16 VinP/N236 - (VinP/N236 - VinP/N240)*(3R/4R)
V200/V55 VinP/N180 - (VinP/N180 - VinP/N204)*(20R/24R) V240/V15 VinP/N240
V201/V54 VinP/N180 - (VinP/N180 - VinP/N204)*(21R/24R) V241/V14 VinP/N240 - (VinP/N240 - VinP/N243)*(1R/3R)
V202/V53 VinP/N180 - (VinP/N180 - VinP/N204)*(22R/24R) V242/V13 VinP/N240 - (VinP/N240 - VinP/N243)*(2R/3R)
V203/V52 VinP/N180 - (VinP/N180 - VinP/N204)*(23R/24R) V243/V12 VinP/N243
V204/V51 VinP/N204 V244/V11 VinP/N243 - (VinP/N243 - VinP/N246)*(1R/3R)
V205/V50 VinP/N204 - (VinP/N204 - VinP/N216)*(1R/12R) V245/V10 VinP/N243 - (VinP/N243 - VinP/N246)*(2R/3R)
V206/V49 VinP/N204 - (VinP/N204 - VinP/N216)*(2R/12R) V246/V9 VinP/N246
V207/V48 VinP/N204 - (VinP/N204 - VinP/N216)*(3R/12R) V247/V8 VinP/N246 - (VinP/N246 - VinP/N248)*(1R/2R)
V208/V47 VinP/N204 - (VinP/N204 - VinP/N216)*(4R/12R) V248/V7 VinP/N248
V209/V46 VinP/N204 - (VinP/N204 - VinP/N216)*(5R/12R) V249/V6 VinP/N248 - (VinP/N248 - VinP/N250)*(1R/2R)
V210/V45 VinP/N204 - (VinP/N204 - VinP/N216)*(6R/12R) V250/V5 VinP/N250
V211/V44 VinP/N204 - (VinP/N204 - VinP/N216)*(7R/12R) V251/V4 VinP/N250 - (VinP/N250 - VinP/N252)*(1R/2R)
V212/V43 VinP/N204 - (VinP/N204 - VinP/N216)*(8R/12R) V252/V3 VinP/N252
V213/V42 VinP/N204 - (VinP/N204 - VinP/N216)*(9R/12R) V253/V2 VinP/N252 - (VinP/N252 - VinP/N254)*(1R/2R)
V214/V41 VinP/N204 - (VinP/N204 - VinP/N216)*(10R/12R) V254/V1 VinP/N254
V215/V40 VinP/N204 - (VinP/N204 - VinP/N216)*(11R/12R) V255/V0 VinP/N255
Table 5.38: Voltage calculation formula of 256-grayscale voltage (positive/negative polarity)

Himax Confidential -P.88-

5.7.2 Gray voltage generator for digital gamma correction

The HX8398-A digital gamma correction can reach the independent GAMMA curve of
RGB. HX8398-A utilizes DGC_LUT (Digital Gamma Correction Look Up Table) to
change input data from 8-bit into 10-bit and sends 10-bit data to Dithering circuit, and
then drive Source Driver via Dithering circuit.
luminance of R

luminance of R
R,G,B
Gary-scale of R Gamma Source Gary-scale of R
Dithering
correction Driver
8 (LUT) 10 8
luminance of G

luminance of G
Gary-scale of G Gary-scale of G
luminance of B

luminance of B
Gamma
register

Gary-scale of B Gary-scale of B

Figure 5.25: Block diagram of digital gamma correction

There are 126 bytes DGC LUT to set R, G, B gamma independently. When
DGC_EN=1, R, G, B gamma will mapping V0, V8, V16, ...., V240, V248, V255 voltage
to the LUT register setting gray level voltage.

LUT D7 D6 D5 D4 D3 D2 D1 D0 Mapping Gray Scale

1st R009 R008 R007 R006 R005 R004 R003 R002 R0
2nd R019 R018 R017 R016 R015 R014 R013 R012 R8
3rd R029 R028 R027 R026 R025 R024 R023 R022 R16
: : : : : : : : : :
: : : : : : : : : :
32th R319 R318 R317 R316 R315 R314 R313 R312 R240
33th R329 R328 R327 R326 R325 R324 R323 R322 R255
34th R001 R000 R011 R010 R021 R020 R031 R030 dithering
35th R041 R040 R051 R050 R061 R060 R071 R070 dithering
: : : : : : : : : :
: : : : : : : : : :
41th R281 R280 R291 R290 R301 R300 R311 R310 dithering
42th R321 R320 0 0 0 0 0 0 dithering
43th G009 G008 G007 G006 G005 G004 G003 G002 G0
44th G019 G018 G017 G016 G015 G014 G013 G012 G8
45th G029 G028 G027 G026 G025 G024 G023 G022 G16
: : : : : : : : : :
: : : : : : : : : :
74th G319 G318 G317 G316 G315 G314 G313 G312 G240
75th G329 G328 G327 G326 G325 G324 G323 G322 G255
76th G001 G000 G011 G010 G021 G020 G031 G030 dithering
77th G041 G040 G051 G050 G061 G060 G071 G070 dithering
: : : : : : : : : :
: : : : : : : : : :
83th G281 G280 G291 G290 G301 G300 G311 G310 dithering
84th G321 G320 0 0 0 0 0 0 dithering
85th B009 B008 B007 B006 B005 B004 B003 B002 B0
86th B019 B018 B017 B016 B015 B014 B013 B012 B8
87th B029 B028 B027 B026 B025 B024 B023 B022 B16
: : : : : : : : : :
: : : : : : : : : :
Himax Confidential -P.89-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
116th B319 B318 B317 B316 B315 B314 B313 B312 B240
117th B329 B328 B327 B326 B325 B324 B323 B322 B255
118th B001 B000 B011 B010 B021 B020 B031 B030 dithering
119th B041 B040 B051 B050 B061 B060 B071 B070 dithering
: : : : : : : : : :
: : : : : : : : : :
125th B281 B280 B291 B290 B301 B300 B311 B310 dithering
126th B321 B320 0 0 0 0 0 0 dithering
Table 5.39: DGC Look-up table

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5.8.1 Output or bi-directional (I/O) pins

Output or
After power on After hardware reset After software reset
bi-directional pins
TE Low Low Low
TE1 Low Low Low
SDO High-Z (Inactive) High-Z (Inactive) High-Z (Inactive)
CABC_PWM_OUT Low Low Low
GPO1~3 Low Low Low
HSOUT, VSOUT High High High
REQOUT Low Low Low

Table 5.40: Characteristics of output or bi-directional (I/O) pins

5.8.2 Input pins

After After
During power After power During power
Input pins hardware software
on process on off process
reset reset
RESX Input valid Input valid Input valid Input valid Input valid
CSX Input valid Input valid Input valid Input valid Input valid
DCX Input valid Input valid Input valid Input valid Input valid
SCL Input valid Input valid Input valid Input valid Input valid
DB23~DB0
Input valid Input valid Input valid Input valid Input valid
SDI_SDA
HSYNC Input valid Input valid Input valid Input valid Input valid
VSYNC Input valid Input valid Input valid Input valid Input valid
PCLK Input valid Input valid Input valid Input valid Input valid
DE Input valid Input valid Input valid Input valid Input valid
OSC, IM2, IM1,
Input valid Input valid Input valid Input valid Input valid
IM0,
PNSWAP,
Input valid Input valid Input valid Input valid Input valid
DSWAP0~1
FRM Input valid Input valid Input valid Input valid Input valid
IMAGE_UPDATE,
Input valid Input valid Input valid Input valid Input valid
LV_DETEC
TEST2, TEST1,
Low Low Low Low Low
TEST0
Table 5.41: Characteristics of input pins

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5.9.1 Register loading detection

Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the
display module, which indicates, if the display module loading function of factory
default values from OTP (or similar device) to registers of the display controller is
working properly. There are compared factory values of the OTP and register values
of the display controller by the display controller. If those both values (OTP and
register values) are same, there is inverted (=increased by 1) a bit, which is defined in
command “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of
this command is D7). If those both values are not same, this bit (D7) is not inverted
(=increased by 1).
The flow chart for this internal function is following:

Power on sequence
Sleep In (10h) HW reset
SW reset

Sleep Out Sleep In

RDDSDR`s D7=0
Mode Mode

Sleep Out (11h)

Loads and Compares OTP and register

values

NO
Are OTP and register
values the same

YES

D7 inverted

Figure 5.26: Sleep out flow chart–command and self-diagnostic functions

Himax Confidential -P.92-

Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the
display module, which indicates, if the display module is still running and meets
functionality requirements.
The internal function (=the display controller) is comparing, if the display module still
meets functionality requirements (e.g. booster voltage levels, timings, etc.). If
functionality requirement is met, 1 bit will be inverted (=increased by 1), which is
defined in command “Read Display Self- Diagnostic Result (0Fh)” (=RDDSDR) (The
used bit of this command is D6). If functionality requirement is not the same, this bit
(D6) is not inverted (=increased by 1). The flow chart for this internal function is shown
as below.

Power on sequence
Sleep In (10h) HW reset
SW reset

Sleep Out Sleep In

RDDSDR`s D6=0
Mode Mode

Sleep Out (11h)

Checks timing, voltage levels and other

functionalities

NO
Is functionality
requirement meet?

YES

D6 inverted

Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In–mode
toSleep Out -mode, before there is possible to check if Customer’s functionality requirements are met and
a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep
Out –command is sent in Sleep Out -mode.
Figure 5.27: Sleep out flow chart internal function detection

Himax Confidential -P.93-

The Power supply On/Off, Sleep In/Out and Display On/Off sequence is illustrated
below.
Power On Sequence Power Off Sequence

Power Up Normal Display

Wait 1ms

DSI Data Lane and

Clock Lane set to DISPOFF (28h)
LP11
Wait 3 frame

HW Reset SLPIN (10h)

Wait 5ms
Wait 50ms

SLPOUT (11h) Power Down

Wait 120ms

DISPON (29h)

Normal Display

Figure 5.28: Power on/off sequence

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VDD1 >1ms
HS_VCC

>1ms
VDD3 ≥10us

RESX
>1ms

Note: MIPI Data Lane and

CLK Lane must set LP11
before HW reset go high
MIPI Data & CLK lane
+/- no limit
>50ms >120ms

MIPI Video Packet

Host Command
Initial SLPOUT Initial+DISPON
Note: SLPOUT CMD can before or after Initial code, but after SLPOUT CMD must wait at least 120ms

Figure 5.29: VDD3/VDD1 input power on sequence

VDD1
HS_VCC
≥0us

VDD3

RESX ≥0us

MIPI Video Packet

>0ms

>3 frame
>5ms
Host Command
DISPOFF SLPIN

Figure 5.30: VDD3/VDD1 input power off sequence

Himax Confidential -P.95-

VDD1
HS_VCC >1ms

VSP ≥10us
>1ms

RESX
>1ms

Note: MIPI Data Lane and

CLK Lane must set LP11
MIPI Data & CLK lane before HW reset go high
+/- no limit
>50ms >120ms

MIPI Video Packet

Host Command
Initial SLPOUT Initial+DISPON
Note: SLPOUT CMD can before or after Initial code, but after SLPOUT CMD must wait at least 120ms

Figure 5.31: VSP/VDD1 input power on sequence

VDD1
HS_VCC

VSP ≥0us

RESX ≥0us

MIPI Video Packet

>0ms

>3 frame
>5ms
Host Command
DISPOFF SLPIN

Figure 5.32: VSP/VDD1 input power off sequence

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VDD1 >1ms
HS_VCC

VSP >1ms

VSN

≥10us

>1ms

RESX
>1ms

Note: MIPI Data Lane and

CLK Lane must set LP11
MIPI Data & CLK lane before HW reset go high

+/- no limit
>50ms >120ms

MIPI Video Packet

Host Command
Initial SLPOUT Initial+DISPON
Note: SLPOUT CMD can before or after Initial code, but after SLPOUT CMD must wait at least 120ms

Figure 5.33: VSP/VSN/VDD1 input power on sequence

VDD1
HS_VCC

≥0us
VSP

VSN
≥0us

RESX ≥0us

MIPI Video Packet

>0ms

>3 frame
>5ms
Host Command
DISPOFF SLPIN

Figure 5.34: VSP/VSN/VDD1 input power off sequence

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VDD1 >1ms

HS_VCC

VSP >1ms

VDD3 >1ms

VSN ≥10us

>1ms

RESX
>1ms

Note: MIPI Data Lane and

CLK Lane must set LP11
MIPI Data & CLK lane before HW reset go high
+/- no limit
>50ms >120ms

MIPI Video Packet

Host Command
Initial SLPOUT Initial+DISPON
Note: SLPOUT CMD can before or after Initial code, but after SLPOUT CMD must wait at least 120ms

Figure 5.35: VDD3/VSP/VSN/VDD1 input power on sequence

VDD1
HS_VCC
≥0us
VSP

VDD3 ≥0us

VSN
≥0us

RESX ≥0us

MIPI Video Packet

>0ms

>3 frame
>5ms
Host Command
DISPOFF SLPIN

Figure 5.36: VDD3/VSP/VSN/VDD1 input power off sequence

Himax Confidential -P.98-

5.10.5 VSP/VSN/VGH/VGL iput power(PCCS[2:0]=100)

VDD1
>1ms
HS_VCC

VGH

VGL

>1ms

VSP

VSN

>1ms
≥10us

RESX
>1ms

Note: MIPI Data Lane and

CLK Lane must set LP11
MIPI Data & CLK lane before HW reset go high

+/- no limit
>50ms >120ms

MIPI Video Packet

Host Command
Initial SLPOUT Initial+DISPON
Note: SLPOUT CMD can before or after Initial code, but after SLPOUT CMD must wait at least 120ms

Figure 5.37: VSP/VSN/VGH/VGL input power on sequence

Himax Confidential -P.99-

VGL

≥0us
VSP

VSN

RESX ≥0us

MIPI Video Packet

>0ms

>3 frame
>5ms
Host Command
DISPOFF SLPIN

Figure 5.38: VSP/VSN/VGH/VGL input power off sequence

Himax Confidential -P.100-

The uncontrolled power off means a situation when e.g. there is removed a battery
without the controlled power off sequence. There will not be any damages for the
display module or the display module will not cause any damages for the host or lines
of the interface. At an uncontrolled power off the display will go blank and there will
not be any visible effects within 1 second on the display (blank display) and remains
blank until “Power On Sequence” powers it up.

Note: HX8398-A is support the noise reject filter (20ns) to reject spike or noise.
20n
S

Less than 20nS width positive spike will be

rejected.

GAS circuit GAS Filter circuit Logic circuit

Himax Confidential -P.101-

The general block diagram of the CABC and the brightness control is illustrated
below:

Display Data
Image data
Generator

C[1:0]= ‘00’ à off

Display Data
Contents Analysis C[1:0]= ‘01’, ‘10’,
‘11’ à on

CABC Gain / Duty

CABC Block

DBV[7:0] (R52h)
(BL=0)

PWM_CLK Brightness Control PWM_OUT

PWM Clock Devider
(FoscD) Block (BL=1)

CABC[1:0] (R55h)

DBV[7:0] (R51h)
SEL_PWMCLK[2:0]( C9h) BCTRL, BL(R53h)
CMB[7:0](R5Eh)
INVPLUS
SEL_BLDUTY
PWM_PERIOD
(RC9h)

Figure 5.39: CABC block diagram

Himax Confidential -P.102-

HX8398-A can support two module architectures for CABC operation. The BL bit
setting of R53h can be used to select used display module architecture. White LED
driver circuit for display backlight is located on the main PWB, not in the display
module both in architecture I and II.

 Architecture I

Main PWB Display module

Display
interface LCD
MPU 1. BL=”1" of R53h
driver
LCD Panel 2. LED backlight brightness for the
CABC_PWM_
display is controlled by external
OUT output “BC”
VBAT
W-LED
driver LEDs
Power
lines

 Architecture II

Main PWB Display module

Display
interface LCD 1. BL=”0" of R53h
MPU 2. LED backlight brightness data
driver
LCD Panel for the display is read DBV[7:0]
bits of R52h
3. Read commands R52h should
VBAT be synchronized with VSYNC
W-LED
driver LEDs
Power
lines
Figure 5.40: Module architecture

Himax Confidential -P.103-

There are DBG0~8[6:0] register bits in CABC block to define the “CABC gain”/ “CABC
duty” table. Every DBGx[6:0] has 33 gain/duty value setting.

After one-frame display data content analysis, LSI will generate one CABC gain /
CABC duty value calculated from DBG0~8[6:0] register bits setting (by using
interpolated method) for display data generating and for backlight PWM pulse
generating.

Please note that the CABC gain / CABC duty value calculated by the LSI is one of the
33 gain/duty value setting in DBGxx[6:0].

Please note that : Duty ( valid level period (LED on) / one complete period)=1/ gain.
D B G0

G a in c u r v e

DBG1

D B G2

D B G3

D B G4
G a in
D B G5

SA V EPO W ER D B G6
D B G7

DBG8

0 32 64 96 128 160 192 224 256

O n e f ra m e d is p la y d a t a
c o n t e n t a n a ly s is

Figure 5.41: CABC gain / CABC duty generation

Himax Confidential -P.104-

There is an external output signal from brightness block, CABC_PWM_OUT, to

control the LED driver IC in order to control display brightness.

There are resister bits, DBV[7:0] of R51h, for display brightness of manual brightness
setting. The CABC_PWM_OUT duty is calculated as (DBV[7:0])/255 x CABC duty
(generated after one-frame display data content analysis).

For ex: CABC_PWM_OUT period=2.95 ms, and DBV[7:0](R51h)=‘228DEC’ and

CABC duty is 74%. Then CABC_PWM_OUT duty=(228) / 255 x 74.42%66.54%.
Correspond to the CABC_PWM_OUT period=2.95 ms, the high-level of
CABC_PWM_OUT (high effective) = 1.96ms, and the low-level of CABC_PWM_OUT
=0.99ms.

One Period (tpw)

ON
CABC_
Display
PWM_OUT
Brightness
(INVPLUS=`1`)
OFF

Duty = 100% Duty = 100% Duty = 33% Duty = 66.57%

OFF Maximum

Figure 5.42: CABC_PWM_OUT output duty

Symbol Parameter Min. Max. Unit Description

tpw Pulse width 0.0333 8.33 ms -
Table 5.42: CABC timing table

Note1: The signal rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
Note2: The pulse width range by setting CABC related registers is locate between 0.0333ms to 8.33ms.

When Architecture II module is used (BL=’0’) with the example below, the
CABC_PWM_OUT is always output low and the DBV[7:0](R51h) will be read a value
as 169DEC ((169)/255 66.27%).

Himax Confidential -P.105-

CABC function is automatically reduced backlight brightness based on image

contents. In the case of the combination with the CABC or manual brightness setting,
display brightness is too dark. It must affect to image quality degradation. CABC
minimum brightness setting (CMB[7:0] bits of R5Eh) is to avoid too much brightness
reduction.

When CABC is active, CABC can not reduce the display brightness to less than
CABC minimum brightness setting. Image processing function is worked as normal,
even if the brightness can not be changed.

This function does not affect to the other function, manual brightness setting. Manual
brightness can be set the display brightness to less than CABC minimum brightness.
Smooth transition and dimming function can be worked as normal.

When display brightness is turned off (BCTRL=’0’ of R53h), CABC minimum

brightness setting is ignored. “CMB[7:0], Read CABC minimum brightness
(R5Fh)“ always read the setting value of “CMB[7:0], Write CABC minimum brightness
(R5Eh)”

Himax Confidential -P.106-

5.13 Temperature sensor

HX8398-A support the temperature sensor function. This function would make the
driver to change the relative setting on the High_Temp and Low_Temp to satisfy with
different temperature environment.

User can elasticity to define the tempeture upper boundary and lower boundary. And
the Driver can auto to change the other power valtage / source drvring. The Tempeture
sensor can cover the panel GIP deviation in different temperature, Driver can change
the GIP Timing automatically.

H_TEMP[4:0]

L_TEMP[4:0]

H_STATE

ADCOUT_AVG[4:0] N_STATE
H_STATE
L_STATE
N_STATE

L_STATE

Figure 5.43: Tempeture sensor diagram

Himax Confidential -P.107-

HX8398-A support display data from GRAM in Idle mode. User can use 2Ch/3Ch
command to write image data into GRAM. R/G/B MSB bit data stored in GRAM.
GRAM write direction not support MX/MY/MV function.

Enter Idle Mode Sequence Exit Idle Mode Sequence

Host starts entry to Host starts to exit Idle

Idle Mode Mode

MCU transfers Idle MCU transfers Idle

Mode On command Mode Off command

Display Idle Mode On Display Idle Mode Off

MCU transfers Image

MCU transfers Image
Data in Command
Data in Video Mode
Mode

Display receives
2Ch/3Ch commands Display switch to
and switch to 1bpp Video mode
Idle mode
Figure 5.44: Idle Mode On/Off Sequence

Himax Confidential -P.108-

5.15.1 OTP table

OTP_INDE
B7 B6 B5 B4 B3 B2 B1 B0
X (HEX)
000 ID1_1[7:0]
001 ID2_1[7:0]
002 ID3_1[7:0]
003 ID4_1[7:0]
004 ID1_2[7:0]
005 ID2_2[7:0]
006 ID3_2[7:0]
007 ID4_2[7:0]
008 ID1_3[7:0]
009 ID2_3[7:0]
00A ID3_3[7:0]
00B ID4_3[7:0]
00C NVALID_ID1 NVALID_ID2 NVALID_ID3 - - - - -
00D VCMC_F1[7:0]
00E VCMC_B1[7:0]
00F VCMC_F2[7:0]
010 VCMC_B2[7:0]
011 VCMC_F3[7:0]
012 VCMC_B3[7:0]
VCMC_B3[ VCMC_B3[ VCMC_B2[ VCMC_B2[ VCMC_B1[ VCMC_B1[
013 - -
8] 8] 8] 8] 8] 8]
NVALID_V NVALID_V NVALID_V
014 - - - - -
CMC1 CMC2 CMC3
NVALID_P GS_PANE REV_PAN BGR_PAN
015 - - - SS_PANEL
ANEL L EL EL
NVALID_I2
016 I2C_SA[6:0]
C_SA
NVALID_P DSTBY_O VSP_FBO
02F - AP[2:0] DSTB
OWER PT FF
030 - VCI_LDOS[1:0] VRHP[4:0]
031 VPPS[2:0] VRHN[4:0]
032 - - - - - XDK[2:0]
033 - - CLK_OPT2 CLK_OPT1 FS0[3:0]
034 FS1[3:0] FS2[3:0]
035 - VGHS[9:8] BTP[4:0]
036 - VGLS[9:8] BTN[4:0]
037 VGHS[7:0]
038 VGLS[7:0]
VCIREG_O VGLO2_E
039 - VGLO2S[4:0]
PT N
03A DT1[1:0] DT2[1:0] DCDIV[3:0]
03B - DCS[2:0] - DC[2:0]
03C - DTPS[2:0] - DTP[2:0]
03D - DTNS[2:0] - DTN[2:0]
NVALID_G
03E APF_EN GASIOVCC_OPT[1:0] - GASVCI_OPT[2:0]
AS
03F - GASVSN_OPT[2:0] - GASVSP_OPT[2:0]
VGH1_DIS
040 - GASVGL_OPT[1:0] - - GASVGH_OPT[1:0]
CHARGE
NVALID_D
042 ZZ_LR ZZ_EO ZZ_2PL - NW[2:0]
ISP
MESSI_EN
043 H_RES[2:0] - - - -
B

Himax Confidential -P.109-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
044 NL[7:0]
045 BP [7:0]
046 FP [7:0]
047 RTN[7:0]
048 - END_SET END_SET_0[1:0] - INIT_SET INIT_SET_0[1:0]
049 - - INIT_SET_1[1:0] - - INIT_SET_2[1:0]
04A - - END_SET_1[1:0] - - END_SET_2[1:0]
INIT_SD_S INIT_VCO END_SD_ END_VCO
04B - - - -
EL M_SEL SEL M_SEL
DISP_BIST
04C FRM_PATTERN_CYCLE[3:0] FRM_SCAN_CYCLE[2:0]
_EN
NVALID_C
051 - - DX2_EN - - - -
YC
052 GEN_ON[7:0]
053 GEN_OFF[7:0]
054 SPON[7:0]
055 SPOFF[7:0]
056 CON[7:0]
057 COFF[7:0]
058 CON1[7:0]
059 COFF1[7:0]
05A EQON1[7:0]
05B SON[7:0]
05C SOFF[7:0]
05D SAP1_P[3:0] SAP1_N[3:0]
05E - - - - - SAP2[2:0]
05F DX2OFF[7:0]
060 SPON_MPU[7:0]
061 SPOFF_MPU[7:0]
062 CON_MPU[7:0]
063 COFF_MPU[7:0]
064 CON1_MPU[7:0]
065 COFF1_MPU[7:0]
066 EQON1_MPU[7:0]
067 SON_MPU[7:0]
068 SOFF_MPU[7:0]
069 DX2OFF_MPU[7:0]
NVALID_S
074 DSISETUP0[6:0]
ETDSI
075 DSISETUP1[7:0]
NVALID_C DYN_CEH
080 - - - - - -
EMODE _EN
081 HUE_MODE[1:0] SE_MODE[1:0] BE_MODE[1:0] CE_MODE[1:0]
NVALID_S TSENSOR EXT_TPS_
0CE LT_EN HT_EN TEMP_GAP[2:0]
ENSOR _EN EN
L_VGLS2[
0CF - - L_TEMP[4:0]
4]
0D0 L_SAP1_P[3:0] L_SAP1_N[3:0]
0D1 L_VGLS2[3:0] L_VGLS[9:8] L_VGHS[9:8]
0D2 L_VGHS[7:0]
0D3 L_VGLS[7:0]
0D4 L_COFF[7:0]
0D5 L_COFF1[7:0]
0D6 L_SOFF[7:0]
0D7 - - - L_VCOM[4:0]
H_VGLS2[
0D8 - - H_TEMP[4:0]
4]
0D9 H_SAP1_P[3:0] H_SAP1_N[3:0]
0DA H_VGLS2[3:0] H_VGLS[9:8] H_VGHS[9:8]
Himax Confidential -P.110-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
0DB H_VGHS[7:0]
0DC H_VGLS[7:0]
0DD H_COFF[7:0]
0DE H_COFF1[7:0]
0DF H_SOFF[7:0]
0E0 - - - H_VCOM[4:0]
NVALID_1 1BRAM_E
0E1 - - - NW_I[2:0]
BPP N
0E2 BP_I[7:0]
0E3 FP_I[7:0]
0E4 RTN_I[7:0]
0E5 VCMC_F_I[7:0]
0E6 VCMC_B_I[7:0]
VCMC_B_I VCMC_F_I
0E7 AP_I[2:0] - - -
[8] [8]
0E8 FS0_I[3:0] FS1_I[3:0]
0E9 FS2_I[3:0] - - - -
NVALID_C PWM_PER EN_DIM_M SEL_BLDU
0ED SEL_PWMCLK[2:0] INVPULS
ABC IOD[16] IX TY
0EE PWM_PERIOD[15:8]
0EF PWM_PERIOD[7:0]
NVALID_G EQ_DELAY_HSYNC[1:
100 - GIP_EQ_MODE[1:0] - -
IP_D3 0]
101 - - - - - - EQ_DISC[1:0]
102 EQ_DELAY_ON1[7:0]
103 EQ_DELAY_ON2[7:0]
104 EQ_DELAY_OFF1[7:0]
105 EQ_DELAY_OFF2[7:0]
106 GTO[7:0]
107 GNO[7:0]
108 USER_GIP_GATE[7:0]
109 USER_GIP_GATE1[7:0]
10A SHR0_3[3:0] SHR0_2[3:0]
10B SHR0_1[3:0] SHR0[11:8]
10C SHR0[7:0]
10D - - - - SHR0_GS[11:8]
10E SHR0_GS[7:0]
10F SHR1_3[3:0] SHR1_2[3:0]
110 SHR1_1[3:0] SHR1[11:8]
111 SHR1[7:0]
112 - - - - SHR1_GS[11:8]
113 SHR1_GS[7:0]
114 SHR2_3[3:0] SHR2_2[3:0]
115 SHR2_1[3:0] SHR2[11:8]
116 SHR2[7:0]
117 - - - - SHR2_GS[11:8]
118 SHR2_GS[7:0]
119 SHP0[3:0] SCP[3:0]
11A SHP2[3:0] SHP1[3:0]
11B CHR0[7:0]
11C CHR0_GS[7:0]
11D CHP0[3:0] CCP0[3:0]
11E CHR1[7:0]
11F CHR1_GS[7:0]
120 CHP1[3:0] CCP1[3:0]
121 vbp_setting[7:0]
vbp_self_le OVERLAP
122 - - DCHG1R[1:0] DCHG2R[1:0]
arning _OPT
13B NVALID_GI CGTS_L_IN COS1_L[5:0]
Himax Confidential -P.111-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
P_D5 V[1]
CGTS_R_IN
13C - COS1_R[5:0]
V[1]
CGTS_L_IN
13D - COS2_L[5:0]
V[2]
CGTS_R_IN
13E - COS2_R[5:0]
V[2]
CGTS_L_IN
13F - COS3_L[5:0]
V[3]
CGTS_R_IN
140 - COS3_R[5:0]
V[3]
CGTS_L_IN
141 - COS4_L[5:0]
V[4]
CGTS_R_IN
142 - COS4_R[5:0]
V[4]
CGTS_L_IN
143 - COS5_L[5:0]
V[5]
CGTS_R_IN
144 - COS5_R[5:0]
V[5]
CGTS_L_IN
145 - COS6_L[5:0]
V[6]
CGTS_R_IN
146 - COS6_R[5:0]
V[6]
CGTS_L_IN
147 - COS7_L[5:0]
V[7]
CGTS_R_IN
148 - COS7_R[5:0]
V[7]
CGTS_L_IN
149 - COS8_L[5:0]
V[8]
CGTS_R_IN
14A - COS8_R[5:0]
V[8]
CGTS_L_IN
14B - COS9_L[5:0]
V[9]
CGTS_R_IN
14C - COS9_R[5:0]
V[9]
CGTS_L_IN
14D - COS10_L[5:0]
V[10]
CGTS_R_IN
14E - V[10]
COS10_R[5:0]
CGTS_L_IN
14F - COS11_L[5:0]
V[11]
CGTS_R_IN
150 - COS11_R[5:0]
V[11]
CGTS_L_IN
151 - V[12]
COS12_L[5:0]
CGTS_R_IN
152 - COS12_R[5:0]
V[12]
CGTS_L_IN
153 - COS13_L[5:0]
V[13]
CGTS_R_IN
154 - COS13_R[5:0]
V[13]
CGTS_L_IN
155 - COS14_L[5:0]
V[14]
CGTS_R_IN
156 - COS14_R[5:0]
V[14]
CGTS_L_IN
157 - COS15_L[5:0]
V[15]
CGTS_R_IN
158 - COS15_R[5:0]
V[15]
CGTS_L_IN
159 - COS16_L[5:0]
V[16]
CGTS_R_IN
15A - COS16_R[5:0]
V[16]
CGTS_L_IN
15B - COS17_L[5:0]
V[17]
15C - CGTS_R_IN COS17_R[5:0]
Himax Confidential -P.112-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
V[17]
CGTS_L_IN
15D - COS18_L[5:0]
V[18]
CGTS_R_IN
15E - COS18_R[5:0]
V[18]
CGTS_L_IN
15F - COS19_L[5:0]
V[19]
CGTS_R_IN
160 - COS19_R[5:0]
V[19]
CGTS_L_IN
161 - COS20_L[5:0]
V[20]
CGTS_R_IN
162 - COS20_R[5:0]
V[20]
NVALID_GI CGOUT_L_
163 COS1_L_GS[5:0]
P_D6 HIZ_IN[1]
CGOUT_R_
164 - COS1_R_GS[5:0]
HIZ_IN[1]
CGOUT_L_
165 - COS2_L_GS[5:0]
HIZ_IN[2]
CGOUT_R_
166 - COS2_R_GS[5:0]
HIZ_IN[2]
CGOUT_L_
167 - COS3_L_GS[5:0]
HIZ_IN[3]
CGOUT_R_
168 - COS3_R_GS[5:0]
HIZ_IN[3]
CGOUT_L_
169 - COS4_L_GS[5:0]
HIZ_IN[4]
CGOUT_R_
16A - COS4_R_GS[5:0]
HIZ_IN[4]
CGOUT_L_
16B - COS5_L_GS[5:0]
HIZ_IN[5]
CGOUT_R_
16C - COS5_R_GS[5:0]
HIZ_IN[5]
CGOUT_L_
16D - COS6_L_GS[5:0]
HIZ_IN[6]
CGOUT_R_
16E - COS6_R_GS[5:0]
HIZ_IN[6]
CGOUT_L_
16F - HIZ_IN[7]
COS7_L_GS[5:0]
CGOUT_R_
170 - COS7_R_GS[5:0]
HIZ_IN[7]
CGOUT_L_
171 - COS8_L_GS[5:0]
HIZ_IN[8]
CGOUT_R_
172 - HIZ_IN[8]
COS8_R_GS[5:0]
CGOUT_L_
173 - COS9_L_GS[5:0]
HIZ_IN[9]
CGOUT_R_
174 - COS9_R_GS[5:0]
HIZ_IN[9]
CGOUT_L_
175 - COS10_L_GS[5:0]
HIZ_IN[10]
CGOUT_R_
176 - COS10_R_GS[5:0]
HIZ_IN[10]
CGOUT_L_
177 - COS11_L_GS[5:0]
HIZ_IN[11]
CGOUT_R_
178 - COS11_R_GS[5:0]
HIZ_IN[11]
CGOUT_L_
179 - COS12_L_GS[5:0]
HIZ_IN[12]
CGOUT_R_
17A - COS12_R_GS[5:0]
HIZ_IN[12]
CGOUT_L_
17B - COS13_L_GS[5:0]
HIZ_IN[13]
CGOUT_R_
17C - COS13_R_GS[5:0]
HIZ_IN[13]
17D - CGOUT_L_ COS14_L_GS[5:0]
Himax Confidential -P.113-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
HIZ_IN[14]
CGOUT_R_
17E - COS14_R_GS[5:0]
HIZ_IN[14]
CGOUT_L_
17F - COS15_L_GS[5:0]
HIZ_IN[15]
CGOUT_R_
180 - COS15_R_GS[5:0]
HIZ_IN[15]
CGOUT_L_
181 - COS16_L_GS[5:0]
HIZ_IN[16]
CGOUT_R_
182 - COS16_R_GS[5:0]
HIZ_IN[16]
CGOUT_L_
183 - COS17_L_GS[5:0]
HIZ_IN[17]
CGOUT_R_
184 - COS17_R_GS[5:0]
HIZ_IN[17]
CGOUT_L_
185 - COS18_L_GS[5:0]
HIZ_IN[18]
CGOUT_R_
186 - COS18_R_GS[5:0]
HIZ_IN[18]
CGOUT_L_
187 - COS19_L_GS[5:0]
HIZ_IN[19]
CGOUT_R_
188 - COS19_R_GS[5:0]
HIZ_IN[19]
CGOUT_L_
189 - COS20_L_GS[5:0]
HIZ_IN[20]
CGOUT_R_
18A - COS20_R_GS[5:0
HIZ_IN[20]
NVALID_G
18B - - - - - - -
IP_D8
INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT2 INIT_0_SEL_CGOUT3 INIT_0_SEL_CGOUT4
18C
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
INIT_0_SEL_CGOUT5 INIT_0_SEL_CGOUT6 INIT_0_SEL_CGOUT7 INIT_0_SEL_CGOUT8
18D
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
INIT_0_SEL_CGOUT9 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1
18E
_L[1:0] 0_L[1:0] 1_L[1:0] 2_L[1:0]
INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1
18F
3_L[1:0] 4_L[1:0] 5_L[1:0] 6_L[1:0]
INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT2
190
7_L[1:0] 8_L[1:0] 9_L[1:0] 0_L[1:0]
INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT2 INIT_0_SEL_CGOUT3 INIT_0_SEL_CGOUT4
191
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
INIT_0_SEL_CGOUT5 INIT_0_SEL_CGOUT6 INIT_0_SEL_CGOUT7 INIT_0_SEL_CGOUT8
192
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
INIT_0_SEL_CGOUT9 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1
193
_R[1:0] 0_R[1:0] 1_R[1:0] 2_R[1:0]
INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1
194
3_R[1:0] 4_R[1:0] 5_R[1:0] 6_R[1:0]
INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT1 INIT_0_SEL_CGOUT2
195
7_R[1:0] 8_R[1:0] 9_R[1:0] 0_R[1:0]
INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT2 INIT_1_SEL_CGOUT3 INIT_1_SEL_CGOUT4
196
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
INIT_1_SEL_CGOUT5 INIT_1_SEL_CGOUT6 INIT_1_SEL_CGOUT7 INIT_1_SEL_CGOUT8
197
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
INIT_1_SEL_CGOUT9 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1
198
_L[1:0] 0_L[1:0] 1_L[1:0] 2_L[1:0]
INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1
199
3_L[1:0] 4_L[1:0] 5_L[1:0] 6_L[1:0]
INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT2
19A
7_L[1:0] 8_L[1:0] 9_L[1:0] 0_L[1:0]
INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT2 INIT_1_SEL_CGOUT3 INIT_1_SEL_CGOUT4
19B
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
19C INIT_1_SEL_CGOUT5 INIT_1_SEL_CGOUT6 INIT_1_SEL_CGOUT7 INIT_1_SEL_CGOUT8

Himax Confidential -P.114-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
INIT_1_SEL_CGOUT9 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1
19D
_R[1:0] 0_R[1:0] 1_R[1:0] 2_R[1:0]
INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1
19E
3_R[1:0] 4_R[1:0] 5_R[1:0] 6_R[1:0]
INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT1 INIT_1_SEL_CGOUT2
19F
7_R[1:0] 8_R[1:0] 9_R[1:0] 0_R[1:0]
END_0_SEL_CGOUT1 END_0_SEL_CGOUT2 END_0_SEL_CGOUT3 END_0_SEL_CGOUT4
1A0
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
END_0_SEL_CGOUT5 END_0_SEL_CGOUT6 END_0_SEL_CGOUT7 END_0_SEL_CGOUT8
1A1
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
END_0_SEL_CGOUT9 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1
1A2
_L[1:0] 0_L[1:0] 1_L[1:0] 2_L[1:0]
END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1
1A3
3_L[1:0] 4_L[1:0] 5_L[1:0] 6_L[1:0]
END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT2
1A4
7_L[1:0] 8_L[1:0] 9_L[1:0] 0_L[1:0]
END_0_SEL_CGOUT1 END_0_SEL_CGOUT2 END_0_SEL_CGOUT3 END_0_SEL_CGOUT4
1A5
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
END_0_SEL_CGOUT5 END_0_SEL_CGOUT6 END_0_SEL_CGOUT7 END_0_SEL_CGOUT8
1A6
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
END_0_SEL_CGOUT9 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1
1A7
_R[1:0] 0_R[1:0] 1_R[1:0] 2_R[1:0]
END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1
1A8
3_R[1:0] 4_R[1:0] 5_R[1:0] 6_R[1:0]
END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT1 END_0_SEL_CGOUT2
1A9
7_R[1:0] 8_R[1:0] 9_R[1:0] 0_R[1:0]
END_1_SEL_CGOUT1 END_1_SEL_CGOUT2 END_1_SEL_CGOUT3 END_1_SEL_CGOUT4
1AA
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
END_1_SEL_CGOUT5 END_1_SEL_CGOUT6 END_1_SEL_CGOUT7 END_1_SEL_CGOUT8
1AB
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
END_1_SEL_CGOUT9 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1
1AC
_L[1:0] 0_L[1:0] 1_L[1:0] 2_L[1:0]
END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1
1AD
3_L[1:0] 4_L[1:0] 5_L[1:0] 6_L[1:0]
END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT2
1AE
7_L[1:0] 8_L[1:0] 9_L[1:0] 0_L[1:0]
END_1_SEL_CGOUT1 END_1_SEL_CGOUT2 END_1_SEL_CGOUT3 END_1_SEL_CGOUT4
1AF
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
END_1_SEL_CGOUT5 END_1_SEL_CGOUT6 END_1_SEL_CGOUT7 END_1_SEL_CGOUT8
1B0
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
END_1_SEL_CGOUT9 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1
1B1
_R[1:0] 0_R[1:0] 1_R[1:0] 2_R[1:0]
END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1
1B2
3_R[1:0] 4_R[1:0] 5_R[1:0] 6_R[1:0]
END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT1 END_1_SEL_CGOUT2
1B3
7_R[1:0] 8_R[1:0] 9_R[1:0] 0_R[1:0]
END_2_SEL_CGOUT1 END_2_SEL_CGOUT2 END_2_SEL_CGOUT3 END_2_SEL_CGOUT4
1B4
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
END_2_SEL_CGOUT5 END_2_SEL_CGOUT6 END_2_SEL_CGOUT7 END_2_SEL_CGOUT8
1B5
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
END_2_SEL_CGOUT9 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1
1B6
_L[1:0] 0_L[1:0] 1_L[1:0] 2_L[1:0]
END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1
1B7
3_L[1:0] 4_L[1:0] 5_L[1:0] 6_L[1:0]
END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT2
1B8
7_L[1:0] 8_L[1:0] 9_L[1:0] 0_L[1:0]
END_2_SEL_CGOUT1 END_2_SEL_CGOUT2 END_2_SEL_CGOUT3 END_2_SEL_CGOUT4
1B9
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
1BA END_2_SEL_CGOUT5 END_2_SEL_CGOUT6 END_2_SEL_CGOUT7 END_2_SEL_CGOUT8
Himax Confidential -P.115-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
END_2_SEL_CGOUT9 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1
1BB
_R[1:0] 0_R[1:0] 1_R[1:0] 2_R[1:0]
END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1
1BC
3_R[1:0] 4_R[1:0] 5_R[1:0] 6_R[1:0]
END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT1 END_2_SEL_CGOUT2
1BD
7_R[1:0] 8_R[1:0] 9_R[1:0] 0_R[1:0]
GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT2 GAS_0_SEL_CGOUT3 GAS_0_SEL_CGOUT4
1BE
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
GAS_0_SEL_CGOUT5 GAS_0_SEL_CGOUT6 GAS_0_SEL_CGOUT7 GAS_0_SEL_CGOUT8
1BF
_L[1:0] _L[1:0] _L[1:0] _L[1:0]
GAS_0_SEL_CGOUT9 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1
1C0
_L[1:0] 0_L[1:0] 1_L[1:0] 2_L[1:0]
GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1
1C1
3_L[1:0] 4_L[1:0] 5_L[1:0] 6_L[1:0]
GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT2
1C2
7_L[1:0] 8_L[1:0] 9_L[1:0] 0_L[1:0]
GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT2 GAS_0_SEL_CGOUT3 GAS_0_SEL_CGOUT4
1C3
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
GAS_0_SEL_CGOUT5 GAS_0_SEL_CGOUT6 GAS_0_SEL_CGOUT7 GAS_0_SEL_CGOUT8
1C4
_R[1:0] _R[1:0] _R[1:0] _R[1:0]
GAS_0_SEL_CGOUT9 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1
1C5
_R[1:0] 0_R[1:0] 1_R[1:0] 2_R[1:0]
GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1
1C6
3_R[1:0] 4_R[1:0] 5_R[1:0] 6_R[1:0]
GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT1 GAS_0_SEL_CGOUT2
1C7
7_R[1:0] 8_R[1:0] 9_R[1:0] 0_R[1:0]
NVALID_D
200 - - - - - - DGC_EN
GC
201 R_GAMMA0[9:2]
202 R_GAMMA1[9:2]
203 R_GAMMA2[9:2]
204 R_GAMMA3[9:2]
205 R_GAMMA4[9:2]
206 R_GAMMA5[9:2]
207 R_GAMMA6[9:2]
208 R_GAMMA7[9:2]
209 R_GAMMA8[9:2]
20A R_GAMMA9[9:2]
20B R_GAMMA10[9:2]
20C R_GAMMA11[9:2]
20D R_GAMMA12[9:2]
20E R_GAMMA13[9:2]
20F R_GAMMA14[9:2]
210 R_GAMMA15[9:2]
211 R_GAMMA16[9:2]
212 R_GAMMA17[9:2]
213 R_GAMMA18[9:2]
214 R_GAMMA19[9:2]
215 R_GAMMA20[9:2]
216 R_GAMMA21[9:2]
217 R_GAMMA22[9:2]
218 R_GAMMA23[9:2]
219 R_GAMMA24[9:2]
21A R_GAMMA25[9:2]
21B R_GAMMA26[9:2]
21C R_GAMMA27[9:2]
21D R_GAMMA28[9:2]
21E R_GAMMA29[9:2]
Himax Confidential -P.116-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
21F R_GAMMA30[9:2]
220 R_GAMMA31[9:2]
221 R_GAMMA32[9:2]
222 R_GAMMA0[1:0] R_GAMMA1[1:0] R_GAMMA2[1:0] R_GAMMA3[1:0]
223 R_GAMMA4[1:0] R_GAMMA5[1:0] R_GAMMA6[1:0] R_GAMMA7[1:0]
224 R_GAMMA8[1:0] R_GAMMA9[1:0] R_GAMMA10[1:0] R_GAMMA11[1:0]
225 R_GAMMA12[1:0] R_GAMMA13[1:0] R_GAMMA14[1:0] R_GAMMA15[1:0]
226 R_GAMMA16[1:0] R_GAMMA17[1:0] R_GAMMA18[1:0] R_GAMMA19[1:0]
227 R_GAMMA20[1:0] R_GAMMA21[1:0] R_GAMMA22[1:0] R_GAMMA23[1:0]
228 R_GAMMA24[1:0] R_GAMMA25[1:0] R_GAMMA26[1:0] R_GAMMA27[1:0]
229 R_GAMMA28[1:0] R_GAMMA29[1:0] R_GAMMA30[1:0] R_GAMMA31[1:0]
22A R_GAMMA32[1:0] - - - - - -
22B G_GAMMA0[9:2]
22C G_GAMMA1[9:2]
22D G_GAMMA2[9:2]
22E G_GAMMA3[9:2]
22F G_GAMMA4[9:2]
230 G_GAMMA5[9:2]
231 G_GAMMA6[9:2]
232 G_GAMMA7[9:2]
233 G_GAMMA8[9:2]
234 G_GAMMA9[9:2]
235 G_GAMMA10[9:2]
236 G_GAMMA11[9:2]
237 G_GAMMA12[9:2]
238 G_GAMMA13[9:2]
239 G_GAMMA14[9:2]
23A G_GAMMA15[9:2]
23B G_GAMMA16[9:2]
23C G_GAMMA17[9:2]
23D G_GAMMA18[9:2]
23E G_GAMMA19[9:2]
23F G_GAMMA20[9:2]
240 G_GAMMA21[9:2]
241 G_GAMMA22[9:2]
242 G_GAMMA23[9:2]
243 G_GAMMA24[9:2]
244 G_GAMMA25[9:2]
245 G_GAMMA26[9:2]
246 G_GAMMA27[9:2]
247 G_GAMMA28[9:2]
248 G_GAMMA29[9:2]
249 G_GAMMA30[9:2]
24A G_GAMMA31[9:2]
24B G_GAMMA32[9:2]
24C G_GAMMA0[1:0] G_GAMMA1[1:0] G_GAMMA2[1:0] G_GAMMA3[1:0]
24D G_GAMMA4[1:0] G_GAMMA5[1:0] G_GAMMA6[1:0] G_GAMMA7[1:0]
24E G_GAMMA8[1:0] G_GAMMA9[1:0] G_GAMMA10[1:0] G_GAMMA11[1:0]
24F G_GAMMA12[1:0] G_GAMMA13[1:0] G_GAMMA14[1:0] G_GAMMA15[1:0]
250 G_GAMMA16[1:0] G_GAMMA17[1:0] G_GAMMA18[1:0] G_GAMMA19[1:0]
251 G_GAMMA20[1:0] G_GAMMA21[1:0] G_GAMMA22[1:0] G_GAMMA23[1:0]
252 G_GAMMA24[1:0] G_GAMMA25[1:0] G_GAMMA26[1:0] G_GAMMA27[1:0]
253 G_GAMMA28[1:0] G_GAMMA29[1:0] G_GAMMA30[1:0] G_GAMMA31[1:0]
254 G_GAMMA32[1:0] - - - - - -
255 B_GAMMA0[9:2]
256 B_GAMMA1[9:2]
257 B_GAMMA2[9:2]
258 B_GAMMA3[9:2]
259 B_GAMMA4[9:2]
Himax Confidential -P.117-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
25A B_GAMMA5[9:2]
25B B_GAMMA6[9:2]
25C B_GAMMA7[9:2]
25D B_GAMMA8[9:2]
25E B_GAMMA9[9:2]
25F B_GAMMA10[9:2]
260 B_GAMMA11[9:2]
261 B_GAMMA12[9:2]
262 B_GAMMA13[9:2]
263 B_GAMMA14[9:2]
264 B_GAMMA15[9:2]
265 B_GAMMA16[9:2]
266 B_GAMMA17[9:2]
267 B_GAMMA18[9:2]
268 B_GAMMA19[9:2]
269 B_GAMMA20[9:2]
26A B_GAMMA21[9:2]
26B B_GAMMA22[9:2]
26C B_GAMMA23[9:2]
26D B_GAMMA24[9:2]
26E B_GAMMA25[9:2]
26F B_GAMMA26[9:2]
270 B_GAMMA27[9:2]
271 B_GAMMA28[9:2]
272 B_GAMMA29[9:2]
273 B_GAMMA30[9:2]
274 B_GAMMA31[9:2]
275 B_GAMMA32[9:2]
276 B_GAMMA0[1:0] B_GAMMA1[1:0] B_GAMMA2[1:0] B_GAMMA3[1:0]
277 B_GAMMA4[1:0] B_GAMMA5[1:0] B_GAMMA6[1:0] B_GAMMA7[1:0]
278 B_GAMMA8[1:0] B_GAMMA9[1:0] B_GAMMA10[1:0] B_GAMMA11[1:0]
279 B_GAMMA12[1:0] B_GAMMA13[1:0] B_GAMMA14[1:0] B_GAMMA15[1:0]
27A B_GAMMA16[1:0] B_GAMMA17[1:0] B_GAMMA18[1:0] B_GAMMA19[1:0]
27B B_GAMMA20[1:0] B_GAMMA21[1:0] B_GAMMA22[1:0] B_GAMMA23[1:0]
27C B_GAMMA24[1:0] B_GAMMA25[1:0] B_GAMMA26[1:0] B_GAMMA27[1:0]
27D B_GAMMA28[1:0] B_GAMMA29[1:0] B_GAMMA30[1:0] B_GAMMA31[1:0]
27E B_GAMMA32[1:0] - - - - - -
NVALID_G
296 VHP_0[6:0]
AMMA
297 - VHP_1[6:0]
298 - VHP_2[6:0]
299 - VHP_3[6:0]
29A - VHP_4[6:0]
29B - VHP_5[6:0]
29C - VHP_6[6:0]
29D - VHP_7[6:0]
29E VMP_0[7:0]
29F VMP_1[7:0]
2A0 VMP_2[7:0]
2A1 VMP_3[7:0]
2A2 VMP_4[7:0]
2A3 VMP_5[7:0]
2A4 VMP_6[7:0]
2A5 VMP_7[7:0]
2A6 VMP_8[7:0]
2A7 VMP_9[7:0]
2A8 VMP_10[7:0]
2A9 VMP_11[7:0]
2AA VMP_12[7:0]
Himax Confidential -P.118-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
2AB - VLP_0[6:0]
2AC - VLP_1[6:0]
2AD - VLP_2[6:0]
2AE - VLP_3[6:0]
2AF - VLP_4[6:0]
2B0 - VLP_5[6:0]
2B1 - VLP_6[6:0]
2B2 - VLP_7[6:0]
2B3 - VHN_0[6:0]
2B4 - VHN_1[6:0]
2B5 - VHN_2[6:0]
2B6 - VHN_3[6:0]
2B7 - VHN_4[6:0]
2B8 - VHN_5[6:0]
2B9 - VHN_6[6:0]
2BA - VHN_7[6:0]
2BB VMN_0[7:0]
2BC VMN_1[7:0]
2BD VMN_2[7:0]
2BE VMN_3[7:0]
2BF VMN_4[7:0]
2C0 VMN_5[7:0]
2C1 VMN_6[7:0]
2C2 VMN_7[7:0]
2C3 VMN_8[7:0]
2C4 VMN_9[7:0]
2C5 VMN_10[7:0]
2C6 VMN_11[7:0]
2C7 VMN_12[7:0]
2C8 - VLN_0[6:0]
2C9 - VLN_1[6:0]
2CA - VLN_2[6:0]
2CB - VLN_3[6:0]
2CC - VLN_4[6:0]
2CD - VLN_5[6:0]
2CE - VLN_6[6:0]
2CF - VLN_7[6:0]
NVALID_O
2D0 - - - - - - -
FFSET3
2D1 VN_REFS[3:0] VP_REFS[3:0]
NVALID_S SCALING_ SCALING_
2D2 - - - - -
CL TYPE EN
300~3FF Customer use flexible OTP
Table 5.43: OTP table

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OTP Program Flow OTP_KEY0[7:0]

Description Note
OTP_KEY1[7:0]

OTP_KEY0[7:0] = 0xAAh
Enter OTP program mode
H/W Reset OTP_KEY1[7:0] = 0x55h
<Step1> +
SLPOUT
OTP_KEY0[7:0] = 0x00h
Delay 120ms Leave OTP program mode
OTP_KEY1[7:0] = 0x00h
Set 0xB9h=0xFFh, 0x83h, 0x98h to 1. If HX8398-A operate on OTP
<Step2>
access extension commands
program mode, then keep on OTP
program mode.
Other value Invalid
Write optimized OTP value in related 2. If HX8398-A operate on
<Step3> register
(need to programmed value) non-OTP program mode, then
keep on non-OTP program mode.

OTP_KEY0[7:0] = 0xAAh
<Step4>
OTP_KEY1[7:0] = 0x55h

<Step5> Set INTVPP_EN=1

<Step6> Set OTP index

<Step7> OTP_PROG=1

<Step8> Delay 10ms/byte

Yes
<Step9> Program another OTP index

<Step10> OTP_KEY0[7:0] = 0x00h

OTP_KEY1[7:0] = 0x00h

END

Figure 5.45: OTP programming sequence

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Step Operation
1 Power on, reset the module and SLPOUT.
2 Set 0xB9h = 0xFFh, 0x83h, 0x98h to access the extension commands.
3 Write optimized values to related registers.
4 Set OTP_KEY0[7:0]=0xAAh and OTP_KEY1[7:0]=0x55h to enter OTP program mode.
5 Set INTVPP_EN=1 for internal power mode.
6 Specify OTP_Index, please refer to the OTP table.
7 Set OTP_PROG=1, Internal register begin write to OTP according to OTP_index.
8 Wait 10 ms/byte for programming time (Note 1)
Complete programming one parameter to OTP. If continue to programming other parameter, return to
9
step (6). Otherwise, go to step (10)
10 Set OTP_KEY0[7:0]=0x00h and OTP_KEY1[7:0]=0x00h to leave OTP program mode.
Note1: When do the OTP programming process, it must be added 10ms/byte delay time after setting OTP_PROG=1.
Note2: If user want to program ID1~ID4, only need program OTP Index [Link] machine will program ID1~ID4 and
valid bit automatically.
Note3: If user want to program VCMC_F and VCMC_B, only need program OTP Index [Link] machine will program
VCMC_F and VCMC_B and valid bit automatically.

Table 5.44: OTP Programming sequence

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5.15.4 OTP Programming example of VCOM setting VCMC

O T P P r o g r a m F lo w

H /W R e s e t + S L P O U T

D e la y 1 2 0 m s

S e t e x te n s io n c o m m a n d s
S et C M D 0xB 9h
1 s t p a r a m e te r 0 x F F h
2 n d p a r a m e te r 0 x 8 3 h
3 r d p a r a m e te r 0 x 9 8 h

W r ite o p tim iz e d V C O M v a lu e o f R e g is te r
S et C M D 0xB 6h
1 s t~ 3 r d p a r a m e te r ( V C M C _ F [8 :0 ] a n d
V C M C _ B [8 :0 ])

S e t O T P _ K E Y 0 [7 :0 ] = 0 x A A h
O T P _ K E Y 1 [7 :0 ] = 0 x 5 5 h
S et C M D 0xB B h
6 th p a r a m e te r 0 x A A h
7 th p a r a m e te r 0 x 5 5 h

S e t IN T V P P _ E N = 1
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 0 h

S e t O T P in d e x 0 x 0 D h
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 0 h
2 n d p a r a m e te r 0 x 0 D h

S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 0 h
2 n d p a r a m e te r 0 x 0 D h
3 r d p a r a m e te r 0 x 0 0 h
4 th p a r a m e te r 0 x 0 1 h

D e la y 4 0 m s ( p r o g r a m V C M C _ F [8 :0 ],
V C M C _ B [8 :0 ] a n d v a lid b it to ta l 4 b y te s )

S e t O T P _ K E Y 0 [7 :0 ] = 0 x 0 0 h
O T P _ K E Y 1 [7 :0 ] = 0 x 0 0 h
S et C M D 0xB B h
6 th p a r a m e te r 0 x 0 0 h
7 th p a r a m e te r 0 x 0 0 h

END

Figure 5.46: OTP programming VCOM sequence

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O T P P r o g r a m F lo w

H /W R e s e t + S L P O U T

D e la y 1 2 0 m s

S e t e x te n s io n c o m m a n d s
S et C M D 0xB 9h
1 s t p a r a m e te r 0 x F F h
2 n d p a r a m e te r 0 x 8 3 h
3 r d p a r a m e te r 0 x 9 8 h

W r ite o p tim iz e d V C O M v a lu e o f R e g is te r
S et C M D 0xC 3h
1 s t~ 4 th p a r a m e te r ( ID 1 [7 :0 ] ~ ID 4 [7 :0 ])

S e t O T P _ K E Y 0 [7 :0 ] = 0 x A A h
O T P _ K E Y 1 [7 :0 ] = 0 x 5 5 h
S et C M D 0xB B h
6 th p a r a m e te r 0 x A A h
7 th p a r a m e te r 0 x 5 5 h

S e t IN T V P P _ E N = 1
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 0 h

S e t O T P in d e x 0 x 0 0 h
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 0 h
2 n d p a r a m e te r 0 x 0 0 h

S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 0 h
2 n d p a r a m e te r 0 x 0 0 h
3 r d p a r a m e te r 0 x 0 0 h
4 th p a r a m e te r 0 x 0 1 h

D e la y 5 0 m s ( p r o g r a m ID 1 [7 :0 ] ~ ID 4 [7 :0 ] a n d
v a lid b it to ta l 5 b y te s )

S e t O T P _ K E Y 0 [7 :0 ] = 0 x 0 0 h
O T P _ K E Y 1 [7 :0 ] = 0 x 0 0 h
S et C M D 0xB B h
6 th p a r a m e te r 0 x 0 0 h
7 th p a r a m e te r 0 x 0 0 h

END

Figure 5.47: OTP programming ID sequence

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O T P P r o g r a m F lo w

H /W R e s e t + S L P O U T

D e la y 1 2 0 m s

S e t e x t e n s io n c o m m a n d s
Set C M D 0xB 9h
1 s t p a ra m e te r 0 x F F h
2 n d p a ra m e te r 0 x 8 3 h
3 rd p a ra m e te r 0 x 9 8 h

W r it e R e g is t e r v a lu e o f A ll in it ia l s e t t in g

S e t O T P _ K E Y 0 [7 :0 ] = 0 x A A h
O T P _ K E Y 1 [7 :0 ] = 0 x 5 5 h
Set C M D 0xB B h
6 th p a ra m e te r 0 x A A h
7 th p a ra m e te r 0 x 5 5 h

S e t IN T V P P _ E N = 1
Set C M D 0xB B h
1 s t p a ra m e te r 0 x 8 0 h

Set O TP_PR O G _A LL=1

Set C M D 0xB B h
1 s t p a ra m e te r 0 x A 0 h

S e t O T P _ P R O G = 1 f o r p r o g r a m m in g a c t io n
Set C M D 0xB B h
1 s t p a ra m e te r 0 x A 0 h
2 n d p a ra m e te r 0 x 0 0 h
3 rd p a ra m e te r 0 x 0 0 h
4 th p a ra m e te r 0 x 0 1 h

D e la y 2 5 0 0 m s

S e t O T P _ K E Y 0 [7 :0 ] = 0 x 0 0 h
O T P _ K E Y 1 [7 :0 ] = 0 x 0 0 h
Set C M D 0xB B h
6 th p a ra m e te r 0 x 0 0 h
7 th p a ra m e te r 0 x 0 0 h

END

Figure 5.48: OTP programming all Index sequence

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O T P P r o g r a m F lo w
N o t e 1 : O T P I n d e x r a n g e is 3 0 0 ~ 3 F F h .
N o t e 2 : k k h = la s t O T P I n d e x h a d b e p r o g r a m m e d + 1 .
N o t e 3 : R e g is t e r P a r a m e t e r c a n a s s ig n a n y P a r a m e t e r o f
R e g is t e r I n d e x . B it [ 7 : 6 ] = 0 0 m e a n s B a n k 0 ; B it [ 7 : 6 ] = 0 1
H /W R e s e t + S L P O U T m e a n s B a n k 1 ; B it [ 7 : 6 ] = 1 0 m e a n s B a n k 2 . B it [ 5 : 0 ]
m e a n s P a ra m e te r n u m b e r .
D e la y 1 2 0 m s F o r e x a m p le : I f w a n t t o p r o g r a m R C 1 h B a n k 1 P a r a m e t e r 3 . I n t h e
f lo w c h a r t R e g is t e r I n d e x = C 1 h , R e g is t e r P a r a m e t e r = 4 3 h .
S e t e x t e n s io n c o m m a n d s
S et C M D 0xB 9h
1 s t p a ra m e te r 0 x F F h
2 n d p a ra m e te r 0 x 8 3 h
3 rd p a ra m e te r 0 x 9 8 h

O T P p r o g r a m m in g a c t io n d o n e
S et C M D 0xB B h
1 s t p a ra m e te r 0 x 8 3 h
S e t O T P _ K E Y 0 [7 :0 ] = 0 x A A h 2 n d p a ra m e te r (0 x k k + 1 )h
O T P _ K E Y 1 [7 :0 ] = 0 x 5 5 h 3 r d p a r a m e t e r ( R e g is t e r P a r a m e t e r )
S et C M D 0xB B h 4 th p a ra m e te r 0 x 0 0 h
6 th p a ra m e te r 0 x A A h
7 th p a ra m e te r 0 x 5 5 h

S e t O T P in d e x
S et C M D 0xB B h
S e t IN T V P P _ E N = 1
1 s t p a ra m e te r 0 x 8 3 h
S et C M D 0xB B h
2 n d p a ra m e te r (0 x k k + 2 )h
1 s t p a ra m e te r 0 x 8 0 h

S e t O T P V a lu e
S e t O T P in d e x S et C M D 0xB B h
S et C M D 0xB B h 1 s t p a ra m e te r 0 x 8 3 h
1 s t p a ra m e te r 0 x 8 3 h 2 n d p a ra m e te r (0 x k k + 2 )h
2 n d p a ra m e te r 0 x k k h 3 r d p a r a m e t e r ( R e g is t e r V a lu e )

S e t O T P R e g is t e r I n d e x S e t O T P _ P R O G = 1 f o r p r o g r a m m in g a c t io n
S et C M D 0xB B h S et C M D 0xB B h
1 s t p a ra m e te r 0 x 8 3 h 1 s t p a ra m e te r 0 x 8 3 h
2 n d p a ra m e te r 0 x k k h 2 n d p a ra m e te r (0 x k k + 2 )h
3 r d p a r a m e t e r ( R e g is t e r I n d e x ) ( N o t e 2 ) 3 r d p a r a m e t e r ( R e g is t e r V a lu e )
4 th p a ra m e te r 0 x 0 1 h

S e t O T P _ P R O G = 1 f o r p r o g r a m m in g a c t io n
S et C M D 0xB B h
1 s t p a ra m e te r 0 x 8 3 h D e la y 1 0 m s
2 n d p a ra m e te r 0 x k k h
3 r d p a r a m e t e r ( R e g is t e r I n d e x )
4 th p a ra m e te r 0 x 0 1 h

O T P p r o g r a m m in g a c t io n d o n e
S et C M D 0xB B h
1 s t p a ra m e te r 0 x 8 3 h
D e la y 1 0 m s
2 n d p a ra m e te r (0 x k k + 2 )h
3 r d p a r a m e t e r ( R e g is t e r V a lu e )
4 th p a ra m e te r 0 x 0 0 h

O T P p r o g r a m m in g a c t io n d o n e
S et C M D 0xB B h
1 s t p a ra m e te r 0 x 8 3 h
2 n d p a ra m e te r 0 x k k h O T P _ K E Y 0 [7 :0 ] = 0 x 0 0 h
3 r d p a r a m e t e r ( R e g is t e r I n d e x ) O T P _ K E Y 1 [7 :0 ] = 0 x 0 0 h
4 th p a ra m e te r 0 x 0 0 h S et C M D 0xB B h
6 th p a ra m e te r 0 x 0 0 h
7 th p a ra m e te r 0 x 0 0 h

S e t O T P in d e x
1 s t p a ra m e te r 0 x 8 3 h
2 n d p a ra m e te r (0 x k k + 1 )h
R e s e t I C o r S L P O U T f o r O T P r e la o d

S e t O T P R e g is t e r P a r a m e t e r
S et C M D 0xB B h END
1 s t p a ra m e te r 0 x 8 3 h
2 n d p a ra m e te r (0 x k k + 1 )h
3 r d p a r a m e t e r ( R e g is t e r P a r a m e t e r ) ( N o t e 3 )

S e t O T P _ P R O G = 1 f o r p r o g r a m m in g a c t io n
S et C M D 0xB B h
1 s t p a ra m e te r 0 x 8 3 h
2 n d p a ra m e te r (0 x k k + 1 )h
3 r d p a r a m e t e r ( R e g is t e r P a r a m e t e r )
4 th p a ra m e te r 0 x 0 1 h

D e la y 1 0 m s

Figure 5.49: Flexible OTP programming sequence

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O T P P r o g r a m F lo w

H /W R e s e t + S L P O U T

D e la y 1 2 0 m s

S e t e x te n s io n c o m m a n d s
S et C M D 0xB 9h
1 s t p a r a m e te r 0 x F F h
2 n d p a r a m e te r 0 x 8 3 h
3 r d p a r a m e te r 0 x 9 8 h N o te 1 : O T P In d e x r a n g e is 3 0 0 ~ 3 F F h .
N o te 2 : k k h a n d jjh = la s t O T P In d e x h a d b e p r o g r a m m e d + 1 .
N o te 3 : B it[7 :6 ]= 1 1 fo r c o n tin u o u s O T P . n is th e n u m b e r o f n e e d to p r o g r a m fr o m P A 1 .
S e t O T P _ K E Y 0 [7 :0 ] = 0 x A A h
O T P _ K E Y 1 [7 :0 ] = 0 x 5 5 h N o te 4 : If u s e r h a d n e v e r u s e c o n tin u o u s O T P flo w , th e B a n k is k e e p in B a n k 0 . S o fir s t tim e
S et C M D 0xB B h u s e c o n tin u o u s O T P flo w to p r o g r a m B a n k 0 , th e P r o g r a m B a n k flo w is n o t n e e d .
6 th p a r a m e te r 0 x A A h
7 th p a r a m e te r 0 x 5 5 h F o r e x a m p le : If w a n t to p r o g r a m R C 1 h B a n k 2 P A 1 ~ P A 8 . In th e flo w c h a r t fir s t s te p is
p r o g r a m R B D h P A 1 to 0 x 0 2 , th a n p r o g r a m R C 1 h P A 1 ~ P A 8 .

S e t IN T V P P _ E N = 1
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 0 h

T h e B a n k n u m b e r is th e Yes
s a m e a s la s t c o n tin u e d
p ro g ra m m e d B a n k
n u m b e r o r n o t?

NO
P r o g r a m B a n k flo w

S e t O T P in d e x S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n S e t O T P in d e x O T P p r o g r a m m in g a c tio n d o n e
S et C M D 0xB B h S et C M D 0xB B h S et C M D 0xB B h S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 3 h 1 s t p a r a m e te r 0 x 8 3 h 1 s t p a r a m e te r 0 x 8 3 h 1 s t p a r a m e te r 0 x 8 3 h
2 n d p a r a m e te r 0 x k k h 2 n d p a r a m e te r ( 0 x k k + 1 )h 2 n d p a r a m e te r (0 x k k + 3 ) h o r 0 x jjh 2 n d p a r a m e te r (0 x k k + 4 ) h o r (0 x jj+ 1 ) h
3 r d p a r a m e te r 0 x 0 1 h 3 rd (0 x C 0 + n )h
4 th p a r a m e te r 0 x 0 1 h 4 th p a r a m e te r 0 x 0 0 h

S et O TP 0xB D h S e t O T P R e g is te r In d e x i= 1
S et C M D 0xB B h S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 3 h 1 s t p a r a m e te r 0 x 8 3 h S e t O T P in d e x
i= i+ 1
2 n d p a r a m e te r 0 x k k h D e la y 1 0 m s 2 n d p a r a m e te r (0 x k k + 3 ) h o r 0 x jjh S et C M D 0xB B h
3 r d p a r a m e te r 0 x B D h 3 r d ( R e g is te r In d e x ) 1 s t p a r a m e te r 0 x 8 3 h
2 n d p a r a m e te r ( 0 x k k + 4 + i) h o r (0 x jj+ 1 + i)h

O T P p r o g r a m m in g a c tio n d o n e
S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n
S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n S et C M D 0xB B h
S et C M D 0xB B h S e t O T P V a lu e
S et C M D 0xB B h 1 s t p a r a m e te r 0 x 8 3 h
1 s t p a r a m e te r 0 x 8 3 h S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 3 h 2 n d p a r a m e te r ( 0 x k k + 1 )h
2 n d p a r a m e te r (0 x k k + 3 ) h o r 0 x jjh 1 s t p a r a m e te r 0 x 8 3 h
2 n d p a r a m e te r 0 x k k h 3 r d p a r a m e te r 0 x 0 1 h
3 r d ( R e g is te r In d e x ) 2 n d p a r a m e te r ( 0 x k k + 4 + i) h o r (0 x jj+ 1 + i)h
3 r d p a r a m e te r 0 x B D h 4 th p a r a m e te r 0 x 0 0 h
4 th p a r a m e te r 0 x 0 1 h 3 r d p a r a m e te r (R e g is te r V a lu e )
4 th p a r a m e te r 0 x 0 1 h

S e t O T P in d e x
D e la y 1 0 m s S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n
S et C M D 0xB B h
S et C M D 0xB B h
D e la y 1 0 m s 1 s t p a r a m e te r 0 x 8 3 h
1 s t p a r a m e te r 0 x 8 3 h
2 n d p a r a m e te r (0 x k k + 2 )h
2 n d p a r a m e te r ( 0 x k k + 4 + i) h o r (0 x jj+ 1 + i)h
3 r d p a r a m e te r (R e g is te r V a lu e )
O T P p r o g r a m m in g a c tio n d o n e
4 th p a r a m e te r 0 x 0 1 h
S et C M D 0xB B h
O T P p r o g r a m m in g a c tio n d o n e Set O TP Bank num ber 1 s t p a r a m e te r 0 x 8 3 h
S et C M D 0xB B h S et C M D 0xB B h 2 n d p a r a m e te r (0 x k k + 3 ) h o r 0 x jjh
1 s t p a r a m e te r 0 x 8 3 h 1 s t p a r a m e te r 0 x 8 3 h 3 r d ( R e g is te r In d e x )
2 n d p a r a m e te r 0 x k k h 2 n d p a r a m e te r (0 x k k + 2 )h 4 th p a r a m e te r 0 x 0 0 h D e la y 1 0 m s
3 r d p a r a m e te r 0 x B D h 3 r d p a r a m e te r ( B a n k n u m b e r )
4 th p a r a m e te r 0 x 0 1 h 0 x 0 0 h

S e t O T P in d e x
O T P p r o g r a m m in g a c tio n d o n e
S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n S et C M D 0xB B h
S et C M D 0xB B h
S et C M D 0xB B h 1 s t p a r a m e te r 0 x 8 3 h
S e t O T P in d e x 1 s t p a r a m e te r 0 x 8 3 h
1 s t p a r a m e te r 0 x 8 3 h 2 n d p a r a m e te r (0 x k k + 4 ) h o r ( 0 x jj+ 1 )h
S et C M D 0xB B h 2 n d p a r a m e te r ( 0 x k k + 4 + i) h o r (0 x jj+ 1 + i)h
2 n d p a r a m e te r (0 x k k + 2 )h
1 s t p a r a m e te r 0 x 8 3 h 3 r d p a r a m e te r (R e g is te r V a lu e )
3 r d p a r a m e te r ( B a n k n u m b e r )
2 n d p a r a m e te r (0 x k k + 1 ) h 4 th p a r a m e te r 0 x 0 0 h
4 th p a r a m e te r 0 x 0 1 h
S e t n u m b e rs o f O T P
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 3 h No
D e la y 1 0 m s 2 n d p a r a m e te r (0 x k k + 4 ) h o r ( 0 x jj+ 1 )h
Set O TP R BD h PA 1 i= n
3 r d ( 0 x C 0 + n ) h ( N o te 3 )
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 3 h
2 n d p a r a m e te r (0 x k k + 1 ) h Yes
3 r d p a r a m e te r 0 x 0 1 h
O T P p r o g r a m m in g a c tio n d o n e
S e t O T P _ P R O G = 1 fo r p r o g r a m m in g a c tio n
S et C M D 0xB B h O T P _ K E Y 0 [7 :0 ] = 0 x 0 0 h
S et C M D 0xB B h
1 s t p a r a m e te r 0 x 8 3 h O T P _ K E Y 1 [7 :0 ] = 0 x 0 0 h
1 s t p a r a m e te r 0 x 8 3 h
2 n d p a r a m e te r ( 0 x k k + 2 )h S et C M D 0xB B h
2 n d p a r a m e te r (0 x k k + 4 ) h o r ( 0 x jj+ 1 )h
3 r d p a r a m e te r (B a n k n u m b e r ) 6 th p a r a m e te r 0 x 0 0 h
3 rd (0 x C 0 + n )h
4 th p a r a m e te r 0 x 0 0 h 7 th p a r a m e te r 0 x 0 0 h
4 th p a r a m e te r 0 x 0 1 h

D e la y 1 0 m s
R e s e t IC o r S L P O U T fo r O T P r e la o d

END

Figure 5.50: Flexible OTP continuous programming sequence

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OTP Read Flow

H/W Reset + SLPOUT

Clear OTP_POR
Set CMD 0xBBh
Delay 120 ms 1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x00h
4th parameter 0x00h
Set extension commands
Set CMD 0xB9h
1st parameter 0xFFh
2nd parameter 0x83h Read OTP_DATA from BBh
3rd parameter 0x98h Read CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
Set OTP_KEY0[7:0] = 0xAAh 3rd parameter 0x00h
OTP_KEY1[7:0] = 0x55h 4th parameter 0x00h
Set CMD 0xBBh 5th parameter 0x##h (OTP data)
6th parameter 0xAAh
7th parameter0x55h

Set OTP_INDEX(0x00) for ID1 setting Read OTP_DATA YES

Set CMD 0xBBh Comparing the related register
1st parameter 0x00h If 0x##=0xFF
2nd parameter 0x00h

Set OTP_POR
Set CMD 0xBBh OTP Programmed OTP not Program
1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x00h
4th parameter 0x80h

Figure 5.51: OTP read sequence flow of Index 00h

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6. Command
6.1 Command list

6.1.1 Standard command

Default
(Hex) Operation code DCX D7 D6 D5 D4 D3 D2 D1 D0 Function
(Hex)
00 NOP 0 0 0 0 0 0 0 0 0 No Operation -
01 SWRESET 0 0 0 0 0 0 0 0 1 Software Reset -
0 0 0 0 0 0 1 0 0 -
1 ID1[7:0] Read Display Identification 83h
04 RDDIDIF
1 ID2[7:0] Information 98h
1 ID3[7:0] 0Ah
0 0 0 0 0 0 1 0 1 Read Number of DSI -
05 RDNUMPE
1 P[7:0] Parity Error -
0 0 0 0 0 0 1 1 0 -
06 RDRED Read Red Colour
1 R7 R6 R5 R4 R3 R2 R1 R0 -
0 0 0 0 0 0 1 1 1 -
07 RDGREEN Read Green Colour
1 G7 G6 G5 G4 G3 G2 G1 G0 -
0 0 0 0 0 1 0 0 0 -
08 RDBLUE Read Blue Colour
1 B7 B6 B5 B4 B3 B2 B1 B0 -
0 0 0 0 0 1 0 0 1 -
1 D31 D30 D29 0 0 D26 D25 D24 00h
09 RDDST 1 D23 D22 D21 D20 D19 0 D17 D16 Read display status 71h
1 0 0 D13 D12 D11 D10 D9 D8 00h
1 D7 D6 D5 D4 D3 D2 D1 D0 00h
0 0 0 0 0 1 0 1 0 -
0A RDDPM Read display power mode
1 D7 D6 0 D4 D3 D2 0 0 08h
0 0 0 0 0 1 0 1 1 -
0B RDDMADCTL Read display MADCTL
1 D7 D6 0 0 D3 D2 D1 D0 00h
0 0 0 0 0 1 1 0 0 -
0C RDDCOLMOD Read display pixel format
1 0 D6 D5 D4 0 0 0 0 70h
0 0 0 0 0 1 1 0 1 -
0D RDDIM Read display image mode
1 0 0 D5 D4 D3 D2 D1 D0 00h
0 0 0 0 0 1 1 1 0 -
0E RDDSM Read display signal mode
1 D7 D6 D5 D4 D3 D2 0 D0 00h
0 0 0 0 0 1 1 1 1 Read display -
0F RDDSDR
1 D7 D6 D5 D4 0 0 0 0 self-diagnostic result 00h
10 SLPIN 0 0 0 0 1 0 0 0 0 Sleep In -
11 SLPOUT 0 0 0 0 1 0 0 0 1 Sleep Out -
13 NORON 0 0 0 0 1 0 0 1 1 Normal display mode on -
20 INVOFF 0 0 0 1 0 0 0 0 0 Display inversion off -
21 INVON 0 0 0 1 0 0 0 0 1 Display inversion on -
22 ALLPOFF 0 0 0 1 0 0 0 1 0 All pixel off (black) -
23 ALLPON 0 0 0 1 0 0 0 1 1 All pixel on (white) -
0 0 0 1 0 0 1 1 0 -
26 GAMSET Gamma set
1 GC[7:0] 01h
28 DISPOFF 0 0 0 1 0 1 0 0 0 Display off -
29 DISPON 0 0 0 1 0 1 0 0 1 Display on -
2C RAMWR 0 0 0 1 0 1 1 0 0 Write_memory_start
34 TEOFF 0 0 0 1 1 0 1 0 0 Tearing Effect Line OFF -
0 0 0 1 1 0 1 0 1 -
35 TEON Tearing Effect Line ON
1 X X X X X X X M 00h
0 0 0 1 1 0 1 1 0 -
36 MADCTL Memory access Control
1 D7 D6 X X D3 D2 D1 D0 00h
38 IDMOFF 0 0 0 1 1 1 0 0 0 Idle mode off -
39 IDMON 0 0 0 1 1 1 0 0 1 Idle mode on -
0 0 0 1 1 1 0 1 0 - -
3A COLMOD
1 X D6 D5 D4 X X X X - 70h
3C RAMWR 0 0 0 1 1 1 1 0 0 Write_memory_continuously

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Default
(Hex) Operation Code DCX D7 D6 D5 D4 D3 D2 D1 D0 Function
(Hex)
0 0 1 0 0 0 1 0 0 -
Tearing Effect Scan Line
44 TESL 1 TELINE[15:8] 00h
number
1 TELINE[7:0] 00h
0 0 1 0 0 0 1 0 1 -
Reture the current
45 GETSCAN 1 SLN[15:8] 00h
scanline SLN[15:0]
1 SLN[7:0] 00h
0 0 1 0 1 0 0 0 1 -
51 WRDISBV Write Display Brightness
1 DBV[7:0] 00h
0 0 1 0 1 0 0 1 0 Read Display Brightness -
52 RDDISBV
1 DBV[7:0] Value 00h
0 0 1 0 1 0 0 1 1 -
53 WRCTRLD BCT Write CTRL Display
1 X X X DD BL X X 00h
RL
0 0 1 0 1 0 1 0 0 -
Read Control Value
54 RDCTRLD BCT
1 0 0 0 DD BL 0 0 Display 00h
RL
0 0 1 0 1 0 1 0 1 Write Adaptive Brightness -
55 WRCABC
1 X X X X X X CABC[1:0] Control 00h
0 0 1 0 1 0 1 1 0 Read Adaptive Brightness -
56 RDCABC
1 0 0 0 0 0 0 C1 C0 Control Content 00h
0 0 1 0 1 1 1 1 0 Write CABC minimum -
5E WRCABCMB
1 CMB[7:0] brightness 00h
0 0 1 0 1 1 1 1 1 Read CABC minimum -
5F RDCABCMB
1 CMB[7:0] brightness 00h
0 0 1 1 0 1 0 0 0 Read Automatic -
68 RDABCSDR Brightness Control
1 D[7:6] 0 0 0 0 0 0 00h
Self-Diagnostic Result
0 1 0 0 0 0 0 0 0 -
80 WRIMCOL Write Idle Mode Color
1 X X X X X R G B 07
0 1 0 0 0 0 0 0 1 -
81 RDIMCOL Read Idle Mode Color
1 0 0 0 0 0 R G B 07
0 1 0 1 0 0 0 0 1 -
1 xx xx xx xx xx xx xx xx Read the DDB from the -
A1 Read_DDB_start
1 xx xx xx xx xx xx xx xx provided location. -
1 xx xx xx xx xx xx xx xx -
0 1 0 1 0 1 0 0 0 -
1 xx xx xx xx xx xx xx xx Continue reading the DDB -
A8 Read_DDB_continue
1 xx xx xx xx xx xx xx xx from the last read location. -
1 xx xx xx xx xx xx xx xx -
0 1 1 0 1 1 0 1 0 Read ID1 -
DA RDID1
1 ID1[7:0] 83h
0 1 1 0 1 1 0 1 1 Read ID2 -
DB RDID2
1 ID2[7:0] 98h
0 1 1 0 1 1 1 0 0 Read ID3 -
DC RDID3
1 ID3[7:0] 0Ah
Note: (1) Undefined commands are treated as NOP (00h) command.

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Operation Code DCX D7 D6 D5 D4 D3 D2 D1 D0 Default Function

(Hex)
0 1 0 1 1 0 1 0 0 -
1 GEN_ON[7:0] 00h
1 GEN_OFF[7:0] FFh
1 SPON[7:0] 03h
1 SPOFF[7:0] 38h
1 CON[7:0] 0Ah
1 COFF[7:0] 6Ch
1 CON1[7:0] 05h
1 COFF1[7:0] 36h
1 EQON1[7:0] 05h
1 SON[7:0] 10h
1 SOFF[7:0] 75h
1 SAP1_P[3:0] SAP1_N[3:0] 22h
B4 SETCYC 1 - - - - - SAP2[2:0] 03h Set Cycle
1 DX2OFF[7:0] 3Ah
1 SPON_MPU[7:0] 03h
1 SPOFF_MPU[7:0] 38h
1 CON_MPU[7:0] 0Ah
1 COFF_MPU[7:0] 6Ch
1 CON1_MPU[7:0] 05h
1 COFF1_MPU[7:0] 36h
1 EQON1_MPU[7:0] 05h
1 SON_MPU[7:0] 10h
1 SOFF_MPU[7:0] 75h
1 DX2OFF_MPU[7:0] 3Ah
DX2_E
1 - - - - - - - 00h
N
0 1 0 1 1 0 1 1 0 -
1 VCMC_F[7:0] 34h
Set VCOM
B6 SETVCOM 1 VCMC_B[7:0] 34h
Voltage
VCMC_ VCMC_
1 VCOM_TIMES[2:0] - - - E3h
B8 F8
0 1 0 1 1 0 1 1 1 -
Set TE
B7 SETTE 1 TEI[3:0] - TEP[10:8] 00h
function
1 TEP[7:0] 00h
Set
0 1 0 1 1 1 0 0 0 - Temperature
Sensor
TSENS EXT_T
1 - LT_EN HT_EN TEMP_GAP[2:0] 01h
OR_EN PS_EN
L_VGL
1 - - L_TEMP[4:0] -
S2[4]
1 L_SAP1_P[3:0] L_SAP1_N[3:0] -
1 L_VGLS2[3:0] L_VGLS[9:8] L_VGHS[9:8] -
1 L_VGHS[7:0] -
1 L_VGLS[7:0] -
1 L_COFF[7:0] -
1 L_COFF1[7:0] -
1 L_SOFF[7:0] -
B8 SETSENSOR Bank0
1 - - - L_VCOM[4:0] -
H_VGL
1 - - H_TEMP[4:0] -
S2[4]
1 H_SAP1_P[3:0] H_SAP1_N[3:0] -
1 H_VGLS2[3:0] H_VGLS[9:8] H_VGHS[9:8] -
1 H_VGHS[7:0] -
1 H_VGLS[7:0] -
1 H_COFF[7:0] -
1 H_COFF1[7:0] -
1 H_SOFF[7:0] -
1 - - - H_VCOM[4:0] -
REG_A
1 - - DCOUT REG_ADCOUT[4:0] 00h Bank1
_EN
0 1 0 1 1 1 0 0 1 -
1 EXTC1[7:0] 00h Set extended
B9 SETEXTC
1 EXTC2[7:0] 00h command
1 EXTC3[7:0] 00h

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Operation Code DCX D7 D6 D5 D4 D3 D2 D1 D0 Default Function

(Hex)
0 1 0 1 1 1 0 1 0 -
Set MIPI
BA SETRMIPI 1 - DSISETUP0[6:0] 63h
Control
1 DSISETUP1[7:0] 03h
0 1 0 1 1 1 0 1 1 -
OTP_P
INTVPP
1 - ROG_A - - - OTP_INDEX[9:8] 00h
_EN
LL
1 OTP_INDEX[7:0] 00h
1 OTP_DATA[7:0] 00h
BB SETOTP Set OTP
OTP_P
OTP_P OTP_P OTP_T OTP_P
1 WR_SE OTP_PTM[2:0] 00h
OR WE EST ROG
L
1 OTP_DATA_READ[7:0] 00h
1 OTP_KEY0[7:0] 00h
1 OTP_KEY1[7:0] 00h
0 1 0 1 1 1 1 0 1 -
Set Register
BD SETBANK BANK_INDEX[1:
1 - - - - - - 00h Bank
0]
0 1 1 0 0 0 0 0 1 - Set DGC
DGC_E
1 - - - - - - - 00h
N
1 R_GAMMA0[9:2] -
1 R_GAMMA1[9:2] -
1 R_GAMMA2[9:2] -
1 R_GAMMA3[9:2] -
1 R_GAMMA4[9:2] -
1 R_GAMMA5[9:2] -
1 R_GAMMA6[9:2] -
1 R_GAMMA7[9:2] -
1 R_GAMMA8[9:2] -
1 R_GAMMA9[9:2] -
1 R_GAMMA10[9:2] -
1 R_GAMMA11[9:2] -
1 R_GAMMA12[9:2] -
1 R_GAMMA13[9:2] -
1 R_GAMMA14[9:2] -
1 R_GAMMA15[9:2] -
1 R_GAMMA16[9:2] -
1 R_GAMMA17[9:2] -
1 R_GAMMA18[9:2] -
1 R_GAMMA19[9:2] -
Bank0
1 R_GAMMA20[9:2] -
1 R_GAMMA21[9:2] -
1 R_GAMMA22[9:2] -
C1 SETDGC
1 R_GAMMA23[9:2] -
1 R_GAMMA24[9:2] -
1 R_GAMMA25[9:2] -
1 R_GAMMA26[9:2] -
1 R_GAMMA27[9:2] -
1 R_GAMMA28[9:2] -
1 R_GAMMA29[9:2] -
1 R_GAMMA30[9:2] -
1 R_GAMMA31[9:2] -
1 R_GAMMA32[9:2] -
1 R_GAMMA0[1:0] R_GAMMA1[1:0] R_GAMMA2[1:0] R_GAMMA3[1:0] -
1 R_GAMMA4[1:0] R_GAMMA5[1:0] R_GAMMA6[1:0] R_GAMMA7[1:0] -
1 R_GAMMA8[1:0] R_GAMMA9[1:0] R_GAMMA10[1:0] R_GAMMA11[1:0] -
1 R_GAMMA12[1:0] R_GAMMA13[1:0] R_GAMMA14[1:0] R_GAMMA15[1:0] -
1 R_GAMMA16[1:0] R_GAMMA17[1:0] R_GAMMA18[1:0] R_GAMMA19[1:0] -
1 R_GAMMA20[1:0] R_GAMMA21[1:0] R_GAMMA22[1:0] R_GAMMA23[1:0] -
1 R_GAMMA24[1:0] R_GAMMA25[1:0] R_GAMMA26[1:0] R_GAMMA27[1:0] -
1 R_GAMMA28[1:0] R_GAMMA29[1:0] R_GAMMA30[1:0] R_GAMMA31[1:0] -
1 R_GAMMA32[1:0] - - - - - - -
1 G_GAMMA0[9:2] -
1 G_GAMMA1[9:2] -
1 G_GAMMA2[9:2] -
1 G_GAMMA3[9:2] - Bank1
1 G_GAMMA4[9:2] -
1 G_GAMMA5[9:2] -
1 G_GAMMA6[9:2] -
Himax Confidential -P.132-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
1 G_GAMMA7[9:2] -
1 G_GAMMA8[9:2] -
1 G_GAMMA9[9:2] -
1 G_GAMMA10[9:2] -
1 G_GAMMA11[9:2] -
1 G_GAMMA12[9:2] -
1 G_GAMMA13[9:2] -
1 G_GAMMA14[9:2] -
1 G_GAMMA15[9:2] -
1 G_GAMMA16[9:2] -
1 G_GAMMA17[9:2] -
1 G_GAMMA18[9:2] -
1 G_GAMMA19[9:2] -
1 G_GAMMA20[9:2] -
1 G_GAMMA21[9:2] -
1 G_GAMMA22[9:2] -
1 G_GAMMA23[9:2] -
1 G_GAMMA24[9:2] -
1 G_GAMMA25[9:2] -
1 G_GAMMA26[9:2] -
1 G_GAMMA27[9:2] -
1 G_GAMMA28[9:2] -
1 G_GAMMA29[9:2] -
1 G_GAMMA30[9:2] -
1 G_GAMMA31[9:2] -
1 G_GAMMA32[9:2] -
1 G_GAMMA0[1:0] G_GAMMA1[1:0] G_GAMMA2[1:0] G_GAMMA3[1:0] -
1 G_GAMMA4[1:0] G_GAMMA5[1:0] G_GAMMA6[1:0] G_GAMMA7[1:0] -
1 G_GAMMA8[1:0] G_GAMMA9[1:0] G_GAMMA10[1:0] G_GAMMA11[1:0] -
1 G_GAMMA12[1:0] G_GAMMA13[1:0] G_GAMMA14[1:0] G_GAMMA15[1:0] -
1 G_GAMMA16[1:0] G_GAMMA17[1:0] G_GAMMA18[1:0] G_GAMMA19[1:0] -
1 G_GAMMA20[1:0] G_GAMMA21[1:0] G_GAMMA22[1:0] G_GAMMA23[1:0] -
1 G_GAMMA24[1:0] G_GAMMA25[1:0] G_GAMMA26[1:0] G_GAMMA27[1:0] -
1 G_GAMMA28[1:0] G_GAMMA29[1:0] G_GAMMA30[1:0] G_GAMMA31[1:0] -
1 G_GAMMA32[1:0] - - - - - - -
1 B_GAMMA0[9:2] -
1 B_GAMMA1[9:2] -
1 B_GAMMA2[9:2] -
1 B_GAMMA3[9:2] -
1 B_GAMMA4[9:2] -
1 B_GAMMA5[9:2] -
1 B_GAMMA6[9:2] -
1 B_GAMMA7[9:2] -
1 B_GAMMA8[9:2] -
1 B_GAMMA9[9:2] -
1 B_GAMMA10[9:2] -
1 B_GAMMA11[9:2] -
1 B_GAMMA12[9:2] -
1 B_GAMMA13[9:2] -
1 B_GAMMA14[9:2] -
1 B_GAMMA15[9:2] -
1 B_GAMMA16[9:2] -
1 B_GAMMA17[9:2] -
1 B_GAMMA18[9:2] -
Bank2
1 B_GAMMA19[9:2] -
1 B_GAMMA20[9:2] -
1 B_GAMMA21[9:2] -
1 B_GAMMA22[9:2] -
1 B_GAMMA23[9:2] -
1 B_GAMMA24[9:2] -
1 B_GAMMA25[9:2] -
1 B_GAMMA26[9:2] -
1 B_GAMMA27[9:2] -
1 B_GAMMA28[9:2] -
1 B_GAMMA29[9:2] -
1 B_GAMMA30[9:2] -
1 B_GAMMA31[9:2] -
1 B_GAMMA32[9:2] -
1 B_GAMMA0[1:0] B_GAMMA1[1:0] B_GAMMA2[1:0] B_GAMMA3[1:0] -
1 B_GAMMA4[1:0] B_GAMMA5[1:0] B_GAMMA6[1:0] B_GAMMA7[1:0] -
1 B_GAMMA8[1:0] B_GAMMA9[1:0] B_GAMMA10[1:0] B_GAMMA11[1:0] -
1 B_GAMMA12[1:0] B_GAMMA13[1:0] B_GAMMA14[1:0] B_GAMMA15[1:0] -
1 B_GAMMA16[1:0] B_GAMMA17[1:0] B_GAMMA18[1:0] B_GAMMA19[1:0] -
Himax Confidential -P.133-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
1 B_GAMMA20[1:0] B_GAMMA21[1:0] B_GAMMA22[1:0] B_GAMMA23[1:0] -
1 B_GAMMA24[1:0] B_GAMMA25[1:0] B_GAMMA26[1:0] B_GAMMA27[1:0] -
1 B_GAMMA28[1:0] B_GAMMA29[1:0] B_GAMMA30[1:0] B_GAMMA31[1:0] -
1 B_GAMMA32[1:0] - - - - - - -
0 1 1 0 0 0 0 1 1 -
1 ID1[7:0] 83h
1 ID2[7:0] 98h
C3 SETID Set ID
1 ID3[7:0] 0Ah
1 ID4[7:0] 00h
1 ID_TIMES[2:0] - - - - - E0h
0 1 1 0 0 0 1 0 0 -
1 DDB1[7:0] 00h
C4 SETDDB 1 DDB2[7:0] 00h Set DDB
1 DDB3[7:0] 00h
1 DDB4[7:0] 00h
0 1 1 0 0 1 0 0 1 -
PWM_P
EN_DI INVPUL SEL_BL
1 - SEL_PWMCLK[2:0] ERIOD[ 17h Set CABC
C9 SETCABC M_MIX S DUTY
16] Control
1 PWM_PERIOD[15:8] 00h
1 PWM_PERIOD[7:0] 2Eh
0 1 1 0 0 1 1 0 0 -
CC SETPANEL SS_PA GS_PA REV_P BGR_P Set Panel
1 - - - - 00h
NEL NEL ANE ANEL
0 1 1 0 1 0 0 1 0 - Set voltage
D2 SETOFFSET
1 VN_REFS[3:0] VP_REFS[3:0] 55h offset
Set GIP
0 1 1 0 1 0 0 1 1 -
Option0
GIP_EQ_MODE[ EQ_DELAY_HSY
1 - - - - 00h
1:0] NC[1:0]
1 - - - - - - EQ_DISC[1:0] 00h
1 EQ_DELAY_ON1[7:0] 00h
1 EQ_DELAY_ON2[7:0] 00h
1 EQ_DELAY_OFF1[7:0] 00h
1 EQ_DELAY_OFF2[7:0] 00h
1 GTO[7:0] 00h
1 GNO[7:0] 00h
1 USER_GIP_GATE[7:0] 08h
1 USER_GIP_GATE1[7:0] 08h
1 SHR0_3[3:0] SHR0_2[3:0] 32h
1 SHR0_1[3:0] SHR0[11:8] 10h
1 SHR0[7:0] 02h
1 - - - - SHR0_GS[11:8] 00h
1 SHR0_GS[7:0] 02h
1 SHR1_3[3:0] SHR1_2[3:0] 32h
1 SHR1_1[3:0] SHR1[11:8] 13h
D3 SETGIP0
1 SHR1[7:0] C0h
Bank0
1 - - - - SHR1_GS[11:8] 00h
1 SHR1_GS[7:0] 00h
1 SHR2_3[3:0] SHR2_2[3:0] 32h
1 SHR2_1[3:0] SHR2[11:8] 10h
1 SHR2[7:0] 08h
1 - - - - SHR2_GS[11:8] 00h
1 SHR2_GS[7:0] 00h
1 SHP0[3:0] SCP[3:0] 4Bh
1 SHP2[3:0] SHP1[3:0] 00h
1 CHR0[7:0] 06h
1 CHR0_GS[7:0] 06h
1 CHP0[3:0] CCP0[3:0] 47h
1 CHR1[7:0] 04h
1 CHR1_GS[7:0] 00h
1 CHP1[3:0] CCP1[3:0] 27h
1 vbp_setting[7:0] 00h
vbp_self OVERL
1 - _learnin AP_OP - DCHG1R[1:0] DCHG2R[1:0] 00h
g T
0 1 1 0 1 0 1 0 1 -
CGTS_L
1 - _INV[1]
COS1_L[5:0] 18h
Set GIP
D5 SETGIP1 CGTS_R
1 - COS1_R[5:0] 18h Option1
_INV[1]
CGTS_L
1 - _INV[2]
COS2_L[5:0] 18h

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NOP (No Operation)

00H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 0 0 0 0 00
Parameter NO PARAMETER
This command is an empty command; it does not have any effect on the display
Description
module.
Restriction -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Default N/A
Flow Chart -

Himax Confidential -P.141-

SWRESET (Software Reset)

01H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 0 0 0 1 01
Parameter NO PARAMETER
When the Software Reset command is written, it causes a software reset. It resets
Description the commands and parameters to their S/W Reset default values. (See default
tables in each command description.)
It will be necessary to wait 5msec before sending new command following
software reset.
The display module loads all display supplier’s factory default values to the
registers during this 5msec. If Software Reset is applied during Sleep Out mode, it
Restriction
will be necessary to wait 120msec before sending Sleep out command. Software
Reset Command cannot be sent during Sleep Out sequence.
The host processor needs continuing to send PCLK, HSYNC, VSYNC and DE
signals to HX8398-A for two frames after this command is sent.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A

Legend

SWRESET
Red and Blue

Parameter
Display whole
blank screen

Display
Flow Chart
Action
Set Commands
to S/W Default
Value
Mode

Sequential
transfer
Sleep In Mode

Himax Confidential -P.142-

RDDIDIF (Read Display Identification Information)

04H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 0 1 0 0 04
st
1 parameter 1 ID1[7:0] 83
nd
2 parameter 1 ID2[7:0] 98
rd
3 parameter 1 ID3[7:0] 0A
st
This read byte returns 24-bit display identification information. The 1 Parameter
identifies the LCD module’s manufacturer. It is specified by display supplier and for
nd
xx is defined as xxHEX. The 2 Parameter has 2 purposes. Bit7 (MSB) defines the
type of panel. 0=Driver (STN B/W), 1=Module (Colour). Bits 6..0 are used to track
the LCD module/driver version. It is defined by display supplier and it changes
each time a revision is made to the display, material or construction specifications.
See Table:
ID Byte Value V[7:0] Version Changes
Description 80h -- --
81h -- --
82h -- --
83h -- --
84h -- --
85h -- --
rd
The 3 parameter identifies the LCD module/driver. It is specified by display
supplier and for this LCD project module is defined as xxHEX.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence OTP Value
Default
S/W Reset OTP Value
H/W Reset OTP Value

Serial I/F Mode Legend

Command
RDDIDIF (04h)

Host
Parameter
Driver

Send ID1[7:0]
Display
Flow Chart

Send ID2[7:0] Action

Mode
Send ID3[7:0]

Sequential
transfer

Himax Confidential -P.143-

RDNUMPE (Read Number of the Parity Errors)

05H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 0 1 0 1 05
st
1 parameter 1 P7 P6 P5 P4 P3 P2 P1 P0 00
The first parameter is telling a number of the errors on DSI. The more detailed
description of the bits is below.
P[6..0] bits are telling a number of the errors.
Description P[7] is set to ‘1’ if there is overflow with P[6..0] bits.
P[7..0] bits are set to ‘0’s (as well as RDDSM(0Eh)’s D0 is set ‘0’ at the same time)
after there is sent the second parameter information (The read function is
completed).
Restriction SETEXTC turn on to enable this command
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

D S I I /F M o d e Legend

C om m and
RDNUMPE

(R 0 5 h )
H ost
P a r a m e te r
D r iv e r

S e n d 1 s t p a r a m e te r
D is p la y

Flow Chart

A c tio n
R D D S M ( R 0 E h ) 's D 0 = '0 '
P [7 :0 ] = " 0 0 " h

M ode

S e q u e n tia l
tr a n s fe r

Himax Confidential -P.144-

RDRED (Read Red Colour)

06H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 0 1 1 0 06
st
1 parameter 1 R7 R6 R5 R4 R3 R2 R1 R0 00
The first parameter is telling red colour value of the first pixel of the frame when
there is used DPI I/F.
Description 16 bit format: R5 is MSB and R1 is LSB. R7, R6 and R0 are set to ‘0’.
18 bit format: R5 is MSB and R0 is LSB. R7 and R6 are set to ‘0’.
24 bit format: R7 is MSB and R0 is LSB.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend

Command

Serial I/F Mode

Parameter

RDBLUE (06h)
Displa
Host y
Flow Chart
Driver
Actio
Send D[7:0]
n

Mode

Sequentia
l
transfer

Himax Confidential -P.145-

RDGREEN (Read Green Colour)

07H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 0 1 1 1 07
st
1 parameter 1 G7 G6 G5 G4 G3 G2 G1 G0 00
The first parameter is telling green colour value of the first pixel of the frame when
there is used DPI I/F.
Description
16 and 18 bit formats: G5 is MSB and G0 is LSB. G7 and G6 are set to ‘0’.
24 bit format: G7 is MSB and G0 is LSB.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend

Command

Serial I/F Mode

Parameter

RDBLUE (07h)
Displa
Host y
Flow Chart
Driver
Actio
Send D[7:0]
n

Mode

Sequentia
l
transfer

Himax Confidential -P.146-

RDBLUE (Read Blue Colour)

08H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 0 0 0 08
st
1 parameter 1 B7 B6 B5 B4 B3 B2 B1 B0 00
The first parameter is telling blue colour value of the first pixel of the frame
when there is used DPI I/F.
Description 16 bit format: B5 is MSB and B1 is LSB. B7, B6 and B0 are set to ‘0’.
18 bit format: B5 is MSB and B0 is LSB. B7 and B6 are set to ‘0’.
24 bit format: B7 is MSB and B0 is LSB.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend

Command

Serial I/F Mode

Parameter

RDBLUE (08h)
Display
Host
Flow Chart
Driver
Send D[7:0] Action

Mode

Sequential
transfer

Himax Confidential -P.147-

RDDST (Read Display Status)

09H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 0 0 1 09
st
1 parameter 1 D[31:24] 00
nd
2 parameter 1 D[23:16] 71
rd
3 parameter 1 D[15:8] 00
th
4 parameter 1 D[7:0] 00
This command indicates the current status of the display as described in the table
below:
Bit Description Comment
D31 Booster Voltage Status -
D30 Page Address Order -
D29 Column Address Order -
D28 Page/Column Order Set to ‘0’
D27 Line Address Order Set to ‘0’
D26 RGB/BGR Order -
D25 Display Data Latch Order -
D24 Flip Horizontal -
D23 Flip Vertical -
D22
D21 Interface Colour Pixel Format Definition -
D20
D19 Idle Mode On/Off -
D18 Partial Mode On/Off Set to ‘0’
D17 Sleep In/Out -
D16 Display Normal Mode On/Off -
D15 Vertical Scrolling Status Set to ‘0’
D14 Horizontal Scrolling Status Set to ‘0’
D13 Inversion Status -
D12 All Pixels On -
D11 All Pixels Off -
Description D10 Display On/Off -
D9 Tearing Effect Line On/Off -
D8
D7 Gamma Curve Selection -
D6
D5 Tearing Effect Output Line Mode -
D4 Horizontal Sync. (HSYNC, DPI I/F) -
D3 Vertical Sync. (VSYNC, DPI I/F) -
D2 Pixel Clock (DCK, DPI I/F) -
D1 Data Enable (ENABLE, DPI I/F) -
D0 Error on DSI -
Bit Values are explained overleaf.
Bit D31 – Booster Voltage Status
‘0’ = Booster Off or has a fault.
‘1’ = Booster On and working OK (Meets display supplier’s optical requirements).
Bit D30 – Page Address Order
‘0’ = Top to Bottom (When MADCTL B7=’0’).
‘1’ = Bottom to Top (When MADCTL B7=’1’).
Bit D29 – Column Address Order
‘0’ = Left to Right (When MADCTL B6=’0’).
‘1’ = Right to Left (When MADCTL B6=’1’).
Bit D28 – Page/Column Order
‘0’ = Normal (When MADCTL B5=’0’).
‘1’ = Rotation (When MADCTL B5=’1’).
This bit is not applicable for this project, so it is set to ‘0’
Himax Confidential -P.148-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
Bit D27 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4=’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4=’1’).
This bit is not applicable for this project, so it is set to ‘0’
Bit D26 – RGB/BGR Order
‘0’ = RGB (When MADCTL B3=’0’).
‘1’ = BGR (When MADCTL B3=’1’).
Bit D25 – Display Data Latch Order
‘0’ = LCD Refresh Left to Right (When MADCTL B2=’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2=’1’).
Bit D24 – Flip Horizontal
‘0’ = Normal (When MADCTL B1=’0’).
‘1’ = Flipped (When MADCTL B1=’1’).
Bit D23 – Flip Vertical
‘0’ = Normal (When MADCTL B0=’0’).
‘1’ = Flipped (When MADCTL B0=’1’).
Bits D22, D21, D20 – Interface Colour Pixel Format Definition
Interface Format D22 D21 D20
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16 Bit/Pixel 1 0 1
18 Bit/Pixel 1 1 0
24 Bit/Pixel 1 1 1
Bit D19 – Idle Mode On/Off
‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D18 – Partial Mode On/Off
‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
This bit is not applicable for this project, so it is set to ‘0’
Bit D17 – Sleep In/Out
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D16 – Display Normal Mode On/Off
‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D15 – Vertical Scrolling On/Off
‘0’ = Vertical Scrolling is Off.
‘1’ = Vertical Scrolling is On.
This bit is not applicable for this project, so it is set to ‘0’
Bit D14 – Horizontal Scrolling Status
This bit is not applicable for this project, so it is set to ‘0’
Bit D13 – Inversion On/Off
‘0’ = Inversion is Off.
‘1’ = Inversion is On.
Bit D12 – All Pixels On.
‘0’ = Nornal mode.
‘1’ = All Pixels On.
Bit D11 – All Pixels Off.
0’ = Nornal mode.
‘1’ = All Pixels Off.
Bit D10 – Display On/Off
‘0’ = Display is Off.
‘1’ = Display is On.
Bit D9 – Tearing Effect Line On/Off
‘0’ =Tearing Effect Line Off.
‘1’ = Tearing Effect On.
Bits D8, D7, D6 – Gamma Curve Selection
Himax Confidential -P.149-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
Gamma Curve Gamma Set (26h)
D8 D7 D6
Selected Parameter
Gamma Curve 1 0 0 0 GC0
Gamma Curve 2 0 0 1 Setting Inhibit
Gamma Curve 3 0 1 0 Setting Inhibit
Gamma Curve 4 0 1 1 Setting Inhibit
Not Defined 1 0 0 Not Defined
Not Defined 1 0 1 Not Defined
Not Defined 1 1 0 Not Defined
Not Defined 1 1 1 Not Defined
Bit D5 – Tearing Effect Line Output Mode.
‘0’ = Mode 1, V-Blanking only.
‘1’ = Mode 2, both H-Blanking and V-Blanking.
Bit D4 – Horizontal Sync. (HSYNC) On/Off, Note
‘0’ = Horizontal Sync. Line is Off (“Low”).
‘1’ = Horizontal Sync. Line is On (“High”).
Bit D3 – Vertical Sync. (VSYNC) On/Off, Note
‘0’ = Vertical Sync. Line is Off (“Low”).
‘1’ = Vertical Sync. Line is On (“High”).
Bit D2 – Pixel Clock (PCLK) On/Off, Note
‘0’ = Pixel Clock line is Off (“Low”).
‘1’ = Pixel Clock line is On (“High”).
Bit D1 – Data Enable (DE) On/Off, Note
‘0’ = Data Enable line is Off (“Low”).
‘1’ = Data Enable line is On (“High”).
Bit D0 –Error on DSI
‘0’ = No Error.
‘1’ = Error.
Note: This bit indicates current status of the line when this command has been
sent.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence Refer to Description
Default
S/W Reset Refer to Description
H/W Reset Refer to Description

Himax Confidential -P.150-

RDDST (09h) Command

Host
Driver Parameter
Send ST[31:24]

Displa
y
Flow Chart
Send ST[23:16]
Action

Send ST[15:8] Mode

Sequential
transfer
Send ST[7:0]

Himax Confidential -P.151-

RDDPM (Read Display Power Mode)

0AH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 0 1 0 0A
st
1 parameter 1 D7 D6 0 D4 D3 D2 0 0 08
This command indicates the current status of the display as described in the table
below:
Bit Description Comment
D7 Booster Voltage Status -
D6 Idle Mode On/Off -
D5 Partial Mode On/Off Set to ‘0’
D4 Sleep In/Out -
D3 Display Normal Mode On/Off -
D2 Display On/Off -
D1 Not Defined Set to ‘0’
D0 Not Defined Set to ‘0’

Bit D7 – Booster Voltage Status

‘0’ = Booster Off or has a fault.
‘1’ = Booster On and working OK (Meets display supplier’s optical requirements).
Description Bit D6 – Idle Mode On/Off
‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D5 – Partial Mode On/Off
‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
This bit is not applicable for this project, so it is set to ‘0’
Bit D4 – Sleep In/Out
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D3 – Display Normal Mode On/Off
‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D2 – Display On/Off
‘0’ = Display is Off.
‘1’ = Display is On.
Bits D1 and D0 are for future use and set to ‘0’.
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 08h
Default
S/W Reset 08h
H/W Reset 08h

Himax Confidential -P.152-

Legend

Command

Serial I/F Mode

Parameter

RDDPM (0Ah)
Display
Host
Flow Chart
Driver
Send D[7:0] Action

Mode

Sequential
transfer

Himax Confidential -P.153-

RDDMADCTL (Read Display MADCTL)

0BH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 0 1 1 0B
st
1 parameter 1 D7 D6 0 0 D3 D2 D1 D0 00
This command indicates the current status of the display as described in the table
below:
Bit Description Comment
D7 Page Address Order -
D6 Column Address Order -
D5 Page/Column Order Set to ‘0’
D4 Line Address Order Set to ‘0’
D3 RGB/BGR Order -
D2 Display Data Latch Order -
D1 Flip Horizontal -
D0 Flip Vertical -

Bit D7 – Page Address Order

‘0’ = Top to Bottom (When MADCTL B7=’0’).
‘1’ = Bottom to Top (When MADCTL B7=’1’).
Bit D6 – Column Address Order
‘0’ = Left to Right (When MADCTL B6=’0’).
‘1’ = Right to Left (When MADCTL B6=’1’).
Description Bit D5 – Page/Column Order
‘0’ = Normal (When MADCTL B5=’0’).
‘1’ = Rotation (When MADCTL B5=’1’).
This bit is not applicable for this project, so it is set to ‘0’
Bit D4 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4=’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4=’1’).
This bit is not applicable for this project, so it is set to ‘0’
Bit D3 – RGB/BGR Order
‘0’ = RGB (When MADCTL B3=’0’).
‘1’ = BGR (When MADCTL B3=’1’).
Bit D2 – Display Data Latch Order
‘0’ = LCD Refresh Left to Right (When MADCTL B2=’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2=’1’).
Bit D1 – Flip Horizontal
‘0’ = Normal (When MADCTL B1=’0’).
‘1’ = Flipped (When MADCTL B1=’1’).
Bit D0 – Flip Vertical
‘0’ = Normal (When MADCTL B0=’0’).
‘1’ = Flipped (When MADCTL B0=’1’).
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset No Change
H/W Reset 00h

Himax Confidential -P.154-

Legend

Red and Blue

Serial I/F Mode

Parameter

RDDMADCTR (0Bh)
Host Display
Flow Chart
Driver
Send D[7:0] Action

Mode

Sequential
transfer

Himax Confidential -P.155-

RDDCOLMOD (Read Display COLMOD)

0CH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 1 0 0 0C
st
1 parameter 1 0 D6 D5 D4 0 0 0 0 70
This command indicates the current status of the display as described in the table
below:
Bit Description Comment
D7 Reserved Set to ‘0’
D6 -
D5 DPI Interface Pixel format -
D4 -
D3 Reserved Set to ‘0’
D2 Reserved Set to ‘0’
D1 Reserved Set to ‘0’
D0 Reserved Set to ‘0’

Bits D6, D5, D4 – DPI Interface Colour Pixel Format Definition

Description Bits D2, D1, D0 – DBI Interface Colour Pixel Format Definition. These bits are not
applicable for this project, so it is set to “0”.

Interface Colour Format D6 D5 D4

Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16 bit/pixel 1 0 1
18 bit/pixel 1 1 0
24 bit/pixel 1 1 1
If the setting is not used then the corresponding bits in the parameter returned from
the display module are undefined.
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 70h
Default
S/W Reset 70h
H/W Reset 70h

Himax Confidential -P.156-

Legend

Red and Blue

Serial I/F Mode

Parameter

RDDCOLMOD (0Ch)

Host Display
Flow Chart
Driver
Send D[7:0] Action

Mode

Sequential
transfer

Himax Confidential -P.157-

RDDIM (Read Display Image Mode)

0DH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 1 0 1 0D
st
1 parameter 1 0 0 D5 D4 D3 D2 D1 D0 00
This command indicates the current status of the display as described in the table
below:
Bit D7 – Vertical Scrolling On/Off
This bit is not applicable for this project, so it is set to ‘0’
Bit D6 – Horizontal Scrolling Status
This bit is not applicable for this project, so it is set to ‘0’
Bit D5 – Inversion On/Off
‘0’ = Inversion is Off.
‘1’ = Inversion is On.
Bit D4 – All Pixels On
‘0’ = Normal Display
‘1’ = White Display
Bit D3 – All Pixels Off
Description ‘0’ = Normal Display
‘1’ = Black Display
Bits D2, D1, D0 – Gamma Curve Selection
Gamma Curve Gamma Set (26h)
D2 D1 D0
Selected Parameter
Gamma Curve1 0 0 0 GC0
Gamma Curve2 0 0 1 Setting Inhibit
Gamma Curve3 0 1 0 Setting Inhibit
Gamma Curve4 0 1 1 Setting Inhibit
Not Defined 1 0 0 Not Defined
Not Defined 1 0 1 Not Defined
Not Defined 1 1 0 Not Defined
Not Defined 1 1 1 Not Defined
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Himax Confidential -P.158-

Legend

Red and Blue

Serial I/F Mode

Parameter

RDDIM (0Dh)
Displa
Host y
Flow Chart
Driver
Send D[7:0] Action

Mode

Sequential
transfer

Himax Confidential -P.159-

RDDSM (Read Display Signal Mode)

0EH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 1 1 0 0E
st
1 parameter 1 D7 D6 D5 D4 D3 D2 0 D0 00
This command indicates the current status of the display described in the table as
below:
Bit D7 – Tearing Effect Line On/Off
‘0’ = Tearing Effect Line Off.
‘1’ = Tearing Effect On.
Bit D6 – Tearing Effect Line Output Mode.
‘0’ = Mode 1, V-Blanking only.
‘1’ = Mode 2, both H-Blanking and V-Blanking.
Bit D5 – Horizontal Sync. (DPI I/F) On/Off.
‘0’ = Horizontal Sync. Line is Off (“Low”).
‘1’ = Horizontal Sync. Line is On (“High”).
Bit D4 – Vertical Sync. (DPI I/F) On/Off.
Description
‘0’ = Vertical Sync. Line is Off (“Low”).
‘1’ = Vertical Sync. Line is On (“High”).
Bit D3 – Pixel Clock (PCLK, DPI I/F) On/Off.
‘0’ = PCLK line is Off (“Low”).
‘1’ = PCLK line is On (“High”).
Bit D2 – Data Enable (DE, DPI I/F) On/Off.
‘0’ = DE line is Off (“Low”).
‘1’ = DE line is On (“High”).
Bit D1 – Reserved.
Bit D0 –Error on DSI
‘0’ = No Error.
‘1’ = Error.
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Himax Confidential -P.160-

Red and Blue

Serial I/F Mode

Parameter

RDDSM (0Eh)
Displa
Host y
Flow Chart Driver
Send D[7:0] Action

Mode

Sequential
transfer

Himax Confidential -P.161-

RDDSDR (Read Display Self-Diagnostic Result)

0FH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 1 1 1 1 0F
st
1 parameter 1 D7 D6 D5 D4 0 0 0 0 00
The display module returns the self-diagnostic results following a Sleep Out
command.
Bit D7 – Register Loading Detection
Bit D6 – Functionality Detection
Description Bit D5 – Chip Attachment Detection
Set to ‘0’ if feature unimplemented.
Bit D4 – Display Glass Break Detection
Set to ‘0’ if feature unimplemented.
Bits D[3:0] – Reserved.
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend

Red and Blue

Serial I/F Mode

Parameter

RDDSDR (0Fh)
Displa
Host y
Flow Chart
Driver
Send D[7:0] Action

Mode

Sequential
transfer

Himax Confidential -P.162-

SLPIN (Sleep In)

10H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 1 0 0 0 0 10
Parameter NO PARAMETER
This command causes the LCD module to enter the minimum power consumption
mode.
In this mode the DC/DC converter is stopped, Internal oscillator is stopped, and
panel scanning is stopped.
Output[1:1280] Blank STOP

VST etc.(V scanner control logic) STOP

DISCHARGH 0V
DC charge in the capacitor
Description
DC/DC Converter 0V

DC/DC Converter 0V

Reset pulse for circuit inside panel

RESET

Internal Oscillator STOP STOP

This command has no effect when module is already in sleep in [Link] In
Mode can only be left by the Sleep Out Command (11h). It will be necessary to wait
5msec before sending next command, this is to allow time for the supply voltages
and clock circuits to stabilize. It will be necessary to wait 120msec after sending
Restriction
Sleep Out command (when in Sleep In Mode) before Sleep In command can be
sent.
The host processor continues to send PCLK, HSYNC, and VSYNC and DE signals
to HX8398-A for two frames after this command is sent.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A
It takes 120msec to get into Sleep In mode after SLPIN command issued.

SPLIN

Stop Legend
DC/DC Command
Converter
Display whole blank
Parameter
screen (Automatic
Flow Chart No effect to DISP Stop Display
ON/OFF Commands) Internal
Oscillator Action

Mode

Drain charge Sleep In Mode

Sequential
from LCD panel
transfer

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SLPOUT (Sleep Out)

11H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 1 0 0 0 1 11
Parameter NO PARAMETER
This command turns off sleep mode. In this mode the DC/DC converter is enabled,
Internal oscillator is started, and panel scanning is started.
Blank Memory
Out[1:1280] STOP contents

VST etc.(V scanner control logic)

0V CHARGE
DC charge in the capacitor
Description
DC:DC converter 0V

DC:DC converter 0V

Reset pulse for circuit inside panel RESET

START
Internal Oscillator STOP

This command has no effect when module is already in sleep out mode. Sleep Out
Mode can only be left by the Sleep In Command (10h). It will be necessary to wait
5msec before sending next command, this is to allow time for the supply voltages
and clock circuits to stabilize. The display module loads all display supplier’s factory
default values to the registers during this 5msec and there cannot be any abnormal
visual effect on the display image if factory default and register values are same
Restriction
when this load is done and when the display module is already Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec. It will be
necessary to alit 120msec after sending Sleep In command (when in Sleep Out
mode) before Sleep Out command can be sent.
The host processor continues to send PCLK, HSYNC, and VSYNC and DE signals
to HX8398-A for two frames after this command is sent.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A
It takes 120msec to become Sleep Out mode after SLPOUT command issued.
Legend
SLPOUT Command

Parameter
Start Display whole
Internal blank screen Display
Oscillator for 2 frames
(Automatic No Action
effect to DISP
Start up ON/OFF Mode
DC:DC Commands)
Flow Chart Converter
Sequential
transfer
Display
Charge
Memory contents
Offset voltage
In accordance
for LCD Panel
with the current
command table
settings

Sleep Out mode

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NORON (Normal Display Mode On)

13H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 1 0 0 1 1 13
Parameter NO PARAMETER
Description This command returns the display to normal mode.
Restriction This command has no effect when Normal Display mode is active.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence Normal display mode
Default
S/W Reset Normal display mode
H/W Reset Normal display mode
Flow Chart -

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INVOFF (Display Inversion Off)

20H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 0 0 0 0 20
Parameter NO PARAMETER
This command is used to recover from display inversion mode.
This command does not change any other status.

(Example)
Input Data Display
Description

Restriction This command has no effect when module is already in inversion off mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Normal display mode
Default
S/W Reset Normal display mode
H/W Reset Normal display mode

Legend
Display Inversion
On Mode Command

Parameter

Display
Flow Chart INVOFF
Action

Mode
Display Inversion
OFF Mode Sequential
transfer

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INVON (Display Inversion On)

21H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 0 0 0 1 21
Parameter NO PARAMETER
This command is used to enter into display inversion mode.
This command does not change any other status.

(Example)

Input Data Display

Description

Restriction This command has no effect when module is already in inversion on mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Normal display mode
Default
S/W Reset Normal display mode
H/W Reset Normal display mode

Legend
Display Inversion
Command
OFF Mode
Parameter

Display
Flow Chart INVON
Action

Mode
Display Inversion
ON Mode Sequential
transfer

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ALLPOFF (All Pixel Off)

22H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 0 0 1 0 22
Parameter NO PARAMETER
This command turns the display panel black in ‘Sleep Out’ –mode and a status of
the ‘Display On/Off’ –register can be ‘on’ or ‘off’.
This command does not change any other status.
(Example)

Input Data Display

Description

‘All Pixels On’ or ’Normal Display Mode On’ – commands are used to leave this
mode. The display is showing the input data after ‘Normal Display Mode On’
command.
Restriction This command has no effect when module is already in inversion on mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Normal display mode
Default
S/W Reset Normal display mode
H/W Reset Normal display mode

Legend
Normal Display mode Command

Parameter

Display
Flow Chart ALLPOFF
Action

Mode

Black Display
Sequential
transfer

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ALLPON(All Pixel On)

23H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 0 0 1 1 23
Parameter NO PARAMETER
This command turns the display panel white in ‘Sleep out ‘ –mode and a status of
the ‘Display On/Off’ –register can be ‘on’ or ‘off’.
This command does not change any other status.
(Example)

Input Data Display

Description

‘All Pixels Off’ or ’Normal Display Mode On’ – commands are used to leave this
mode. The display is showing the input data after ‘Normal Display Mode On’
command.
Restriction This command has no effect when module is already in inversion on mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Normal display mode
Default
S/W Reset Normal display mode
H/W Reset Normal display mode

Legend
Normal Display mode Command

Parameter

Display
Flow Chart ALLPON
Action

Mode

White Display
Sequential
transfer

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GAMSET (Gamma Set)

26H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 0 1 1 0 26
Parameter 1 GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 01
This command is used to select the desired Gamma curve for the current display.
A maximum of 4 fixed gamma curves can be selected. The curves are defined in
Curve Correction Power Supply Circuit. The curve is selected by setting the
appropriate bit in the parameter as described in the Table:
GC[7:0] Parameter Curve selected
Description
01h GC0 Gamma Curve 1
02h GC1 Setting Inhibit
04h GC2 Setting Inhibit
08h GC3 Setting Inhibit
Note: All other values are undefined.
Values of GC[7:0] not shown in table above are invalid and will not change the
Restriction
current selected Gamma curve until valid value is received.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 01h
Default
S/W Reset 01h
H/W Reset 01h

Legend
GAMSET Command

Parameter

GC [7:0] Display

Flow Chart Action

New Gamma Mode

Curve Loaded

Sequential
transfer

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DISPOFF (Display Off)

28H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 1 0 0 0 28
Parameter NO PARAMETER
This command is used to enter into DISPLAY OFF mode. In this mode, the output
from DPI I/F is disabled and blank page inserted.
This command does not change any other status.
There will be no abnormal visible effect on the display.
(Example)

Description
Input Data Display

Restriction This command has no effect when module is already in display off mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Display off
Default
S/W Reset Display off
H/W Reset Display off

Legend
Display On Command
Mode
Parameter

Display
Flow Chart DISPOFF
Action

Mode
Display Off
Mode Sequential
transfer

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DISPON (Display On)

29H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 1 0 0 1 29
Parameter NO PARAMETER
This command is used to recover from DISPLAY OFF mode. Output from DPI I/F is
enabled.
This command does not change any other status.
(Example)
Input Data Display
Description

Restriction This command has no effect when module is already in display on mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Display on
Default
S/W Reset Display on
H/W Reset Display on

Legend

Display Command
Off Mode
Parameter

Display
DISPON
Flow Chart
Action

Display Mode
On Mode

Sequential
transfer

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RAMWR (Memory Write)

2CH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 0 1 1 0 0 2C
st
1 parameter 1 D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
N parameter 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
This command transfers image data from the host processor to the display module’s
Description frame memory in Ilde mode. The start pointer is (0,0).Frame memory pointer will
auto increment when data is written.
Restriction The transferred data must be line based.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Default Contents of memory is set randomly and not cleared.

Legend
RAMWR Command

Parameter
Image Data
D1[7:0],D2[7:0], Display
...,Dn[7:0]
Flow Chart Action

Any Command Mode

Sequential
transfer

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TEOFF (Tearing Effect Line OFF)

34H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 0 1 0 0 34
Parameter NO PARAMETER
This command is used to turn OFF (Active Low) the Tearing Effect output signal
Description
from the TE signal line.
Restriction This command has no effect when Tearing Effect output is already OFF.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence Off
Default
S/W Reset Off
H/W Reset Off

Legend

Command
TE Line Output ON
Parameter

TEOFF Display
Flow Chart
Action
TE Line Output OFF
Mode

Sequential
transfer

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TEON (Tearing Effect Line ON)

35H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 0 1 0 1 35
Parameter 1 X X X X X X X M 00
This command is used to turn ON the Tearing Effect output signal from the TE
signal line.

The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line. (X=Don’t Care).
When M=0:
The Tearing Effect Output line consists of V-Blanking information only:
tvdl tvdh
Vertical Time
Description Scale

When M=1:
The Tearing Effect Output Line consists of both V-Blanking and H-Blanking
information:
tvdl tvdh

Vertical Time
Scale

Note: M=1 is not applicable for this project, so it is set to “0”.

Restriction This command has no effect when Tearing Effect output is already ON.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence Off
Default
S/W Reset Off
H/W Reset Off

Legend

TE Line Output OFF Command

Parameter
TEON
Display

Flow Chart
M Action

Mode
TE Line Output ON
Sequential
transfer

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MADCTL (Memory Access Control)

36H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 0 1 1 0 36
st
1 parameter 1 D7 D6 X X D3 D2 D1 D0 00
This command defines the display scanning direction of LCD.
This command makes no change on the other driver status.

Bit Assignment
Bit Name Description
Page Address Order LCD vertical updating order direction
D7
control
Column Address Order LCD horizontal updating order direction
D6
control
Page/Column Selection This bit is not applicable for this project,
D5
so it is set to “0”.
Line Address Order This bit is not applicable for this project,
D4
so it is set to “0”.
Colour selector switch control
D3 RGB-BGR Order (BGR) (0=RGB colour filter panel, 1=BGR
colour filter panel)
D2 Display Data Latch Order LCD horizontal refresh direction control
Flip Horizontal Select the Source driver scan direction
D1
(Source scan sequence) on panel module
Flip Vertical Select the Gate driver scan direction on
D0
(Gate scan sequence) panel module

RGB-BGR Order
Description D3= 0 D3= 1
RGB Driver IC R G B RGB Driver IC RGB
SIG1 SIG2 ………… SIG1200 SIG1 SIG2 ………… SIG1200

SIG1 SIG2 ………… SIG1200 SIG1 SIG2 ………… SIG1200

RG B RG B RG B B GR B GR B GR
RG B RG B RG B B GR B GR B GR
LCD panel LCD panel
Display Data Latch Order
D2= 0
Host Image Display Image

Top-Left (0,0) 1 Top-Left (0,0) 1

n n
1 m 1 m
D2= 1
Host Image Display Image

Top-Left (0,0) 1 Top-Left (0,0) 1

n n
1 m 1 m

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Top-Left (0,0) 1 Top-Left (0,0) 1

n n
1 m 1 m
SS= 1
Host Image Display Image

Top-Left (0,0) 1 Top-Left (0,0) 1

n n
1 m m 1

GS - Gate scan sequence

GS= 0
Host Image Display Image

Top-Left (0,0) 1 Top-Left (0,0) 1

n n
1 m 1 m
GS= 1
Host Image Display Image

Top-Left (0,0) 1 Top-Left (0,0) n

n 1
1 m 1 m

Restriction D5 and D4 are set to ‘0’ internally.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset No Change
H/W Reset 00h

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MADCTL Parameter

Display
1st parameter
Flow Chart
B[7:0] Action

Mode

Sequential
transfer

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IDMOFF (Idle mode off)

38H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 1 0 0 0 38
Parameter NO PARAMETER
This command is used to recover from Idle mode on. In the idle off mode, LCD
Description
can display maximum 16.7M colours.
Restriction This command has no effect when module is already in idle off mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Off
Default
S/W Reset Off
H/W Reset Off
Legend

Idle on mode Command

Parameter

IDMOFF Display

Flow Chart Action

Idle off mode Mode

Sequential
transfer

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IDMON (Idle mode on)

39H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 1 0 0 1 39
Parameter NO PARAMETER
This command is used to enter into Idle mode on. In the idle on mode, colour
expression is reduced. The primary and the secondary colours using MSB of
each R, G and B, 8 colour depth data is displayed.
(Example)
Memory Display

Description Display Colour

R7 – R0 G7 – G0 B7 – B0
Black 0XXXXX 0XXXXX 0XXXXX
Blue 0XXXXX 0XXXXX 1XXXXX
Red 1XXXXX 0XXXXX 0XXXXX
Magenta 1XXXXX 0XXXXX 1XXXXX
Green 0XXXXX 1XXXXX 0XXXXX
Cyan 0XXXXX 1XXXXX 1XXXXX
Yellow 1XXXXX 1XXXXX 0XXXXX
White 1XXXXX 1XXXXX 1XXXXX
X=don’t care
Restriction This command has no effect when module is already in idle on mode.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence Off
Default
S/W Reset Off
H/W Reset Off
Legend
Idle off mode Command

Parameter

IDMON Display

Flow Chart Action

Idle on mode
Mode

Sequential
transfer

Himax Confidential -P.180-

COLMOD (Interface Pixel Format)

3A H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 1 0 1 0 3A
st
1 parameter 1 X D6 D5 D4 X X X X 70
This command is used to define the format of RGB picture data.
D6~D4 : DPI Pixel format Definition.
Bits D7, D[3:0] : Reserved.
The formats are shown in the table:
Pixel Format D6 D5 D4
Not Defined 0 0 0
Not Defined 0 0 1
Description Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16 Bit/Pixel 1 0 1
18 Bit/Pixel 1 1 0
24 Bit/Pixel 1 1 1
If the setting is not used then the corresponding bits in the parameter returned
from the display module are undefined.
Restriction There is no visible effect until the image data is written.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 70h
Default
S/W Reset 70h
H/W Reset 70h
Legend
n Bit/Pixel Mode
Command

Parameter
Set Pixel Format
Display

Flow Chart Action

Parameter

Mode

New n Bit/Pixel Mode

Sequential
transfer

Himax Confidential -P.181-

Write_memory_contiune
3CH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 1 1 0 0 3C
st
1 parameter 1 D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
N parameter 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
This command transfers image data from the host processor to the display module’s
frame memory continuing from the pixel location following the previous
Description
write_memory_continue or write_memory_start command. Sending any other
command can stop frame Write.
Restriction The transferred data must be line based.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default value

Default Power On Sequence Contents of memory is set randomly
S/W Reset Contents of memory is set randomly

Legend
RAMWR Command

Parameter
Image Data
D1[7:0],D2[7:0], Display
...,Dn[7:0]
Flow Chart Action

Any Command Mode

Sequential
transfer

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TESL (Tear Effect Scan Lines)

44H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 0 0 1 0 0 44
st
1 parameter 1 TELINE[15:8] 00
nd
2 parameter 1 TELINE[7:0] 00
This command is turns on the display module’s Tearing Effect output signal on the
TE signal
Line when the display module reacfes line TELINE. The TE signal is not affected
by changing MADCTL bit B4.
The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line.
Description The Tearing Effect Output line consists of V-Blanking information only:
tvdl tvdh
Vertical Time
Scale

Note: That TELINE=0 is equivalent to TEMODE=0. The Tearing Effect Output

Line shall be active low when the display module is in Sleep mode.
Restriction The command has no effect when Tearing Effect output is already ON.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 0000h
Default
S/W Reset 0000h
H/W Reset 0000h

Flow Chart

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GETSCAN (Get the current scanline)

45H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 0 0 1 0 1 45
st
1 parameter 1 SLN[15:8] 00
nd
2 parameter 1 SLN[7:0] 00F
The display module returns the current scanline, N, used to update the display
device. The total number of scanlines on a display device is defined as VSYNC +
Description VBP + VACT + VFP. The first scanline is defined as the first line of V Sync and is
denoted as Line 0.
When in Sleep Mode, the value returned by get_scanline is undefined.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 0000h
Default
S/W Reset 0000h
H/W Reset 0000h

Flow Chart

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WRDISBV (Write Display Brightness)

51H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 0 0 0 1 51
st
1 parameter 1 DBV[7:0] 00
This command is used to adjust the brightness value of the display.
It should be checked what the relationship between this written value and output
brightness of the display is. This relationship is defined on the display module
Description specification.
In principle relationship is that 00h value means the lowest brightness and FFh
value means the highest brightness.
See chapter “5.12.3 Brightness Control Block”.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend
WRDISBV Command

Parameter
DBV[7..0]
Display
Flow Chart
New Display Action
Luminance
Value Loaded Mode

Sequential
transfer

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RDDISBV (Read Display Brightness Value)

52H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 0 0 1 0 52
st
1 parameter 1 DBV[7:0] 00
This command returns the brightness value of the display.
It should be checked what the relationship between this returned value and output
brightness of the display. This relationship is defined on the display
modulespecification is.
In principle the relationship is that 00h value means the lowest brightness and
FFh value means the highest brightness.
See chapters: “5.12.3 Brightness Control Block”, and “6.2.35 Write Display
Brightness (51h)”
Description DBV[7:0] is reset when display is in sleep-in mode.
DBV[7:0] is ‘00h’ when bit BCTRL of “6.2.37 Write CTRL Display (53h)” command
is ‘0’.
DBV[7:0] is manual set brightness specified with “6.2.37 Write CTRL Display
(53h)” command when bit BCTRL is ‘1’.
When bit BCTRL of “6.2.37 Write CTRL Display (53h)” command is ‘1’ and bit
C1/C0 of “6.2.37 Write Content Adaptive Brightness Control (55h)” are ‘0’,
DBV[7:0] output is the brightness value specified with “6.2.35 Write Display
Brightness (51h)” command.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h
Legend

Serial I/F Mode Command

Parameter
Read RDDISBV
Host Display
Flow Chart Display
Parameter Action

Mode

Sequential
transfer

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WRCTRLD (Write Control Display)

53H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 0 0 1 1 53
st
1 parameter 1 X X BCTRL X DD BL X X 00
This command is used to control display brightness.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch
brightness for display.
0 = Off (Brightness registers are 00h, DBV[7..0])
1 = On (Brightness registers are active, according to the other parameters.)
DD: Display Dimming(Only for manual brightness setting)
DD = 0: Display Dimming is off
Description DD = 1: Display Dimming is on
BL: Backlight Control On/Off
0 = Off (Completely turn off backlight circuit. Control lines must be low. )
1 = On
Dimming function is adapted to the brightness registers for display when bit
BCTRL is changed at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0.
When BL bit change from “On” to “Off”, backlight is turned off without gradual
dimming, even if dimming-on (DD=1) are selected.
X = Don’t care.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h
Legend
WRCTRLD Command

Parameter

BCTRL, DD, BL Display

Flow Chart
Action
New Control
Value Loaded Mode

Sequential
transfer

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RDCTRLD (Read Control Value Display)

54H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 0 1 0 0 54
st
1 parameter 1 0 0 BCTRL 0 DD BL 0 0 00
This command returns ambient light and brightness control values, see chapter:
“6.2.35 Write CTRL Display (53h)”.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch
brightness for display.
0 = Off
Description 1 = On
DD: Display Dimming.
DD = 0: Display Dimming is off
DD = 1: Display Dimming is on
BL: Backlight Control On/Off
0 = Off (completely turn off backlight circuit)
1 = On
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend
Command
Serial I/F Mode
Parameter
Read RDCTRLD Displa
Host y
Flow Chart Display
Parameter Action

Mode

Sequential
transfer

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WRCABC (Write Content Adaptive Brightness Control)

55 H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 0 1 0 1 55
st
1 parameter 1 X X X X X X C[1:0] 00
This command is used to set parameters for image content based adaptive
brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality,
which are defined on a table below. See chapter “5.12 Content Adaptive
Brightness Control (CABC)”.
Description C1 C0 Function
0 0 Off
0 1 User Interface Image
1 0 Still Picture
1 1 Moving Image
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend
Command
WRCABC
Parameter
Displa
1st parameter: C[1:0] y
Flow Chart
Action
New Adaptive Mode
Image Mode

Sequential
transfer

Himax Confidential -P.189-

RDCABC (Read Content Adaptive Brightness Control)

56H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 0 1 1 0 56
st
1 parameter 1 0 0 0 0 0 0 C1 C0 00
This command is used to set parameters for image content based adaptive
brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality,
which are defined on a table below. See chapter “5.12 Content Adaptive
Brightness Control (CABC)”.
Description C1 C0 Function
0 0 Off
0 1 User Interface Image
1 0 Still Picture
1 1 Moving Image
Restriction
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend
Command
Serial I/F Mode
Parameter
Read RDCABC
Host Display
Flow Chart Display
Parameter Action

Mode

Sequential
transfer

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WRCABCMB (Write CABC minimum brightness)

5E H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 1 1 1 0 5E
st
1 parameter 1 CMB[7:0] 00
This command is used to set the minimum brightness value of the display for
CABC function.
Description In principle relationship is that 00h value means the lowest brightness for CABC
and FFh value means the highest brightness for CABC.
See chapter “5.12.4 Minimum brightness setting of CABC function”.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend
WRCABCMB Command

Parameter
CMB[7..0]
Display

Flow Chart Action

New Display
Luminance
Value Loaded Mode

Sequential
transfer

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RDCABCMB (Read CABC minimum brightness)

5FH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 0 1 1 1 1 1 5F
st
1 parameter 1 CMB[7:0] 00
This command returns the minimum brightness value of CABC function.
In principle the relationship is that 00h value means the lowest brightness and FFh
value means the highest brightness.
Description
See chapter “5.12.4 Minimum brightness setting of CABC function”.
CMB[7:0] is CABC minimum brightness specified with “6.2.41 Write CABC
minimum brightness (5Eh)” command.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h

Legend
Command
Serial I/F Mode
Parameter
Read RDCABCMB
Host Display
Flow Chart Display
Parameter Action

Mode

Sequential
transfer

Himax Confidential -P.192-

RDABCSDR (Read Automatic Brightness Control Self-Diagnostic Result)

68H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 1 1 0 1 0 0 0 68
st
1 parameter 1 D[7:6] 0 0 0 0 0 0 00
This command indicates the status of the display self-diagnostic results for
automatic brightness control after Sleep Out –command as described in the table
below:
Bit D7 – Register Loading Detection.
Description
See section “5.9.1 Register loading Detection”.
Bit D6 – Functionality Detection.
See section “5.9.2 Functionality Detection “.
Bits D[5:0] are for future use and are set to ‘0’.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h
Legend
Command
Serial I/F Mode
Parameter
Read RDABCSDR
Host Display
Flow Chart
Display
Parameter Action

Mode

Sequential
transfer

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WRIMCOL (Write Idle Mode Color)

80 H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 0 0 0 0 0 0 80
st
1 parameter 1 X X X X X R G B 07
This command can be used to select color 1bbp Idle Mode. Color selection is
configured with bits [2:0], where:
D2: R Component
D1: G Component
D0: B Component

Color selection is defined in the following table:

1bpp Idle Mode
R G B
Color Selection
Black 0 0 0
Blue 0 0 1
Description Green 0 1 0
Cyan 0 1 1
Red 1 0 0
Magenta 1 0 1
Yellow 1 1 0
White 1 1 1

Default setting for 1bpp color selection for “Normal Black” panel is ‘White’;
R=G=B=’1’

X=Reserved
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 07h
Default
S/W Reset 07h
H/W Reset 07h

1bpp Idle Mode Legend

Color: White Command

Parameter
WRIMCOL Displa
y
Flow Chart
Action
011
Mode

1bpp Idle Mode

Sequential
Color: Cyan
transfer

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RDIMCOL (Read Idle Mode Color)

81 H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 0 0 0 0 0 1 81
st
1 parameter 1 0 0 0 0 0 R G B 07
This command returns the current color selection of 1bbp Idle Mode. Bits [2:0] are
defined as:
D2: R Component
D1: G Component
D0: B Component

Color selection is defined in the following table:

1bpp Idle Mode
R G B
Color Selection
Black 0 0 0
Description Blue 0 0 1
Green 0 1 0
Cyan 0 1 1
Red 1 0 0
Magenta 1 0 1
Yellow 1 1 0
White 1 1 1

Default setting for 1bpp color selection for “Normal Black” panel is ‘White’;
R=G=B=’1’

Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence 07h
Default
S/W Reset 07h
H/W Reset 07h

Legend
Command
Read RDIMCOL
Parameter
Host Displa
Display y
Flow Chart
Send Parameter Action

Mode

Sequential
transfer

Himax Confidential -P.195-

Read_DDB_start
A1H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 0 0 0 0 1 A1
st
1 parameter 1 xx xx xx xx xx xx xx xx xx
nd
2 parameter 1 xx xx xx xx xx xx xx xx xx
: 1 xx xx xx xx xx xx xx xx xx
th
N parameter 1 xx xx xx xx xx xx xx xx xx
This command reads identifying and descriptive information from the peripheral.
This information is organized in the Device Descriptor Block (DDB) stored on the
peripheral. The response to this command returns a sequence of bytes that may
be any length up to 64K bytes. Note that the returned sequence of bytes does not
necessarily correspond to the entire DDB; it may be a portion of a larger block of
data.
The format of returned data is as follows:
Parameter 1: LS (least significant) byte of Supplier ID. Supplier ID is a unique value
assigned to each peripheral supplier by the MIPI organization.
Parameter 2: MS (most significant) byte of Supplier ID.
Parameter 3: LS (least significant) byte of Supplier Elective Data. This is a byte of
information that is determined by the supplier. It could include model number or
revision information, for example.
Parameter 4: MS (most significant) byte of Supplier Elective Data
Parameter 5: single-byte Escape or Exit Code (EEC). The code is interpreted as
follows:
- FFh – Exit code – there is no more data in the Descriptor Block
- 00h – Escape code – there is supplier-proprietary data in the Descriptor Block
(does not conform to any MIPI standard)
- Any other value – there is DDB data in the Descriptor Block. The format and
Description
interpretation of this data is documented in MIPI Alliance Standard for Device
Descriptor Block (DDB).
DDBs may contain many more data fields providing information about the
peripheral.
In a DSI system, read activity takes the form of two separate transactions across
the bus: first the read command read_DDB_start from host processor to peripheral,
which includes the bus turn-around token.
The peripheral then takes control of the bus and returns the requested data. The
peripheral response to read_DDB_start is a Long Packet type, so its length may be
up to 64K bytes unless limited by a previous set_max_return_size command.
The response to a read_DDB_start command always starts at the beginning of the
Device Descriptor Block. After receiving the first packet and processing the
returned DDB data, the host processor may initiate a read_DDB_continue
command to access the next portion of the DDB. A read_DDB_continue command
begins the next read at the location following the last byte of the previous data read
from the DDB.
Subsequent read_DDB_continue commands can be used to read a DDB or
supplier-proprietary block of arbitrary size. There is, however, no obligation to read
the entire block. The host processor may choose to stop reading after completion
of any read_DDB_xxx command.
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

th
Power On Sequence PA1st~4 is OTP value, PA5th is FFh
Default th
S/W Reset PA1st~4 is OTP value, PA5th is FFh
th
H/W Reset PA1st~4 is OTP value, PA5th is FFh

Himax Confidential -P.196-

DDB Displa
D1[7:0],D2[7:0], y
Flow Chart ....,Dn[7:0] Actio
n
Mode
Any Command
Sequential
transfer

Himax Confidential -P.197-

Read_DDB_continue
A8H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 0 1 0 0 0 A8
st
1 parameter 1 xx xx xx xx xx xx xx xx xx
nd
2 parameter 1 xx xx xx xx xx xx xx xx xx
: 1 xx xx xx xx xx xx xx xx xx
th
N parameter 1 xx xx xx xx xx xx xx xx xx
A read_DDB_start command should be executed at least once before a
Description read_DDB_continue command to define the read location. Otherwise, data read
with a read_DDB_continue command is undefined.
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default Value
st th
Without A1h read, 1 ~4 read is the
st th th
Power On Sequence same as A8h 1 ~4 OTP value, after 5
read is FFh.
st th
Without A1h read, 1 ~4 read is the
Default st th th
S/W Reset same as A8h 1 ~4 OTP value, after 5
read is FFh.
st th
Without A1h read, 1 ~4 read is the
st th th
H/W Reset same as A8h 1 ~4 OTP value, after 5
read is FFh.

Legend
Command
Read_DDB_continue
Parameter
Displa
DDB y
Flow Chart D1[7:0],D2[7:0], Actio
....,Dn[7:0] n

Mode
Any Command
Sequential
transfer

Himax Confidential -P.198-

RDID1 (Read ID1)

DAH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 1 0 1 0 DA
st
1 parameter 1 ID1[7:0] 83
This read byte identifies the LCD module’s manufacturer. It is specified by display
Description
supplier and for xx is defined as xxHEX.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence OTP value
Default
S/W Reset OTP value
H/W Reset OTP value

Legend
Command
Serial I/F Mode
Parameter

Display
Read ID1
Flow Chart Host
Action
Display
Parameter Mode

Sequential
transfer

Himax Confidential -P.199-

RDID2 (Read ID2)

DBH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 1 0 1 1 DB
st
1 parameter 1 ID2[7:0] 98
This read byte is used to track the LCD module/driver version. It is defined by
Description display supplier and changes each time a revision is made to the display, material
or construction specifications.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence OTP value
Default
S/W Reset OTP value
H/W Reset OTP value

Legend
Command
Serial I/F Mode
Parameter

Display
Read ID2
Flow Chart Host
Action
Display
Parameter Mode

Sequential
transfer

Himax Confidential -P.200-

RDID3 (Read ID3)

DCH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 1 1 0 0 DC
st
1 parameter 1 ID3[7:0] 0A
Description This read byte identifies the LCD module/driver.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default Value

Power On Sequence OTP value
Default
S/W Reset OTP value
H/W Reset OTP value

Legend
Command
Serial I/F Mode
Parameter

Display
Read ID3
Flow Chart Host
Action
Display
Parameter Mode

Sequential
transfer

Himax Confidential -P.201-

6.3.1 SETPOWER: Set power (B1h)

SETPOWER( Set power related setting)

B1H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 0 0 0 1 B1
Bank0 DSTBY VSP_F
st 1 - - _OPT BOFF
AP[2:0] DSTB 08
1 parameter
nd
2 parameter 1 -VCI_LDOS[1:0] VRHP[4:0] 10
rd
3 parameter 1 VPPS[2:0] VRHN[4:0] 70
th
4 parameter 1 - - - - - XDK[2:0] 01
th
5 parameter 1 - - CLK_OPT[2:1] FS0[3:0] 32
th
6 parameter FS1[3:0] FS2[3:0] 33
th
7 parameter 1 - VGHS[9:8] BTP[4:0] 31
th
8 parameter 1 - VGLS[9:8] BTN[4:0] 31
th
9 parameter 1 VGHS[7:0] B4
th
10 parameter 1 VGLS[7:0] C8
st VCIRE VGLO
11 parameter 1 - G_OPT
VGLO2S[4:0] 00
2_EN
nd
12 parameter 1 DT1[1:0] DT2[1:0] DCDIV[3:0] 16
rd
13 parameter 1 - DCS[2:0] - DC[2:0] 73
th
14 parameter 1 - DTPS[2:0] - DTP[2:0] 02
th
15 parameter 1 - DTNS[2:0] - DTN[2:0] 02
Bank1 APF_ GASIOVCC_O
st 1 - - GASVCI_OPT[2:0] 64
1 parameter EN PT[1:0]
nd
2 parameter 1 - GASVSN_OPT[2:0] - GASVSP_OPT[2:0] 44
rd GASVGL_OPT[ GASVGH_OPT[
3 parameter 1 - - - - 11
1:0] 1:0]
This command is used to set related setting of power.

DSTBY_OPT: DSTB mode option. When DSTBY_OPT=0, logic power will be off and must
HWRESET to leave deep standy mode.

DSTB: Set ‘1’ to enter deep standby mode for saving power in SLPIN mode. User must
enter SLPIN mode before enter deep standby mode.

When DSTBY_OPT=0:
Enter DSTB Mode Leave DSTB Mode

Description Sleep in mode

Deep standby mode

Set DSTB=1
RESX pin low pulse at least
3ms

Deep standby mode

Sleep in mode

When DSTBY_OPT=1:

Himax Confidential -P.202-

Sleep in mode
Deep standby mode

Set DSTB=1

Set DSTB=0

Deep standby mode

Sleep in mode

VSP_FBOFF: VSP voltage feedback to control VSP pumping clock operation. “1” no
feecdback. For HX5186 mode, no effect for PFM circuit.

AP[2:0]: Adjust the amount of fixed current from the fixed current source for the operational
amplifier in the power supply circuit. When the amount of fixed current is increased, the
LCD driving capacity and the display quality are high, but the current consumption is
increased. This is a tradeoff, Adjust the fixed current by considering both the display quality
and the current consumption. During no display operation, when AP[2:0] = 000, the current
consumption can be reduced by stopping the operations of operational amplifier and
step-up circuit.
AP2 AP1 AP0 Constant Current of Operational Amplifier
0 0 0 Stop
0 0 1 0.5A
0 1 0 1.0A
0 1 1 1.5A
1 0 0 2.0A
1 0 1 2.5A
1 1 0 3.0A
1 1 1 3.5A

VCI_LDOS[1:0]: Set the regulated voltage of VDD3 in PCCS[2:0]= 010, 011, 100
VCI_LDOS 1 VCI_LDOS 0 VDD3 voltage
0 0 VDDDX2
0 1 VDDDX2.5
1 0 VDDDX2.75
1 1 VDDDX3

VRHP[4:0]: VSPR regulator output control setting for source data output driving.
VRHP[4:0] VSPR Voltage
0 0 0 0 0 Inhibited
0 0 0 0 1 3.1V
0 0 0 1 0 3.2V
0 0 0 1 1 3.3V
0 0 1 0 0 3.4V
0 0 1 0 1 3.5V
0 0 1 1 0 3.6V
0 0 1 1 1 3.7V
0 1 0 0 0 3.8V
0 1 0 0 1 3.9V
0 1 0 1 0 4.0V
0 1 0 1 1 4.1V
0 1 1 0 0 4.2V
0 1 1 0 1 4.3V
0 1 1 1 0 4.4V
0 1 1 1 1 4.5V
1 0 0 0 0 4.6V
Himax Confidential -P.203-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
1 0 0 0 1 4.7V
1 0 0 1 0 4.8V
1 0 0 1 1 4.9V
1 0 1 0 0 5.0V
1 0 1 0 1 5.1V
1 0 1 1 0 5.2V
1 0 1 1 1 5.3V
1 1 0 0 0 5.4V
1 1 0 0 1 5.5V
1 1 0 1 0 5.6V
1 1 0 1 1 5.7V
1 1 1 0 0 5.8V
1 1 1 0 1 Inhibited
1 1 1 1 0 Inhibited
1 1 1 1 1 Inhibited

VRHN[4:0]: VSNR regulator output control setting for source data output driving
VRHN[4:0] VSNR Voltage
0 0 0 0 0 Inhibited
0 0 0 0 1 -3.1V
0 0 0 1 0 -3.2V
0 0 0 1 1 -3.3V
0 0 1 0 0 -3.4V
0 0 1 0 1 -3.5V
0 0 1 1 0 -3.6V
0 0 1 1 1 -3.7V
0 1 0 0 0 -3.8V
0 1 0 0 1 -3.9V
0 1 0 1 0 -4.0V
0 1 0 1 1 -4.1V
0 1 1 0 0 -4.2V
0 1 1 0 1 -4.3V
0 1 1 1 0 -4.4V
0 1 1 1 1 -4.5V
1 0 0 0 0 -4.6V
1 0 0 0 1 -4.7V
1 0 0 1 0 -4.8V
1 0 0 1 1 -4.9V
1 0 1 0 0 -5.0V
1 0 1 0 1 -5.1V
1 0 1 1 0 -5.2V
1 0 1 1 1 -5.3V
1 1 0 0 0 -5.4V
1 1 0 0 1 -5.5V
1 1 0 1 0 -5.6V
1 1 0 1 1 -5.7V
1 1 1 0 0 -5.8V
1 1 1 0 1 Inhibited
1 1 1 1 0 Inhibited
1 1 1 1 1 Inhibited

VPPS[2:0]: Set VPP output voltage for OTP.

VPPS[2:0] VPP voltage
0 0 0 8.0V
0 0 1 8.1V
0 1 0 8.2V
0 1 1 8.25V
1 0 0 8.3V
Himax Confidential -P.204-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
1 0 1 8.4V
1 1 0 8.5V
1 1 1 External from VGH

CLK_OPT1: The pumping clock of VCI_REG will reset with Hsync when CLK_OPT1 = 1.

CLK_OPT2: The pumping clock of VGH/VGL will reset with Hsync when CLK_OPT2 = 1.

XDK[2:0]: Setting VSP Voltage pumping ratio in HX5186 mode.

XDK2 XDK1 XDK0 VSP
0 0 0 inhibit
0 0 1 X2
0 1 0 X1.5
0 1 1 inhibit
1 0 0 inhibit
1 0 1 inhibit
1 1 0 inhibit
1 1 1 X3

FS0[3:0]:Set the operating frequency of the step-up circuit for VSP/VSN voltage
generation. (Fosc_pump=4.89MHz)
FS0[3:0] Operation Frequency of Step-up Circuit
0 0 0 0 Fosc_pump/2
0 0 0 1 Fosc_pump/4
0 0 1 0 Fosc_pump/8
0 0 1 1 Fosc_pump/16
0 1 0 0 Fosc_pump/32
0 1 0 1 Fosc_pump/48
0 1 1 0 Fosc_pump/64
0 1 1 1 Fosc_pump/80
1 0 0 0 Fosc_pump/96
1 0 0 1 Fosc_pump/112
1 0 1 0 Fosc_pump/128
1 0 1 1 Fosc_pump/144
1 1 0 0 Fosc_pump/160
1 1 0 1 Fosc_pump/176
1 1 1 0 Fosc_pump/192
1 1 1 1 Fosc_pump/208

FS1[3:0]: Set the operating frequency of the step-up circuit for VGH/VGL voltage
generation. (Fosc_pump=4.89MHz)
FS1[3:0] Operation Frequency of Step-up Circuit
0 0 0 0 Fosc_pump/72
0 0 0 1 Fosc_pump/96
0 0 1 0 Fosc_pump/128
0 0 1 1 Fosc_pump/160
0 1 0 0 Fosc_pump/192
0 1 0 1 Fosc_pump/224
0 1 1 0 Fosc_pump/256
0 1 1 1 Fosc_pump/336
1 0 0 0 Hsync*4
1 0 0 1 Hsync*2
1 0 1 0 Hsync
1 0 1 1 Hsync/2
1 1 0 0 Hsync/4
1 1 0 1 Hsync/8
1 1 1 0 Hsync/16

Himax Confidential -P.205-

FS2[3:0]: Adjust the charge pump frequency of internal VCI_REG. (Fosc_pump=4.89MHz)

FS2[3:0] Operation Frequency of Step-up Circuit
0 0 0 0 Fosc_pump/72
0 0 0 1 Fosc_pump/96
0 0 1 0 Fosc_pump/128
0 0 1 1 Fosc_pump/160
0 1 0 0 Fosc_pump/192
0 1 0 1 Fosc_pump/224
0 1 1 0 Fosc_pump/256
0 1 1 1 Fosc_pump/336
1 0 0 0 Hsync*4
1 0 0 1 Hsync*2
1 0 1 0 Hsync
1 0 1 1 Hsync/2
1 1 0 0 Hsync/4
1 1 0 1 Hsync/8
1 1 1 0 Hsync/16
1 1 1 1 Inhibited

BTP[4:0]: Switch the output factor for DC/DC circuit for VSP voltage generation. The LCD
drive voltage level VSP can be selected according to the characteristic of liquid crystal
which panel used.
BTP4 BTP3 BTP2 BTP1 BTP0 VSP Voltage
0 0 0 0 0 3.00V
0 0 0 0 1 3.15V
0 0 0 1 0 3.30V
0 0 0 1 1 3.45V
0 0 1 0 0 3.60V
: :
1 0 0 0 0 5.40V
1 0 0 0 1 5.55V
1 0 0 1 0 5.70V
1 0 0 1 1 5.85V
1 0 1 0 0 6.00V
Others Inhibited

BTN[4:0]: Switch the output factor of DC/DC circuit for VSN voltage generation. The LCD
drive voltage level VSN can be selected according to the characteristic of liquid crystal
which panel used.
BTN4 BTN3 BTN2 BTN1 BTN0 VSN Voltage
0 0 0 0 0 -3.00V
0 0 0 0 1 -3.15V
0 0 0 1 0 -3.30V
0 0 0 1 1 -3.45V
0 0 1 0 0 -3.60V
: :
1 0 0 0 0 -5.40V
1 0 0 0 1 -5.55V
1 0 0 1 0 -5.70V
1 0 0 1 1 -5.85V
1 0 1 0 0 -6.00V
Others Inhibited

VGHS[9:7]: Specify the VGH voltage source.

VGHS9 VGHS8 VGHS7 VGH Voltage pumping ratio
0 0 0 VCI_REG-VSN
Himax Confidential -P.206-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
0 0 1 VSP-VSN
0 1 0 VSP-VSN+VCI_REG
0 1 1 2*VSP-VSN
1 0 0 VCI_REG+VSP-2*VSN
1 0 1 2*VSP-2*VSN
1 1 0 VCI_REG+2*VSP-2*VSN
1 1 1 3*VSP-2*VSN

VGHS[6:0]: VGH regulator output voltage setting. The LCD drive voltage level VGH can be
selected according to the characteristic of liquid crystal which panel used.
VGHS[6:0] VGH Voltage
0 0 0 0 0 0 0 7.3V
0 0 0 0 0 0 1 7.4V
0 0 0 0 0 1 0 7.5V
0 0 0 0 0 1 1 7.6V
: :
0 1 1 0 0 1 1 12.4V
0 1 1 0 1 0 0 12.5V
0 1 1 0 1 0 1 12.6V
0 1 1 0 1 1 0 12.7V
: :
1 1 1 1 1 0 1 19.8V
1 1 1 1 1 1 0 19.9V
1 1 1 1 1 1 1 20.0V

VGLS[9:7]: Specify the VGL voltage source.

VGLS9 VGLS8 VGLS7 VGL Voltage pumping ratio
0 0 0 VSN-VCI_REG
0 0 1 VSN-VSP
0 1 0 2*VSN-VCI_REG
0 1 1 2*VSN-VSP
1 0 0 2*VSN-VSP
1 0 1 2*VSN-VSP
1 1 0 2*VSN-VSP
1 1 1 2*VSN-VSP

VGLS[6:0]: VGL regulator output voltage setting. The LCD drive voltage level VGL can be
selected according to the characteristic of liquid crystal which panel used.
VGLS[6:0] VGL Voltage
0 0 0 0 0 0 0 -5.3V
0 0 0 0 0 0 1 -5.4V
0 0 0 0 0 1 0 -5.5V
0 0 0 0 0 1 1 -5.6V
: :
1 0 0 0 1 1 1 -12.4V
1 0 0 1 0 0 0 -12.5V
1 0 0 1 0 0 1 -12.6V
1 0 0 1 0 1 0 -12.7V
: :
1 1 1 1 1 0 1 -17.8V
1 1 1 1 1 1 0 -17.9V
1 1 1 1 1 1 1 -18.0V

VCIREG_OPT: VCI_REG voltage setting.

0: VCI_REG = 0.5*VSP
1: VCI_REG = VDD3

VGLO2_EN: ”1” Enable VGLO2 voltage.

Himax Confidential -P.207-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04

VGLO2S[4:0]: VGLO2 regulator output voltage setting. The LCD driving voltage level
VGLO can be selected according to the characteristic of liquid crystal which panel used.
VGLO2S[4:0] VGLO2 Voltage
0 0 0 0 0 -7.0V
0 0 0 0 1 -7.5V
0 0 0 1 0 -8.0V
0 0 0 1 1 -8.5V
0 0 1 0 0 -9.0V
0 0 1 0 1 -9.5V
0 0 1 1 0 -10.0V
0 0 1 1 1 -10.5V
0 1 0 0 0 -11.0V
: :
1 0 1 0 1 -17.50
1 0 1 1 0 -18.00
1 0 1 1 1 -18.00
1 1 0 0 0 -18.00
1 1 0 0 1 -18.00
1 1 0 1 0 -18.00
1 1 0 1 1 -18.00
1 1 1 0 0 -18.00
1 1 1 0 1 -18.00
1 1 1 1 0 -18.00
1 1 1 1 1 -18.00

DT1[1:0]:Delay time of power on and power off sequence.

DT1[1:0] Delay time of power on and power off sequence
0 0 0ms
0 1 2.5ms
1 0 5ms
1 1 7.5ms

DT2[1:0]:Delay time of power on and power off sequence.

DT2[1:0] Delay time of power on and power off sequence
0 0 0ms
0 1 2.5ms
1 0 5ms
1 1 7.5ms

DCDIV[3:0]: Set the normal operate frequency FoscD of DC/DC converter circuit during
normal mode. (Fosc=88MHz)
Normal operate frequency of
DCDIV[3:0]
DC/DC converter(foscD)
0 0 0 0 Fosc/2
0 0 0 1 Fosc/4
0 0 1 0 Fosc/8
0 0 1 1 Fosc/16
0 1 0 0 Fosc/20
0 1 0 1 Fosc/24
0 1 1 0 Fosc/28
0 1 1 1 Fosc/32
1 0 0 0 Fosc/36
1 0 0 1 Fosc/40
1 0 1 0 Fosc/44
1 0 1 1 Fosc/48
1 1 0 0 Fosc/52

Himax Confidential -P.208-

DCS[2:0]: Soft start VSP/VSN frequency of DC/DC clock.

DCS[2:0] Operation Frequency of DC/DC Clock
0 0 0 4/foscD
0 0 1 5/foscD
0 1 0 6/foscD
0 1 1 7/foscD
1 0 0 8/foscD
1 0 1 10/foscD
1 1 0 11/foscD
1 1 1 12/foscD

DC[2:0]: Operation VSP/VSN frequency of DC/DC clock.

DC[2:0] Operation Frequency of DC/DC Clock
0 0 0 4/foscD
0 0 1 5/foscD
0 1 0 6/foscD
0 1 1 7/foscD
1 0 0 8/foscD
1 0 1 10/foscD
1 1 0 11/foscD
1 1 1 12/foscD

DTPS[2:0]: For PFM circuit. Set the soft start operating duty cycle of VSP.
DTPS[2:0] Soft start operation duty of VSP
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8

DTP[2:0]: For PFM circuit:Set the operating duty cycle of VSP.

DTP[2:0] Operation duty of VSP
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8

DTNS[2:0]: For PFM circuit. Set the soft start operating duty cycle of VSN.
DTNS[2:0] Soft start operation duty of VSN
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7

Himax Confidential -P.209-

DTN[2:0]: For PFM circuit:Set the operating duty cycle of VSN.

DTN[2:0] Operation duty of VSN
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8

VSP Phase VSN Phase VSP Phase

Charging Pumping Charging Pumping Charging Pumping

Phase Phase Phase Phase Phase Phase

DTP[2:0] DTN[2:0]

DC[2:0] DC[2:0]

APF_EN: Abnormal power-off detection enable (GAS function). “1”: Enable.

GASIOVCC_OPT[1:0]: Set VDD1 threshold voltage of GAS function.

GASIOVCC_OPT[1:0] GAS threshold VDD1 voltage
0 0 1.2V
0 1 1.3V
1 0 1.4V
1 1 1.5V

GASVCI_OPT[2:0]: Set VDD3 threshold voltage of GAS function.

GASVCI_OPT[2:0] GAS threshold VDD3 voltage
0 0 0 1.9V
0 0 1 2.0V
0 1 0 2.1V
0 1 1 2.2V
1 0 0 2.3V
1 0 1 2.4V
1 1 0 2.5V
1 1 1 2.6V

GASVSN_OPT[2:0]: Set VSN threshold voltage of GAS function.

GASVSN_OPT[2:0] GAS threshold VSN voltage
0 0 0 -2.8V
0 0 1 -3.0V
0 1 0 -3.2V
0 1 1 -3.4V
1 0 0 -3.6V
1 0 1 -3.8V
1 1 0 -4.0V
Himax Confidential -P.210-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
1 1 1 -4.2V

GASVSP_OPT[2:0]: Set VSP threshold voltage of GAS function.

GASVSP_OPT[2:0] GAS threshold VSP voltage
0 0 0 2.8V
0 0 1 3.0V
0 1 0 3.2V
0 1 1 3.4V
1 0 0 3.6V
1 0 1 3.8V
1 1 0 4.0V
1 1 1 4.2V

GASVGL_OPT[1:0]: Set VGL threshold voltage of GAS function.

GASVGL_OPT[1:0] GAS threshold VGL voltage
0 0 -6V
0 1 -7V
1 0 -8V
1 1 -9V

GASVGH_OPT[1:0]: Set VGH threshold voltage of GAS function.

GASVGH_OPT[1:0] GAS threshold VGH voltage
0 0 6V
0 1 7V
1 0 8V
1 1 9V
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.211-

SETDISP( Set display related register)

B2H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 0 0 1 0 B2
Bank0 ZZ_L ZZ_E ZZ_2P
st 1 - - NW[2:0] 40
1 parameter R O L
nd MESS
2 parameter 1 H_RES[2:0] - - - - 80
I_ENB
rd
3 parameter 1 NL[7:0] AE
th
4 parameter 1 BP [7:0] 1C
th
5 parameter 1 FP [7:0] 0B
th
6 parameter 1 RTN[7:0] 45
th END_ INIT_
7 parameter 1 - END_SET_0[1:0] - INIT_SET_0[1:0] 00
SET SET
th
8 parameter 1 - - INIT_SET_1[1:0] - - INIT_SET_2[1:0] 00
th
9 parameter 1 - - END_SET_1[1:0] - - END_SET_2[1:0] 00
INIT_V END_V
th INIT_S END_S
10 parameter 1 - - D_SEL
COM_ - - D_SEL
COM_ 00
SEL SEL
DISP_
st
11 parameter 1 FRM_PATTERN_CYCLE[3:0] BIST_ FRM_SCAN_CYCLE[2:0] C0
EN
This command is used to set display related register

NW[2:0]: Inversion type setting.

NW[2:0] Inversion type
0 0 0 Column inversion
0 0 1 1-dot inversion
0 1 0 2-dot inversion
0 1 1 4-dot inversion
1 0 0 8-dot inversion
1 0 1 Zig-zag inversion
1 1 0 2-dot-2 inversion
1 1 1 3-dot inversion

ZZ_LR: Zig-zag Left / Right mode selection.

ZZ_LR Zig-zag Left / Right mode selection
0 SD0, S1~S3240
Description 1 S1~ S3240, SD3241

ZZ_EO: Zig-zag Odd / Even mode selection.

ZZ_EO Zig-zag Odd / Even mode selection
0 Odd-line shift
1 Even-line shift

ZZ_2PL: Zig-zag 1H/2H selection when NW[2:0]=101

ZZ_2PL Zig-zag 1H/2H selection
0 1H Zig-zag
1 2H Zig-zag

MESSI_ENB : Support Nokia DCS enable bit. “0” Enable.

0: support Nokia,don’t support 44h CMD
1: support 44h CMD to adjust the position of TE(horizontal)

H_RES[2:0]: Resolution selection.

Himax Confidential -P.212-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
H_RES[2:0] Resolution Source channels
000 1080RGB x (528 + 8xNL) dot S1 ~ S3240
001 1024RGB x (528 + 8xNL) dot S1 ~ S1536 , S1705 ~ S3240
010 960RGB x (528 + 8xNL) dot S1 ~ S1440 , S1801 ~ S3240
011 900RGB x (528 + 8xNL) dot S1 ~ S1350 , S1891 ~ S3240
100 800RGB x (528 + 8xNL) dot S1 ~ S1200 , S2041 ~ S3240
101 720RGB x (528 + 8xNL) dot S1 ~ S1080 , S2161 ~ S3240
110 Inhibited -
111 Inhibited -

NL[7:0]: Setting the number of lines to drive the LCD at an interval of 8 lines. The number
of lines must be the same or more than the number of lines necessary for the size of the
liquid crystal panel.
NL[7:0] Lines
0 0 0 0 0 0 0 0 528
0 0 0 0 0 0 0 1 536
: :
1 0 1 0 1 1 1 0 1920

BP[7:0] : Specify the amount of scan line for back porch(BP) in blanking.
FP[7:0]: Specify the amount of scan line for front porch (FP) in blanking.

FP[7:0] / BP[7:0] Number of front porch/ back porch Lines

8h’00 2 lines
8h’01 3 lines
8h’02 4 lines
8h’03 5 lines
8h’04 6 lines
8h’05 7 lines
: :
8h’FB 253 lines
8h’FC 254 lines
8h’FD 255 lines
8h’FE 256 lines
8h’FF 257 lines
Note: Set BP[7:0] = VS + VBP – 2, and FP[7:0] = VFP – 2.

RTN[7:0]: A cycle time of line width in blanking.

(1 TCON clock period= 1/22MHz)
RTN[7:0] Clock per Line
8h’00 97 TCON CLK
8h’01 98 TCON CLK
8h’02 99 TCON CLK
: :
8’hFD 350 TCON CLK
8’hFE 351 TCON CLK
8’hFF 352 TCON CLK

INIT_SD_SEL/END_SD_SEL: Source driver voltage control at D[1:0]=01

INIT_SD_SEL /END_SD_SEL Voltage level
0 GND
1 Blanking

INIT_VCOM_SEL/END_VCOM_SEL: VCOM voltage control at D[1:0]=01

Himax Confidential -P.213-

INIT_SET_X /END_SET_X: GIP control at D[1:0]=01, GIP state set by RD8h

INIT_SET_0[1:0]/
INIT_SET INIT_SET_1[1:0]/ Time or Frame By time/frame
INIT_SET_2[1:0]
0 00 0 frame By frame
0 01 1 frame By frame
0 10 2 frames By frame
0 11 3 frames By frame
1 00 8ms By time
1 01 16ms By time
1 10 24ms By time
1 11 32ms By time

END _SET_0[1:0]/
END_SET END _SET_1[1:0]/ Time or Frame By time/frame
END _SET_2[1:0]
0 00 0 frame By frame
0 01 1 frame By frame
0 10 2 frames By frame
0 11 3 frames By frame
1 00 8ms By time
1 01 16ms By time
1 10 24ms By time
1 11 32ms By time
Note: INIT means SLPIN to SLPOUT
END means SLPOUT to SLPIN

DISP_BIST_EN: Set “1” enable SW free running mode.

FRM_PATTERN_CYCLE[3:0]: Number of Free-running mode pattern.

FRM_PATTERN_CYCLE[3:0] Free-running mode pattern number
0000 White
0001 White, Black
0010 White, Black, Red
0011 White, Black, Red, Green
0100 White, Black, Red, Blue, Green
0101 White, Black, Red, Blue, Green, Gray127
0110 White, Black, Red, Blue, Green, Gray127, Color bar
0111 White, Black, Red, Blue, Green, Gray127, Color bar,
H-Grayscale
1000 White, Black, Red, Blue, Green, Gray127,
Color bar ,H-Grayscale, V-Grayscale
1001 White, Black, Red, Blue, Green, Gray127,
Color bar, H-Grayscale, V-Grayscale,
White pattern with black outline
1010 White, Black, Red, Blue, Green, Gray127, Color bar,
H-Grayscale, V-Grayscale, White pattern with black
outline, Checker 1x1
1011 White, Black, Red, Blue, Green, Gray127, Color bar,
H-Grayscale, V-Grayscale, White pattern with black
Himax Confidential -P.214-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
outline, Checker 1x1, Gray128
1100 White, Black, Red, Blue, Green, Gray127, Color bar,
H-Grayscale, V-Grayscale, White pattern with black
outline, Checker 1x1, Gray128, Black
Others Inhibited

FRM_SCAN_CYCLE[2:0]: Free-running each pattern keeps time.

FRM_ SCAN_CYCLE[2:0] Free-running mode pattern keep time
000 1s
001 2s
010 4s
011 8s
Others Inhibited

Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.215-

SETCYC(Set panel driving timing)

B4H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 0 1 0 0 B4
st
1 parameter 1 GEN_ON[7:0] 00
nd
2 parameter 1 GEN_OFF[7:0] FF
rd
3 parameter 1 SPON[7:0] 03
th
4 parameter 1 SPOFF[7:0] 38
th
5 parameter 1 CON[7:0] 0A
th
6 parameter 1 COFF[7:0] 6C
th
7 parameter 1 CON1[7:0] 05
th
8 parameter 1 COFF1[7:0] 36
th
9 parameter 1 EQON1[7:0] 05
th
10 parameter 1 SON[7:0] 10
st
11 parameter 1 SOFF[7:0] 75
nd
12 parameter 1 SAP1_P[3:0] SAP1_N[3:0] 22h
rd
13 parameter 1 - - - - - SAP2[3:0] 03h
th
14 parameter 1 DX2OFF[7:0] 3A
th
15 parameter 1 SPON_MPU[7:0] 03
th
16 parameter 1 SPOFF_MPU[7:0] 38
th
17 parameter 1 CON_MPU[7:0] 0A
th
18 parameter 1 COFF_MPU[7:0] 6C
th
19 parameter 1 CON1_MPU[7:0] 05
th
20 parameter 1 COFF1_MPU[7:0] 36
st
21 parameter 1 EQON1_MPU[7:0] 05
nd
22 parameter 1 SON_MPU[7:0] 10
rd
23 parameter 1 SOFF_MPU[7:0] 75
th
24 parameter 1 DX2OFF_MPU[7:0] 3A
th DX2_
25 parameter 1 - - - - - - - 00
EN
This command is used to set display waveform cycles.

GEN_ON[7:0]: Gamma OP turned on timing (in-house function not open).

GEN_OFF[7:0]: Gamma OP turned off timing (in-house function not open).

SPON[7:0]: Fine tune the Start and End signal delay from original starting point.
SPON_MPU[7:0]: Fine tune the Start and End signal delay from original starting point for
blanking frame.
(1 TCON CLK period = 1/22MHz)
SPON[7:0]/ SPON_MPU[7:0] Start / END signal output start delay
0x00h 0 TCON CLK
0x01h 1TCON CLK
Description 0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK

SPOFF[7:0]: Fine tune the Start and End signal ending point.
SPOFF_MPU[7:0]: Fine tune the Start and End signal ending point for blanking frame.
SPOFF[7:0]/ SPOFF_MPU[7:0] Start / END signal output end delay
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
Himax Confidential -P.216-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
Note: When output Start / End signal width is 1- Hsync only, set SPON[7:0] < SPOFF[7:0]

CON[7:0]/CON1[7:0]: Fine tune the Clock signal delay from original starting point.
CON_MPU[7:0]/CON1_MPU[7:0]: Fine tune the Clock signal delay from original starting
point for blanking frame.
CON[7:0]/ CON_MPU[7:0] Clock signal output start delay
CON1[7:0]/ CON1_MPU[7:0]
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK

COFF[7:0]/COFF1[7:0]: Fine tune the Clock signal ending point.

COFF_MPU[7:0]/COFF1_MPU[7:0]: Fine tune the Clock signal ending point for blanking
frame.
COFF[7:0]/ COFF_MPU[7:0] Clock signal output end delay
COFF1[7:0]/ COFF1_MPU[7:0]
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
Note: When output Clock signal width is 1- Hsync only, set COFF[7:0] ≧ CON[7:0] + 2

SON[7:0]: Source OP turn on time.

SOFF[7:0]: Source OP turn off time.
SON_MPU[7:0]: Source OP turn on time for blanking frame.
SOFF_MPU[7:0]: Source OP turn off time for blanking frame.

SON[7:0]/SON_MPU[7:0] Source OP turn on/off time

SOFF[7:0]/ SOFF_MPU[7:0]
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK

Himax Confidential -P.217-

VSYNC

HSYNC

SPOFF[7:0]
SPON[7:0]
SHR0[11:0]
Start1
SHP[3:0] define the width of high pulse

End1 SHR1[11:0]

COFF[7:0]
CON[7:0]
CHR[7:0]
Clock1
CHP[3:0] define the width of high pulse

Clock2

1 frame
1920 lines VBLK

GSP

Normal scan
UD=High

CK1 1 3 5 1 3
1919 1921

CK2 0 2 4 0 2
1920 1922

Reverse scan
UD=Low

CK1 0 2
0 2 4
1920 1922

CK2 1
1 3 5 3
1919 1921

HS
COFF[7:0]

CON[7:0]
CK1(2)

CK2(1)

EQON1[7:0]: Specify the source EQ period.

EQON1_MPU[7:0]: Specify the source EQ period for blanking frame.
EQON1[7:0]/ EQON1_MPU[7:0]] Source EQ time
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:

Himax Confidential -P.218-

DX2OFF[7:0]: Source driving enhancement period setting.

DX2OFF_MPU[7:0]: Source driving enhancement period setting for blanking frame.
DX2OFF[7:0]/DX2OFF_MPU[7:0] Set source enhancement time
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK

DX2_EN: DX2 on period selection

“1”: SON ~ DX2OFF
1-Line Period 1-Line Period

SOFF SOFF

DX2OFF DX2OFF
S(N)
SON
SON
DX2 on EQON1
EQON1
Charge
sharing
VSSA VSSA
DX2 on VSSA
Charge
sharing

“0”: SON ~ SOFF

1-Line Period 1-Line Period

SOFF SOFF

S(N)
SON
SON
DX2 on EQON1
EQON1
Charge
sharing
VSSA VSSA
DX2 on VSSA
Charge
sharing

st
SAP1_P[3:0] / SAP1_N[3:0]: 1 stage OP bias current adjust
nd
SAP2[2:0]: class-AB (2 ) stage OP bias current adjust:
st
Total OP biase current = 1 OP current + class-AB biase current
Different SAP1_P[3:0] / SAP1_N[3:0] will have map to diffent class-AB current setting

st
SAP2[2:0] 1 stage OP Class AB OP
Total
(SAP1_P[3:0] / SAP2_N[3:0]=0011)

Himax Confidential -P.219-

st
SAP1_P[3:0] / SAP1_N[3:0] 1 stage OP Class AB OP
Total
(SAP2[2:0]=011)
0 0 0 0 0.222 uA 0.076 uA 0.298 uA
0 0 0 1 0.431 uA 0.149 uA 0.58 uA
0 0 1 0 0.657 uA 0.23 uA 0.887uA
0 0 1 1 0.857 uA 0.307 uA 1.164 uA
0 1 0 0 1.075 uA 0.392 uA 1.467 uA
0 1 0 1 1.269 uA 0.477 uA 1.746uA
0 1 1 0 1.484 uA 0.563 uA 2.047 uA
0 1 1 1 1.677 uA 0.644 uA 2.321 uA
1 0 0 0 1.888 uA 0.738 uA 2.626 uA
1 0 0 1 2.079 uA 0.823uA 2.902 uA
1 0 1 0 2.289 uA 0.916 uA 3.205 uA
1 0 1 1 2.476 uA 0.999 uA 3.475 uA
1 1 0 0 2.683 uA 1.096 uA 3.779 uA
1 1 0 1 2.874 uA 1.182 uA 4.056 uA
1 1 1 0 3.074 uA 1.277 uA 4.351 uA
1 1 1 1 3.258 uA 1.359 uA 4.617 uA
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.220-

SETVCOM ( Set VCOM Voltage)

B6 H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 0 1 1 0 B6
st
1 parameter 1 VCMC_F[7:0] 34
nd
2 parameter 1 VCMC_B[7:0] 34
rd VCMC VCMC
3 parameter 1 VCOM_TIMES[2:0] - - - _B8 _F8
E3
This command is used to set VCOM Voltage.

VCMC_F[8:0]: Forward scan VCOM voltage control.

VCMC_B[8:0]: Backward scan VCOM voltage control.

VCMC_F[8:0]/VCMC_B[8:0] VCOM
0 0 0 0 0 0 0 0 0 VSSA
0 0 0 0 0 0 0 0 1 -4.00V
0 0 0 0 0 0 0 1 0 -4.00V
0 0 0 0 0 0 0 1 1 -4.00V
0 0 0 0 0 0 1 0 0 -4.00V
0 0 0 0 0 0 1 0 1 -4.00V
0 0 0 0 0 0 1 1 0 -4.00V
0 0 0 0 0 0 1 1 1 -4.00V
0 0 0 0 0 1 0 0 0 -4.00V
0 0 0 0 0 1 0 0 1 -3.99V
0 0 0 0 0 1 0 1 0 -3.98V
Description
0 0 0 0 0 1 0 1 1 -3.97V
: :
1 1 0 0 1 0 1 1 0 -0.02V
1 1 0 0 1 0 1 1 1 -0.01V
1 1 0 0 1 1 0 0 0 VSSA
1 1 0 0 1 1 0 0 1 0.01V
1 1 0 0 1 1 0 1 0 0.02V
1 1 0 0 1 1 0 1 1 0.03V
: :
1 1 1 1 1 1 0 1 0 0.98V
1 1 1 1 1 1 0 1 1 0.99V
1 1 1 1 1 1 1 0 0 1V
1 1 1 1 1 1 1 0 1 1V
1 1 1 1 1 1 1 1 0 1V
1 1 1 1 1 1 1 1 1 HZ

Himax Confidential -P.221-

Himax Confidential -P.222-

SETTE ( Set internal TE function)

B7H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 0 1 1 1 B7
st
1 parameter 1 TEI[3:0] - TEP[10:8] 00
nd
2 parameter 1 TEP[7:0] 00
TEI[3:0]: Set the output interval of TE signal according to the display data rewrite cycle and
data transfer rate.
TEI3 TEI2 TEI1 TEI0 Output Interval
0 0 0 0 1 frame
0 0 0 1 2 frames
0 0 1 0 3 frames
: :
1 1 1 0 15 frames
1 1 1 1 16 frames

TEI[3:0]=0000
V-Sync V-Sync V-Sync V-Sync V-Sync V-Sync V-Sync V-Sync V-Sync

Frame1 Frame2 Frame3 Frame14 Frame15 Frame16 Frame17

TEI[3:0]=0001
V-Sync V-Sync V-Sync V-Sync

Frame1 Frame2 Frame3 Frame14 Frame15 Frame16 Frame17

Description

TEI[3:0]=1111
V-Sync V-Sync

Frame1 Frame2 Frame3 Frame14 Frame15 Frame16 Frame17

TEP[10:0]: Set the output position of frame cycle signal. TE can be used as the trigger
signal for frame synchronous write operation.
Make sure the setting restriction 11’h000 ≤ TEP[10:0] ≤ Numbers of Line-1.

TEP[10:0] Output position

000h 0th line
001h 1st line
002h 2nd line
003h 3rd line
: :
77Fh 1919th line
780h 1920th line
Others Inhibited
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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SETSENSOR ( Set temperature sensor)

B8H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 1 0 0 0 B8
Bank0 TSENS EXT_T
st 1 -
OR_EN
LT_EN HT_EN
PS_EN
TEMP_GAP[2:0] 01
1 parameter
nd L_VG
2 parameter 1 - - L_TEMP[4:0] -
LS2[4]
rd
3 parameter 1 L_SAP1_P[3:0] L_SAP1_N[3:0] -
th
4 parameter 1 L_VGLS2[3:0] L_VGLS[9:8] L_VGHS[9:8] -
h
5 parameter 1 L_VGHS[7:0] -
th
6 parameter 1 L_VGLS[7:0] -
th
7 parameter 1 L_COFF[7:0] -
th
8 parameter 1 L_COFF1[7:0] -
th
9 parameter 1 L_SOFF[7:0] -
th
10 parameter 1 - - - L_VCOM[4:0] -
st H_VG
11 parameter 1 - - H_TEMP[4:0] -
LS2[4]
nd
12 parameter 1 H_SAP1_P[3:0] H_SAP1_N[3:0] -
rd
13 parameter 1 H_VGLS2[3:0] H_VGLS[9:8] H_VGHS[9:8] -
th
14 parameter 1 H_VGHS[7:0] -
h
15 parameter 1 H_VGLS[7:0] -
th
16 parameter 1 H_COFF[7:0] -
th
17 parameter 1 H_COFF1[7:0] -
th
18 parameter 1 H_SOFF[7:0] -
th
19 parameter 1 - - - H_VCOM[4:0] -
REG_A
Bank1
st 1 - - DCOU REG_ADCOUT[4:0] 00
1 parameter T_EN
TSENSOR_EN: Set “1” Enable Temperature sensor function.

LT_EN: Set “1” Enable Low Temperature.

HT_EN: Set “1” Enable High Temperature.

EXT_TPS_EN: “1”:External input pin TH0/TH1 enable.

Description TH1: TH0 Temperature Condition
00 Low Temperature
01 Room Temperature
10 High Temperature
11 High Temperature

TEMP_GAP[2:0]: Temperature GAP.

Himax Confidential -P.224-

H_TEMP[4:0]/L_TEMP[4:0]: High/Low Temp setting.

H_TEMP[4:0]/L_TEMP[4:0] Temperature(ﾟC)
00000 -40
00001 -35.97
00010 -31.94
00011 -27.90
00100 -23.87
00101 -19.84
00110 -15.81
00111 -11.77
01000 -7.74
01001 -3.71
01010 0.32
01011 4.35
01100 8.39
01101 12.42
01110 16.45
01111 20.48
10000 24.51
10001 28.55
10010 32.58
10011 36.61
10100 40.65
10101 44.68
10110 48.71
10111 52.74
11000 56.77
11001 60.81
11010 64.84
11011 68.87
11100 72.90
11101 76.94
11110 80.97
11111 85

H_VGHS[9:0]/L_VGHS[9:0]: High/Low temperature VGH Voltage Setting. Register refer

RB1h VGHS[9:0].

H_VGLS[9:0]/L_VGLS[9:0]: High/Low temperature VGL Voltage Setting. Register refer

RB1h VGLS[9:0].

Himax Confidential -P.225-

H_COFF[7:0]/L_COFF[7:0]: High/Low temperature COFF Setting. Register refer RB4h

COFF[7:0].

H_COFF1[7:0]/L_COFF1[7:0]: High/Low temperature COFF1 Setting. Register refer RB4h

COFF1[7:0].

H_SOFF[7:0]/L_SOFF[7:0]: High/Low temperature SOFF Setting. Register refer RB4h

SOFF[7:0].

H_VCOM[4:0]/L_VCOM[4:0]: High/Low temperature VCOM offset from RT.

H_VCOM[4:0]/L_VCOM[4:0] VCOM offset
00000 0V
00001 -0.01V
00010 -0.02V
00011 -0.03V
00100 -0.04V
00101 -0.05V
00110 -0.06V
00111 -0.07V
01000 -0.08V
01001 -0.09V
01010 -0.1V
01011 -0.11V
01100 -0.12V
01101 -0.13V
01110 -0.14V
01111 -0.15V
10000 0.16V
10001 0.15V
10010 0.14V
10011 0.13V
10100 0.12V
10101 0.11V
10110 0.1V
10111 0.09V
11000 0.08V
11001 0.07V
11010 0.06V
11011 0.05V
11100 0.04V
11101 0.03V
11110 0.02V
11111 0.01V

H_SAP1_P[3:0]/L_SAP1_P[3:0]/ H_SAP1_N[3:0]/L_SAP1_N[3:0]: High/Low temperature

st
1 stage OP bias current adjust. Register refer RB4h SAP1_P[3:0]/ SAP1_N[3:0].

REG_ADCOUT_EN: “1”: user input temperature.

”0”: using internal tepmerature sensor to detect temperature.

REG_ADCOUT[4:0]: User input temperature ADC code.

REG_ADCOUT[4:0
ADC code mapping Temperature(ﾟC)
]
00000 -40
00001 -35.97
00010 -31.94
Himax Confidential -P.226-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
00011 -27.90
00100 -23.87
00101 -19.84
00110 -15.81
00111 -11.77
01000 -7.74
01001 -3.71
01010 0.32
01011 4.35
01100 8.39
01101 12.42
01110 16.45
01111 20.48
10000 24.51
10001 28.55
10010 32.58
10011 36.61
10100 40.65
10101 44.68
10110 48.71
10111 52.74
11000 56.77
11001 60.81
11010 64.84
11011 68.87
11100 72.90
11101 76.94
11110 80.97
11111 85
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.227-

SETEXTC ( Set extended command set)

B9H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 1 0 0 1 B9
st
1 parameter 1 EXTC1[7:0] 00
nd
2 parameter 1 EXTC2[7:0] 00
rd
3 parameter 1 EXTC3[7:0] 00
This command is used to set user define command set access enable.
Extend cmd Command description
After command (B9h), must write 3 parameters (FFh, 83h,
Description Enable
98h) by order
After command(B9h), write 3 parameters (xxh,xxh,xxh) any
Disable(default)
value except (FFh, 83h, 98h)
Restrictions -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.228-

SETMIPI( Set MIPI control)

BAH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 1 0 1 0 BA
st
1 parameter 1 - DSISETUP0[6:0] 63
nd
2 parameter 1 DSISETUP1[7:0] 03
This command is used to set MIPI DSI Related Setting.

Tx Type: Define the LP-TX BTA behavior when there are error.
DSISETUP0[6] 0: only BTA Error
1: BTA Read + Error
CD_disable: Define the contention detection (LP-CD) function.
DSISETUP0[5] 0 : LP-CD function enable
1: LP-CD function disable
Tx_OscDiv: LP-TX clock (TLPX) selection.
DSISETUP0[4] 0 : 50ns (10MHz)(osc_clk)
1 :100ns (5MHz)(osc_clk/2)
DSISETUP0[3:2] vc_main: Define the main function Virtual Channel ID.
LAN_NUM: Define the DSI lane number
00 : 1-lane
DSISETUP0[1:0] 01 : 2-lane
10 : 3-lane
11 : 4-lane
Description
DSISETUP1[7] CRC_enable: Enable RX CRC Check.
ECC_ignore: Define the RX behavior when error occurring.
DSISETUP1[6] 0 : the transmission will be broken when there are ECC or CRC error
1 : the transmission will keep when there are ECC or CRC error
RstTrig: Define the reset trigger function(46h).
DSISETUP1[5] 0 : Disable reset trigger
1 : same as HW_RESET function
DSISETUP1[4] Reserved
Txe_Wait: BTA from Tx into Rx overlap waiting time counter(T TA-GO)
00: TA-go = 2 Tlpx
DSISETUP1[3:2] 01: TA-go = 4 Tlpx
10: TA-go = 6 Tlpx
11: TA-go = 8 Tlpx
Txs_Wait: BTA from Rx into Tx overlap waiting time counter(T TA-GET)
00: Disable, no wait time
DSISETUP1[1:0] 01: TA-get = 2 Tlpx
10: TA-get = 4 Tlpx
11: TA-get = 6 Tlpx
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.229-

SETOTP( Set OTP Related Setting)

BBH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 1 0 1 1 BB
OTP_P
st INTVP OTP_INDEX[9:
1 parameter 1 - ROG_ - - - 00
P_EN ALL 8]
nd
2 parameter 1 OTP_INDEX[7:0] 00
rd
3 parameter 1 OTP_DATA[7:0] 00
OTP_P
th OTP_P OTP_P OTP_T OTP_P
4 parameter 1 OR WE
WR_SE OTP_PTM[2:0] EST ROG
00
L
th
5 parameter 1 OTP_DATA_READ[7:0] -
th
6 parameter 1 OTP_KEY0[7:0] 00
th
7 parameter 1 OTP_KEY1[7:0] 00
This command is used to set OTP related setting.

OTP_KEY0[7:0],
Description Note
OTP_KEY1[7:0]
OTP_KEY0[7:0] = 0xAAh
Enter OTP program mode
OTP_KEY1[7:0] = 0x55h
OTP_KEY0[7:0] = 0x00h
Leave OTP program mode
OTP_KEY1[7:0] = 0x00h
If HX8398-A operate on OTP
program mode, Then keep on OTP
program mode.
Other value Invalid
If HX8398-A operate on non-OTP
program mode, Then keep on
non-OTP program mode.

INTVPP_EN: OTP_PWR power selected.

“0” : External OTP_PWR is selected when programmed.
“1” : Internal OTP_PWR is selected when programmed.

OTP_PROG_ALL: When set to “1’, all OTP index is programmed.

Description

OTP_INDEX[9:0]: Set index of OTP table for programming.

OTP_PROG: When set to “1’, the register content of OTP index is programmed.

OTP_PWR_SEL: When written to “1”, OTP power voltage is fed to OTP circuit.

OTP_PTM[2:0]: For test mode using. Not open..

OTP_PWE: OTP program write enable, “1” means OTP is able to be programmed.

OTP_POR: Pulse for OTP data read operation.

OTP_TEST: “0”, setting OTP_PROG high will trigger internal state machine.
“1”, setting OTP_PROG high will not trigger internal state machine.

OTP_DATA[7:0]: Write data of OTP index.

OTP_DATA_READ[7:0]: Read back the OTP index data.

Restrictions SETEXTC turn on to enable this command.

Himax Confidential -P.230-

Himax Confidential -P.231-

SET_BANK(Set register bank)

BDH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 1 1 1 0 1 BD
st BANK_INDEX
1 parameter 1 - - - - - - 00
[1:0]
Set the register bank for some Commands.

This command is active only for RB1h/RB2h/RB8h/RC1h/RD3h/RD8h.

For example:
Write RC1h Bank1
Step1: write RBDh = 01h
Description
Step2: write RC1h, PA1~42

Read RC1h Bank2

Step1: write RBDh = 02h
Step2: read RC1h, PA1~42

Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.232-

SETDGCLUT ( Set DGC LUT)

C1H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 0 0 0 0 1 C1
Bank0 DGC_
st 1 - - - - - - - 00
1 parameter EN
nd
2 parameter 1 R_GAMMA0[9:2] -
rd
3 parameter 1 R_GAMMA1[9:2] -
th
4 parameter 1 R_GAMMA2[9:2] -
th
5 parameter 1 R_GAMMA3[9:2] -
th
6 parameter 1 R_GAMMA4[9:2] -
th
7 parameter 1 R_GAMMA5[9:2] -
th
8 parameter 1 R_GAMMA6[9:2] -
th
9 parameter 1 R_GAMMA7[9:2] -
th
10 parameter 1 R_GAMMA8[9:2] -
st
11 parameter 1 R_GAMMA9[9:2] -
nd
12 parameter 1 R_GAMMA10[9:2] -
rd
13 parameter 1 R_GAMMA11[9:2] -
th
14 parameter 1 R_GAMMA12[9:2] -
th
15 parameter 1 R_GAMMA13[9:2] -
th
16 parameter 1 R_GAMMA14[9:2] -
th
17 parameter 1 R_GAMMA15[9:2] -
th
18 parameter 1 R_GAMMA16[9:2] -
th
19 parameter 1 R_GAMMA17[9:2] -
th
20 parameter 1 R_GAMMA18[9:2] -
st
21 parameter 1 R_GAMMA19[9:2] -
nd
22 parameter 1 R_GAMMA20[9:2] -
rd
23 parameter 1 R_GAMMA21[9:2] -
th
24 parameter 1 R_GAMMA22[9:2] -
th
25 parameter 1 R_GAMMA23[9:2] -
th
26 parameter 1 R_GAMMA24[9:2] -
th
27 parameter 1 R_GAMMA25[9:2] -
th
28 parameter 1 R_GAMMA26[9:2] -
th
29 parameter 1 R_GAMMA27[9:2] -
th
30 parameter 1 R_GAMMA28[9:2] -
st
31 parameter 1 R_GAMMA29[9:2] -
nd
32 parameter 1 R_GAMMA30[9:2] -
rd
33 parameter 1 R_GAMMA31[9:2] -
th
34 parameter 1 R_GAMMA32[9:2] -
th
35 parameter 1 R_GAMMA0[1:0] R_GAMMA1[1:0] R_GAMMA2[1:0] R_GAMMA3[1:0] -
th
36 parameter 1 R_GAMMA4[1:0] R_GAMMA5[1:0] R_GAMMA6[1:0] R_GAMMA7[1:0] -
th
37 parameter 1 R_GAMMA8[1:0] R_GAMMA9[1:0] R_GAMMA10[1:0] R_GAMMA11[1:0] -
th
38 parameter 1 R_GAMMA12[1:0] R_GAMMA13[1:0] R_GAMMA14[1:0] R_GAMMA15[1:0] -
th
39 parameter 1 R_GAMMA16[1:0] R_GAMMA17[1:0] R_GAMMA18[1:0] R_GAMMA19[1:0] -
th
40 parameter 1 R_GAMMA20[1:0] R_GAMMA21[1:0] R_GAMMA22[1:0] R_GAMMA23[1:0] -
st
41 parameter 1 R_GAMMA24[1:0] R_GAMMA25[1:0] R_GAMMA26[1:0] R_GAMMA27[1:0] -
nd
42 parameter 1 R_GAMMA28[1:0] R_GAMMA29[1:0] R_GAMMA30[1:0] R_GAMMA31[1:0] -
rd
43 parameter 1 R_GAMMA32[1:0] - - - - - - -
Bank1
st 1 G_GAMMA0[9:2] -
1 parameter
Himax Confidential -P.233-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
nd
2 parameter 1 G_GAMMA1[9:2] -
rd
3 parameter 1 G_GAMMA2[9:2] -
th
4 parameter 1 G_GAMMA3[9:2] -
th
5 parameter 1 G_GAMMA4[9:2] -
th
6 parameter 1 G_GAMMA5[9:2] -
th
7 parameter 1 G_GAMMA6[9:2] -
th
8 parameter 1 G_GAMMA7[9:2] -
th
9 parameter 1 G_GAMMA8[9:2] -
th
10 parameter 1 G_GAMMA9[9:2] -
st
11 parameter 1 G_GAMMA10[9:2] -
nd
12 parameter 1 G_GAMMA11[9:2] -
rd
13 parameter 1 G_GAMMA12[9:2] -
th
14 parameter 1 G_GAMMA13[9:2] -
th
15 parameter 1 G_GAMMA14[9:2] -
th
16 parameter 1 G_GAMMA15[9:2] -
th
17 parameter 1 G_GAMMA16[9:2] -
th
18 parameter 1 G_GAMMA17[9:2] -
th
19 parameter 1 G_GAMMA18[9:2] -
th
20 parameter 1 G_GAMMA19[9:2] -
st
21 parameter 1 G_GAMMA20[9:2] -
nd
22 parameter 1 G_GAMMA21[9:2] -
rd
23 parameter 1 G_GAMMA22[9:2] -
th
24 parameter 1 G_GAMMA23[9:2] -
th
25 parameter 1 G_GAMMA24[9:2] -
th
26 parameter 1 G_GAMMA25[9:2] -
th
27 parameter 1 G_GAMMA26[9:2] -
th
28 parameter 1 G_GAMMA27[9:2] -
th
29 parameter 1 G_GAMMA28[9:2] -
th
30 parameter 1 G_GAMMA29[9:2] -
st
31 parameter 1 G_GAMMA30[9:2] -
nd
32 parameter 1 G_GAMMA31[9:2] -
rd
33 parameter 1 G_GAMMA32[9:2] -
th
34 parameter 1 G_GAMMA0[1:0] G_GAMMA1[1:0] G_GAMMA2[1:0] G_GAMMA3[1:0] -
th
35 parameter 1 G_GAMMA4[1:0] G_GAMMA5[1:0] G_GAMMA6[1:0] G_GAMMA7[1:0] -
th
36 parameter 1 G_GAMMA8[1:0] G_GAMMA9[1:0] G_GAMMA10[1:0] G_GAMMA11[1:0] -
th
37 parameter 1 G_GAMMA12[1:0] G_GAMMA13[1:0] G_GAMMA14[1:0] G_GAMMA15[1:0] -
th
38 parameter 1 G_GAMMA16[1:0] G_GAMMA17[1:0] G_GAMMA18[1:0] G_GAMMA19[1:0] -
th
39 parameter 1 G_GAMMA20[1:0] G_GAMMA21[1:0] G_GAMMA22[1:0] G_GAMMA23[1:0] -
th
40 parameter 1 G_GAMMA24[1:0] G_GAMMA25[1:0] G_GAMMA26[1:0] G_GAMMA27[1:0] -
st
41 parameter 1 G_GAMMA28[1:0] G_GAMMA29[1:0] G_GAMMA30[1:0] G_GAMMA31[1:0] -
nd
42 parameter 1 G_GAMMA32[1:0] - - - - - - -
Bank2
st 1 G_GAMMA0[9:2] -
1 parameter
nd
2 parameter 1 G_GAMMA1[9:2] -
rd
3 parameter 1 G_GAMMA2[9:2] -
th
4 parameter 1 G_GAMMA3[9:2] -
th
5 parameter 1 G_GAMMA4[9:2] -
th
6 parameter 1 G_GAMMA5[9:2] -
th
7 parameter 1 G_GAMMA6[9:2] -
th
8 parameter 1 G_GAMMA7[9:2] -

Himax Confidential -P.234-

DGC_EN: Enable the DGC function. “1”: Enable; “0”: Disable.

R/G/B_GAMMA0[9:0] ~ R/G/B_GAMMA32[9:0]: MSB 8-bit is setting to mapping related

gary level to which gray level voltage of real gamma. LSB 2-bit is for dithering.
LUT Mapping Gray level
R_GAMMA0[9:0] R0
R_GAMMA1[9:0] R8
Description R_GAMMA2[9:0] R16
: :
R_GAMMA31[9:0] R240
R_GAMMA32[9:0] R255
G_GAMMA0[9:0] G0
G_GAMMA1[9:0] G8
G_GAMMA2[9:0] G16
: :
G_GAMMA31[9:0] G240
G_GAMMA32[9:0] G255
Himax Confidential -P.235-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
B_GAMMA0[9:0] B0
B_GAMMA1[9:0] B8
B_GAMMA2[9:0] B16
: :
B_GAMMA31[9:0] B240
B_GAMMA32[9:0] B255
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.236-

SETID ( Set ID)

C3H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 0 0 0 1 1 C3
st
1 parameter 1 ID1[7:0] 83
nd
2 parameter 1 ID2[7:0] 98
rd
3 parameter 1 ID3[7:0] 0A
th
4 parameter 1 ID4[7:0] 00
th
5 parameter 1 ID_TIMES[2:0] - - - - - E0
ID1[7:0] is used to set ID RDAh value.

ID2[7:0] is used to set ID RDBh value.

ID3[7:0] is used to set ID RDCh value.

ID4[7:0] is used to set the fourth ID.

Description
ID_TIMES[2:0]: Read the ID OTP programmed times.
ID_TIMES[2:0] ID OTP Programmed Times
111 No programmed
011 ID has been programmed 1 time
001 ID has been programmed 2 times
000 ID has been programmed 3 times

Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.237-

SETDDB ( Set DDB)

C4H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 0 0 1 0 0 C4
st
1 parameter 1 DDB1[7:0] 00
nd
2 parameter 1 DDB2[7:0] 00
rd
3 parameter 1 DDB3[7:0] 00
th
4 parameter 1 DDB4[7:0] 00
Description This command is used to set CMD RA1h DDB1~4 value.
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.238-

SETCABC (Set CABC Control)

C9H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 0 1 0 0 1 C9
PWM_
st EN_DI INVPU SEL_BL
1 Parameter 1 - SEL_PWMCLK[2:0] PERIO
M_MIX LS DUTY 17
D[16]
nd
2 Parameter 1 PWM_PERIOD[15:8] 00
rd
3 Parameter 1 PWM_PERIOD[7:0] 2E
This command is used to set CABC parameter.

SEL_BLDUTY: Backlight PWM output duty on/off control when CABC operation.
‘0’, The Backligh pwm output duty is 100%.
‘1’, The Backligh pwm output duty is calculate from CABC operation..

INVPULS: The backlight PWM output polarity select.

‘0’, The backlight PWM output is low level active.
‘1’, The backlight PWM output is high level active.

EN_DIM_MIX: Data gain dimming function

([Link] off to on [Link] switch at CABC on)
1: Dimming enable 0: Dimming disable

SEL_PWMCLK[2:0] : Internal PWM_CLK divider for CABC clock.

SEL_PWMCLK[2:0] Brightness Control Clock frequency
0 0 0 PWM_CLK / 1
0 0 1 PWM_CLK / 2
0 1 0 PWM_CLK / 4
0 1 1 PWM_CLK / 6
1 0 0 PWM_CLK / 8
1 0 1 PWM_CLK / 10
1 1 0 PWM_CLK / 12
1 1 1 PWM_CLK / 14
Description
PWM_PERIOD[16:0]: The backlight PWM output period setting.

When PWM_PERIOD[16]=0, PWM_PERIOD[15:6] setting inhibited.

If PWM_PERIOD[16]=0 and SEL_PWMCLK[2:0]=3’[Link] PWM_CLK frequency
mapping table is as bellows:

PWM_PERIOD[5:0] PWM_CLK
00h 40KHz
01h 39KHz
02h 38KHz
03h 37KHz
04h 36KHz
05h 35KHz
06h 34KHz
07h 33KHz
08h 32KHz
09h 31KHz
0Ah 30KHz
0Bh 29KHz
0Ch 28KHz
0Dh 27KHz
0Eh 26KHz
0Fh 25KHz

Himax Confidential -P.239-

When PWM_PERIOD[16]=1:
CABC_PWM_OUT frequency= (Fosc/4) / (SEL_PWMCLK[2:0]+1) / (PWM_PERIOD[15:0])
Note: PWM_PERIOD[15:0]=0000h is inhibited.

Restriction SETEXTC turn on to enable this command.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.240-

SETPANEL( Set panel related register)

CCH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 0 1 1 0 0 CC
st SS_P GS_P REV_P BGR_P
1 parameter 1 - - - - ANEL ANEL
00
ANEL ANEL
This command is used to set setting of panel related register and make panel module meets
below spec from viewpoint of user

BGR_PANEL: The order of <R><G> dot color for module supplier, default value is stored
in OTP. If color filter of panel is <G><R> type, setting BGR_PANEL = 1, if color filter of
panel is <R><G> type, setting BGR_PANEL = 0. This bit is to make panel module look
like a <R><G> type panel form the user viewpoint.

REV_PANEL: The REV_PANEL setting is used to select the inversion of the display of all
Description0 characters and graphics. This setting allows the display of the same data on both normally
white and normally black panels.

GS_PANEL: Specify the shift direction of gate driver output.

When GS_PANEL = 0, the panel control signal is normal scan.
When GS_PANEL = 1, the panel control signal is reverse scan.

SS_PANEL: Specify the shift direction of source driver output. When SS_PANEL = 0, the
shift direction from S1 to S3240 When SS_PANEL = 1, the shift direction from S3240 to S1.

Restrictions SETEXTC turn on to enable this command

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.241-

SETOFFSET
D2H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 0 0 1 0 D2
st
1 parameter 1 VN_REFS[3:0] VP_REFS[3:0] 55
This command is used for reference voltage setting.

VP_REFS[3:0]: Positive reference voltage VP_REF setting.

VP_REFS[3:0] VP_REF Voltage
0 0 0 0 4.0V
0 0 0 1 4.3V
0 0 1 0 4.5V
0 0 1 1 4.6V
0 1 0 0 4.7V
0 1 0 1 4.8V
0 1 1 0 4.9V
0 1 1 1 5.0V
1 0 0 0 5.1V
1 0 0 1 5.2V
1 0 1 0 5.3V
1 0 1 1 5.4V
1 1 0 0 5.5V
1 1 0 1 5.6V
1 1 1 0 5.8V
Description 1 1 1 1 6.1V

VN_REFS[3:0]: Negative reference voltage VN_REF setting.

VN_REFS[3:0] VN_REF Voltage
0 0 0 0 -4.0V
0 0 0 1 -4.3V
0 0 1 0 -4.5V
0 0 1 1 -4.6V
0 1 0 0 -4.7V
0 1 0 1 -4.8V
0 1 1 0 -4.9V
0 1 1 1 -5.0V
1 0 0 0 -5.1V
1 0 0 1 -5.2V
1 0 1 0 -5.3V
1 0 1 1 -5.4V
1 1 0 0 -5.5V
1 1 0 1 -5.6V
1 1 1 0 -5.8V
1 1 1 1 -6.1V
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.242-

SETGIP0(Set GIP Option0)

D3H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 0 0 1 1 D3
Bank0 GIP_M EQ_DELAY_HS
st 1 - - ODE[1]
- - - 00
1 parameter YNC[1:0]
nd
2 parameter 1 - - -
- - - EQ_DISC[1:0] 00
rd
3 parameter 1 EQ_DELAY_ON1[7:0] 00
th
4 parameter 1 EQ_DELAY_ON2[7:0] 00
th
5 parameter 1 EQ_DELAY_OFF1[7:0] 00
th
6 parameter 1 EQ_DELAY_OFF2[7:0] 00
th
7 parameter 1 GTO[7:0] 00
th
8 parameter 1 GNO[7:0] 00
th
9 parameter 1 USER_GIP_GATE[7:0] 08
th
10 parameter 1 USER_GIP_GATE1[7:0] 08
st
11 parameter SHR0_3[3:0] SHR0_2[3:0] 32
nd
12 parameter 1 SHR0_1[3:0] SHR0[11:8] 10
rd
13 parameter 1 SHR0[7:0] 02
th
14 parameter 1 - - - - SHR0_GS[11:8] 00
th
15 parameter 1 SHR0_GS[7:0] 02
th
16 parameter 1 SHR1_3[3:0] SHR1_2[3:0] 32
th
17 parameter 1 SHR1_1[3:0] SHR1[11:8] 13
th
18 parameter 1 SHR1[7:0] C0
th
19 parameter 1 - - - - SHR1_GS[11:8] 00
th
20 parameter 1 SHR1_GS[7:0] 00
st
21 parameter 1 SHR2_3[3:0] SHR2_2[3:0] 32
nd
22 parameter 1 SHR2_1[3:0] SHR2[11:8] 10
rd
23 parameter 1 SHR2[7:0] 08
th
24 parameter 1 - - - - SHR2_GS[11:8] 00
th
25 parameter 1 SHR2_GS[7:0] 00
th
26 parameter 1 SHP[3:0] SCP[3:0] 4B
th
27 parameter 1 SHP2[3:0] SHP1[3:0] 00
th
28 parameter 1 CHR0[7:0] 06
th
29 parameter 1 CHR0_GS[7:0] 06
th
30 parameter 1 CHP0[3:0] CCP0[3:0] 47
st
31 parameter 1 CHR1[7:0] 04
nd
32 parameter 1 CHR1_GS[7:0] 00
rd
33 parameter 1 CHP1[3:0] CCP1[3:0] 27
th
34 parameter 1 vbp_setting[7:0] 00
vbp_s OVER
th
35 parameter 1 - elf_lea LAP_ - DCHG1R[1:0] DCHG2R[1:0] 00
rning OPT
This command is used for GIP signal setting.

GIP_MODE[1]: GIP state at Sleep in mode

GIP_MODE[1] GIP state at Sleep in mode
0 GND
1 VGL

Description EQ_DELAY_ON1[7:0] / EQ_DELAY_ON2[7:0] / EQ_DELAY_OFF1[7:0] /

EQ_DELAY_OFF2[7:0]: Set GIP control signal EQ period.
(1 TCON CLK period = 1/22MHz)
EQ_DELAY_ON1[7:0] / EQ_DELAY_ON2[7:0] /
GIP EQ Period
EQ_DELAY_OFF1[7:0] / EQ_DELAY_OFF2[7:0]
0 0 0 0 0 0 0 0 Inhibited
0 0 0 0 0 0 0 1 1 TCON clock cycle
0 0 0 0 0 0 1 0 2 TCON clock cycle
Himax Confidential -P.243-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
0 0 0 0 0 0 1 1 3 TCON clock cycle
: :
1 1 1 1 1 1 0 1 253 TCON clock cycle
1 1 1 1 1 1 1 0 254 TCON clock cycle
1 1 1 1 1 1 1 1 255 TCON clock cycle

EQ_DEALY_ON1 EQ_DEALY_OFF1

VGH

VSP

VSSA

VSN

VGL
SPONEQ_DEALY_ON2 SPOFFEQ_DEALY_OFF2
/CON /COFF

EQ_DELAY_HSYNC[1:0]: Set the EQ period in HSYNC width.

EQ_DELAY_HSYNC[1:0] EQ Period in HSYNC width
0 0 Normal Driving
0 1 1 x Hsync
1 0 2 x Hsync
1 1 3 x Hsync

VGH

VSSA

VGL
Full Driving

VGH

VSSA

VGL

Driving 1-HSYNC, others EQ VSSA

VGH

VSSA

VGL

Driving 2-HSYNC, others EQ VSSA

VGH

VSSA

VGL

Driving 3-HSYNC, others EQ VSSA

EQ_DISC[1:0]: GIP EQ GND slew rate option.

EQ_DISC[1:0] GIP EQ GND Ability
00 Strong

Himax Confidential -P.244-

OVERLAP_OPT: Choose GPWR over lap type.

When set ‘1’, GPWR low period longer then high period.
When set ‘0’, GPWR high period longer then low period.

GTO[7:0]: GPWR signal toggle frequency.

GTO[7:0] GPWR toggle frequency
6’h00 256 x Frame/Line
6’h01 1 x Frame/ Line
6’h02 2 x Frame/ Line
6’h03 3 x Frame/ Line
: :
6’h3D 253 x Frame/ Line
6’h3E 254 x Frame/ Line
6’h3F 255 x Frame/ Line

GNO[7:0]: GPWR signal non-overlap timing.

GNO[7:0] GPWR non-overlap timing
8’h00 0
8’h01 1 TCON clock cycle
8’h02 2 TCON clock cycle
8’h03 3 TCON clock cycle
: :
8’hFD 253 TCON clock cycle
8’hFE 254 TCON clock cycle
8’hFF 255 TCON clock cycle
GPWR1/2 toggle period by Frame or Line depend on GIP_OPT[4]. Non-overlap time
depends on GNO.

GPWR1/2 non-overlap signal are as below:

Vsync/
Hsync

GNO GNO GNO

GPWR1_L/R

GPWR2_L/R

GTO GTO

GPWR1/2 overlap signal are as below:

Himax Confidential -P.245-

Vsync/
Hsync

GPWR1_L/R
GTO GTO

GNO GNO GNO

GPWR2_L/R

GPWR1/2 : one-side non-overlap , one-side in the same edge as below

(when set OVERLAP_OPT=1)

Vsync/
Hsync

GNO GNO GNO

GPWR1_L/R

GPWR2_L/R

GTO GTO

USER_GIP_Gate[7:0]: Set the GIP dummy clock numbers for first CKV.
USER_GIP_Gate1[7:0]: Set the GIP dummy clock numbers for second CKV.

VSYNC

HSYNC

vbp_setting[7:0]
DE

2 Lines

Source ouput
Source Ouput at third DE signal

SPOFF[7:0]
SPON[7:0]
SHRn[11:0]
Start1
SHP[3:0] define the width of high pulse

End1 SHRn[11:0]

COFF[7:0]
CON[7:0]
CHRn[7:0]
Clock1
CHP[3:0] define the width of high pulse

Clock2

Group0:
st
SHR0[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=0.
st
SHR0_GS[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=1.
nd rd th st
SHR0_1 / SHR0_2 / SHR0_3[3:0]:Set the 2 /3 /4 Start / End signal delay from the 1
Start/End signal.
Himax Confidential -P.246-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04

Group1:
st
SHR1[11:0]: Set the 1 Start/End siganl delay from VSYNC falling edge when GS=0.
st
SHR1_GS[11:0]: Set the 1 Start/End siganl delay from VSYNC falling edge when GS=1.
nd rd th st
SHR1_1 / SHR1_2 / SHR1_3[3:0]: Set the 2 /3 /4 Start / End signal delay from the 1
Start/End signal.

Group2:
st
SHR2[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=0.
st
SHR2_GS[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=1.
nd rd th st
SHR2_1 / SHR2_2 / SHR2_3[3:0]: Set the 2 /3 /4 Start / End signal delay from the 1
Start/End signal.

SHR0/SHR1/SHR2[11:0]
Start signal output delay
SHR0_GS/SHR1_GS/SHR2_GS[11:0]
0x000h 2 x Hsync
0x001h 3 x Hsync
0x002h 4 x Hsync
: :
0xFFEh 4096 x Hsync
0xFFFh 4097 x Hsync

SHR0_1 / SHR1_1 / SHR2_1[3:0] 2nd Start / End signal output delay

SHR0_2 / SHR1_2 / SHR2_2[3:0] 3th Start / End signal output delay
SHR0_3 / SHR1_3 / SHR2_3[3:0] 4th Start / End signal output delay
0000 0 x Hsync
0001 1 x Hsync
0010 2 x Hsync
: :
1110 14 x Hsync
1111 15 x Hsync

SCP[3:0]: Numbers of output Start and End signal.

SCP3 SCP2 SCP1 SCP0 Start and End numbers
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
: :
1 1 0 1 14
1 1 1 0 15
1 1 1 1 16

SHP0/1/2[3:0]: Width of Start and End signal high pulse.

SHP3 SHP2 SHP1 SHP0 Start Pulse Width
0 0 0 0 1 x Hsync
0 0 0 1 2 x Hsync
0 0 1 0 3 x Hsync
: :
1 1 1 0 15 x Hsync
1 1 1 1 16 x Hsync

CHR0[7:0]/CHR1[7:0]: Set the Clock signal delay from VSYNC falling edge when GS=0.
CHR0_GS[7:0]/CHR1_GS[7:0]: Set the Clock signal delay from VSYNC falling edge when
GS=1.
CHR0[7:0]/CHR0_GS[7:0] Clock signal output delay
CHR1[7:0]/CHR1_GS[7:0]
0x00h 2 x HSYNC
0x01h 3 x HSYNC
Himax Confidential -P.247-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
0x02h 4 x HSYNC
: :
0xFEh 256 x HSYNC
0xFFh 257 x HSYNC

CCP0[3:0]/CCP1[3:0]: Numbers of Output Clock signal.

CCP0[3:0]/CCP1[3:0] Clock nunbers
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
: :
1 1 1 0 15
1 1 1 1 16

CHP0[3:0]/CHP1[3:0]: Width of Clock signal high pulse.

CHP0[3:0]/CHP1[3:0] Clock signal width
0 0 0 0 1 x Hsync
0 0 0 1 2 x Hsync
0 0 1 0 3 x Hsync
: :
1 1 1 0 15 x Hsync
1 1 1 1 16 x Hsync

vbp_setting[7:0]: Set Vertical porch lines(from VSYNC falling to first DE signal).

vbp_setting [7:0] Vertical porch lines
0x00h 1 x HSYNC
0x01h 2 x HSYNC
0x02h 3 x HSYNC
: :
0xFEh 255 x HSYNC
0xFFh 256 x HSYNC

vbp_self_learning: Set ‘1’ to enable self-learning.

DCHG1R[1:0]: Dischage impedence selection for VGH1

DCHG1R[1:0] Discharge resistance
External resistance
0 0
(connect to VGH1_RGND)
0 1 1K ohm
1 0 2K ohm
1 1 4K ohm

DCHG2R[1:0]: Dischage impedence selection for VGH2

DCHG2R[1:0] Discharge resistance
External resistance
0 0
(connect to VGH2_RGND)
0 1 10K ohm
1 0 20K ohm
1 1 40K ohm
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.248-

SETGIP1(Set GIP Option1)

D5H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 0 1 0 1 D5
st CGTS_L_
1 parameter 1 - INV[1] COS1_L[5:0] 18
nd CGTS_R
2 parameter 1 - _INV[1] COS1_R[5:0] 18
rd CGTS_L_
3 parameter 1 - INV[2] COS2_L[5:0] 18
th CGTS_R
4 parameter 1 - _INV[2] COS2_R[5:0] 18
th CGTS_L_
5 parameter 1 - INV[3] COS3_L[5:0] 18
th CGTS_R
6 parameter 1 - _INV[3] COS3_R[5:0] 18
th CGTS_L_
7 parameter 1 - INV[4] COS4_L[5:0] 18
th CGTS_R
8 parameter 1 - _INV[4] COS4_R[5:0] 18
th CGTS_L_
9 parameter 1 - INV[5] COS5_L[5:0] 18
th CGTS_R
10 parameter 1 - _INV[5] COS5_R[5:0] 18
st CGTS_L_
11 parameter 1 - INV[6] COS6_L[5:0] 18
nd CGTS_R
12 parameter 1 - _INV[6] COS6_R[5:0] 18
rd CGTS_L_
13 parameter 1 - INV[7] COS7_L[5:0] 18
th CGTS_R
14 parameter 1 - _INV[7] COS7_R[5:0 18
th CGTS_L_
15 parameter 1 - INV[8] COS8_L[5:0] 18
th CGTS_R
16 parameter 1 - _INV[8] COS8_R[5:0] 18
th CGTS_L_
17 parameter 1 - COS9_L[5:0] 18
INV[9]
th CGTS_R
18 parameter 1 - _INV[9] COS9_R[5:0] 18
th CGTS_L_
19 parameter 1 - INV[10] COS10_L[5:0] 18
th CGTS_R
20 parameter 1 - COS10_R[5:0] 18
_INV[10]
st CGTS_L_
21 parameter 1 - INV[11] COS11_L[5:0] 18
nd CGTS_R
22 parameter 1 - _INV[11] COS11_R[5:0] 18
rd CGTS_L_
23 parameter 1 - INV[12] COS12_L[5:0] 18
th CGTS_R
24 parameter 1 - _INV[12] COS12_R[5:0] 18
th CGTS_L_
25 parameter 1 - COS13_L[5:0] 18
INV[13]
th CGTS_R
26 parameter 1 - _INV[13] COS13_R[5:0] 18
th CGTS_L_
27 parameter 1 - COS14_L[5:0] 18
INV[14]
th CGTS_R
28 parameter 1 - _INV[14] COS14_R[5:0] 18
th CGTS_L_
29 parameter 1 - INV[15] COS15_L[5:0] 18
th CGTS_R
30 parameter 1 - COS15_R[5:0] 18
_INV[15]
st CGTS_L_
31 parameter 1 - INV[16] COS16_L[5:0] 18
nd CGTS_R
32 parameter 1 - _INV[16] COS16_R[5:0] 18
rd CGTS_L_
33 parameter 1 - INV[17] COS17_L[5:0] 18
th CGTS_R
34 parameter 1 - _INV[17] COS17_R[5:0] 18
th CGTS_L_
35 parameter 1 - COS18_L[5:0] 18
INV[18]
th CGTS_R
36 parameter 1 - _INV[18] COS18_R[5:0] 18
th CGTS_L_
37 parameter 1 - COS19_L[5:0] 18
INV[19]
th CGTS_R
38 parameter 1 - _INV[19] COS19_R[5:0] 18

Himax Confidential -P.249-

COSn_L_GS[3:0]: When GS_Panel=1, select CGOUTL_n output, n=1~20

COSn_R_GS[3:0]: When GS_Panel=1, select CGOUTR_n output, n=1~20

COSn_L[5:0]~
COSn_R[5:0]~ Output Signal Description
n=1~20
00_0000 CK[0] GROUP0:Gate CLK
00_0001 CK[1] Gate CLK
00_0010 CK[2] Gate CLK
00_0011 CK[3] Gate CLK
00_0100 CK[4] Gate CLK
00_0101 CK[5] Gate CLK
00_0110 CK[6] Gate CLK
00_0111 CK[7] Gate CLK
00_1000 CK[8] Gate CLK
00_1001 CK[9] Gate CLK
00_1010 CK[10] Gate CLK
00_1011 CK[11] Gate CLK
00_1100 CK[12] Gate CLK
00_1101 CK[13] Gate CLK
00_1110 CK[14] Gate CLK
00_1111 CK[15] Gate CLK
Description 01_0000 CK_1[0] GROUP1:Gate CLK
01_0001 CK_1 [1] Gate CLK
01_0010 CK_1 [2] Gate CLK
01_0011 CK_1 [3] Gate CLK
01_0100 CK_1 [4] Gate CLK
01_0101 CK_1 [5] Gate CLK
01_0110 CK_1 [6] Gate CLK
01_0111 CK_1 [7] Gate CLK
01_1000 1'b0 VGL
01_1001 1'b1 VGH
01_1010 GPWR1 Frame or Line toggle signal GPWR1
01_1011 GPWR2 Frame or Line toggle signal GPWR2
When GS=0, output VGH.
01_1110 DIR
When GS=1, output VGL.
When GS=0, output VGL.
01_1111 DIRB
When GS=1, output VGH.
10_0000 STV[0] GROUP 0 SHR0[11:0]
10_0001 STV[1] SHR0[11:0]+SHR0_1[3:0]
10_0010 STV[2] SHR0[11:0]+SHR0_2[3:0]
10_0011 STV[3] SHR0[11:0]+SHR0_3[3:0]
10_0100 STV[4] GROUP 1 SHR1[11:0]
10_0101 STV[5] SHR1[11:0]+SHR1_1[3:0]
10_0110 STV[6] SHR1[11:0]+SHR1_2[3:0]
10_0111 STV[7] SHR1[11:0]+SHR1_3[3:0]
10_1000 STV[8] GROUP-2 SHR2[11:0]
10_1001 STV[9] SHR2[11:0]+SHR2_1[3:0]

Himax Confidential -P.250-

Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.251-

SETGIP2(Set GIP Option2)

D6H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 0 1 1 0 D6
CGOUT_
st
1 parameter 1 - L_HIZ_IN COS1_L_GS[5:0] 18
[1]
CGOUT_
nd
2 parameter 1 - R_HIZ_IN COS1_R_GS[5:0] 18
[1]
CGOUT_
rd
3 parameter 1 - L_HIZ_IN COS2_L_GS[5:0] 18
[2]
CGOUT_
th
4 parameter 1 - R_HIZ_IN COS2_R_GS[5:0] 18
[2]
CGOUT_
th
5 parameter 1 - L_HIZ_IN COS3_L_GS[5:0] 18
[3]
CGOUT_
th
6 parameter 1 - R_HIZ_IN COS3_R_GS[5:0] 18
[3]
CGOUT_
th
7 parameter 1 - L_HIZ_IN COS4_L_GS[5:0] 18
[4]
CGOUT_
th
8 parameter 1 - R_HIZ_IN COS4_R_GS[5:0] 18
[4]
CGOUT_
th
9 parameter 1 - L_HIZ_IN COS5_L_GS[5:0] 18
[5]
CGOUT_
th
10 parameter 1 - R_HIZ_IN COS5_R_GS[5:0] 18
[5]
CGOUT_
st
11 parameter 1 - L_HIZ_IN COS6_L_GS[5:0] 18
[6]
CGOUT_
nd
12 parameter 1 - R_HIZ_IN COS6_R_GS[5:0] 18
[6]
CGOUT_
rd
13 parameter 1 - L_HIZ_IN COS7_L_GS[5:0] 18
[7]
CGOUT_
th
14 parameter 1 - R_HIZ_IN COS7_R_GS[5:0] 18
[7]
CGOUT_
th
15 parameter 1 - L_HIZ_IN COS8_L_GS[5:0] 18
[8]
CGOUT_
th
16 parameter 1 - R_HIZ_IN COS8_R_GS[5:0] 18
[8]
th CGOUT_
17 parameter
1 - L_HIZ_IN COS9_L_GS[5:0] 18
[9]
CGOUT_
th
18 parameter 1 - R_HIZ_IN COS9_R_GS[5:0] 18
[9]
CGOUT_
th
19 parameter 1 - L_HIZ_IN COS10_L_GS[5:0] 18
[10]
th CGOUT_
20 parameter
1 - R_HIZ_IN COS10_R_GS[5:0] 18
[10]
CGOUT_
st
21 parameter 1 - L_HIZ_IN COS11_L_GS[5:0] 18
[11]
CGOUT_
nd
22 parameter 1 - R_HIZ_IN COS11_R_GS[5:0] 18
[11]
CGOUT_
rd
23 parameter 1 - L_HIZ_IN COS12_L_GS[5:0] 18
[12]
CGOUT_
th
24 parameter 1 - R_HIZ_IN COS12_R_GS[5:0] 18
[12]
th CGOUT_
25 parameter
1 - L_HIZ_IN COS13_L_GS[5:0] 18
[13]
CGOUT_
th
26 parameter 1 - R_HIZ_IN COS13_R_GS[5:0] 18
[13]
Himax Confidential -P.252-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
th CGOUT_
27 parameter
1 - L_HIZ_IN COS14_L_GS[5:0] 18
[14]
CGOUT_
th
28 parameter 1 - R_HIZ_IN COS14_R_GS[5:0] 18
[14]
CGOUT_
th
29 parameter 1 - L_HIZ_IN COS15_L_GS[5:0] 18
[15]
th CGOUT_
30 parameter
1 - R_HIZ_IN COS15_R_GS[5:0] 18
[15]
CGOUT_
st
31 parameter 1 - L_HIZ_IN COS16_L_GS[5:0] 18
[16]
CGOUT_
nd
32 parameter 1 - R_HIZ_IN COS16_R_GS[5:0] 18
[16]
CGOUT_
rd
33 parameter 1 - L_HIZ_IN COS17_L_GS[5:0] 18
[17]
CGOUT_
th
34 parameter 1 - R_HIZ_IN COS17_R_GS[5:0] 18
[17]
th CGOUT_
35 parameter
1 - L_HIZ_IN COS18_L_GS[5:0] 18
[18]
CGOUT_
th
36 parameter 1 - R_HIZ_IN COS18_R_GS[5:0] 18
[18]
th CGOUT_
37 parameter
1 - L_HIZ_IN COS19_L_GS[5:0] 18
[19]
CGOUT_
th
38 parameter 1 - R_HIZ_IN COS19_R_GS[5:0] 18
[19]
CGOUT_
th
49 parameter 1 - L_HIZ_IN COS20_L_GS[5:0] 18
[20]
th CGOUT_
40 parameter
1 - R_HIZ_IN COS20_R_GS[5:0] 18
[20]
CGOUT_L_HIZ_IN[n]: Set the CGOUTL_n output = Hi-Z, n=1~20
CGOUT_R_HIZ_IN[n]: Set the CGOUTR_n output = Hi-Z, n=1~20
0: Normal output
1: Hi-Z

COSn_L_GS[3:0]: When GS_Panel=1, select CGOUTL_n output, n=1~20

COSn_R_GS[3:0]: When GS_Panel=1, select CGOUTR_n output, n=1~20

COSn_L[5:0]~
COSn_R[5:0]~ Output Signal Description
n=1~20
00_0000 CK[0] GROUP0:Gate CLK
00_0001 CK[1] Gate CLK
00_0010 CK[2] Gate CLK
Description 00_0011 CK[3] Gate CLK
00_0100 CK[4] Gate CLK
00_0101 CK[5] Gate CLK
00_0110 CK[6] Gate CLK
00_0111 CK[7] Gate CLK
00_1000 CK[8] Gate CLK
00_1001 CK[9] Gate CLK
00_1010 CK[10] Gate CLK
00_1011 CK[11] Gate CLK
00_1100 CK[12] Gate CLK
00_1101 CK[13] Gate CLK
00_1110 CK[14] Gate CLK
00_1111 CK[15] Gate CLK
01_0000 CK_1[0] GROUP1:Gate CLK
01_0001 CK_1 [1] Gate CLK
Himax Confidential -P.253-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
01_0010 CK_1 [2] Gate CLK
01_0011 CK_1 [3] Gate CLK
01_0100 CK_1 [4] Gate CLK
01_0101 CK_1 [5] Gate CLK
01_0110 CK_1 [6] Gate CLK
01_0111 CK_1 [7] Gate CLK
01_1000 1'b0 VGL
01_1001 1'b1 VGH
01_1010 GPWR1 Frame or Line toggle signal GPWR1
01_1011 GPWR2 Frame or Line toggle signal GPWR2
When GS=0, output VGH.
01_1110 DIR
When GS=1, output VGL.
When GS=0, output VGL.
01_1111 DIRB
When GS=1, output VGH.
10_0000 STV[0] GROUP 0 SHR0[11:0]
10_0001 STV[1] SHR0[11:0]+SHR0_1[3:0]
10_0010 STV[2] SHR0[11:0]+SHR0_2[3:0]
10_0011 STV[3] SHR0[11:0]+SHR0_3[3:0]
10_0100 STV[4] GROUP 1 SHR1[11:0]
10_0101 STV[5] SHR1[11:0]+SHR1_1[3:0]
10_0110 STV[6] SHR1[11:0]+SHR1_2[3:0]
10_0111 STV[7] SHR1[11:0]+SHR1_3[3:0]
10_1000 STV[8] GROUP-2 SHR2[11:0]
10_1001 STV[9] SHR2[11:0]+SHR2_1[3:0]
10_1010 STV[10] SHR2[11:0]+SHR2_2[3:0]
10_1011 STV[11] SHR2[11:0]+SHR2_3[3:0]
Others inhibited -

Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Himax Confidential -P.254-

SETGIP3(Set GIP Option3)

D8H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 1 0 0 0 D8
Bank0 INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
st 1 00
1 parameter GOUT1_L[1:0] GOUT2_L[1:0] GOUT3_L[1:0] GOUT4_L[1:0]
nd INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
2 parameter 1 00
GOUT5_L[1:0] GOUT6_L[1:0] GOUT7_L[1:0] GOUT8_L[1:0]
rd INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
3 parameter 1 00
GOUT9_L[1:0] GOUT10_L[1:0] GOUT11_L[1:0] GOUT12_L[1:0]
th INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
4 parameter 1 00
GOUT13_L[1:0] GOUT14_L[1:0] GOUT15_L[1:0] GOUT16_L[1:0]
th INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
5 parameter 1 00
GOUT17_L[1:0] GOUT18_L[1:0] GOUT19_L[1:0] GOUT20_L[1:0]
th INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
6 parameter 1 00
GOUT1_R[1:0] GOUT2_R[1:0] GOUT3_R[1:0] GOUT4_R[1:0]
th INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
7 parameter 1 00
GOUT5_R[1:0] GOUT6_R[1:0] GOUT7_R[1:0] GOUT8_R[1:0]
th INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
8 parameter 1 00
GOUT9_R[1:0] GOUT10_R[1:0] GOUT11_R[1:0] GOUT12_R[1:0]
th INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
9 parameter 1 00
GOUT13_R[1:0] GOUT14_R[1:0] GOUT15_R[1:0] GOUT16_R[1:0]
th INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C INIT_0_SEL_C
10 parameter 1 00
GOUT17_R[1:0] GOUT18_R[1:0] GOUT19_R[1:0] GOUT20_R[1:0]
st INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
11 parameter 1 00
GOUT1_L[1:0] GOUT2_L[1:0] GOUT3_L[1:0] GOUT4_L[1:0]
nd INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
12 parameter 1 00
GOUT5_L[1:0] GOUT6_L[1:0] GOUT7_L[1:0] GOUT8_L[1:0]
rd INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
13 parameter 1 00
GOUT9_L[1:0] GOUT10_L[1:0] GOUT11_L[1:0] GOUT12_L[1:0]
th INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
14 parameter 1 00
GOUT13_L[1:0] GOUT14_L[1:0] GOUT15_L[1:0] GOUT16_L[1:0]
th INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
15 parameter 1 00
GOUT17_L[1:0] GOUT18_L[1:0] GOUT19_L[1:0] GOUT20_L[1:0]
th INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
16 parameter 1 00
GOUT1_R[1:0] GOUT2_R[1:0] GOUT3_R[1:0] GOUT4_R[1:0]
th INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
17 parameter 1 00
GOUT5_R[1:0] GOUT6_R[1:0] GOUT7_R[1:0] GOUT8_R[1:0]
th INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
18 parameter 1 00
GOUT9_R[1:0] GOUT10_R[1:0] GOUT11_R[1:0] GOUT12_R[1:0]
th INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
19 parameter 1 00
GOUT13_R[1:0] GOUT14_R[1:0] GOUT15_R[1:0] GOUT16_R[1:0]
th INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C INIT_1_SEL_C
20 parameter 1 00
GOUT17_R[1:0] GOUT18_R[1:0] GOUT19_R[1:0] GOUT20_R[1:0]
Bank1 END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
st 1 00
1 parameter GOUT1_L[1:0] GOUT2_L[1:0] GOUT3_L[1:0] GOUT4_L[1:0]
nd END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
2 parameter 1 00
GOUT5_L[1:0] GOUT6_L[1:0] GOUT7_L[1:0] GOUT8_L[1:0]
rd END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
3 parameter 1 00
GOUT9_L[1:0] GOUT10_L[1:0] GOUT11_L[1:0] GOUT12_L[1:0]
th END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
4 parameter 1 00
GOUT13_L[1:0] GOUT14_L[1:0] GOUT15_L[1:0] GOUT16_L[1:0]
th END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
5 parameter 1 00
GOUT17_L[1:0] GOUT18_L[1:0] GOUT19_L[1:0] GOUT20_L[1:0]
th END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
6 parameter 1 00
GOUT1_R[1:0] GOUT2_R[1:0] GOUT3_R[1:0] GOUT4_R[1:0]
Himax Confidential -P.255-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
th END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
7 parameter 1 00
GOUT5_R[1:0] GOUT6_R[1:0] GOUT7_R[1:0] GOUT8_R[1:0]
th END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
8 parameter 1 00
GOUT9_R[1:0] GOUT10_R[1:0] GOUT11_R[1:0] GOUT12_R[1:0]
th END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
9 parameter 1 00
GOUT13_R[1:0] GOUT14_R[1:0] GOUT15_R[1:0] GOUT16_R[1:0]
th END_0_SEL_C END_0_SEL_C END_0_SEL_C END_0_SEL_C
10 parameter 1 00
GOUT17_R[1:0] GOUT18_R[1:0] GOUT19_R[1:0] GOUT20_R[1:0]
st END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
11 parameter 1 00
GOUT1_L[1:0] GOUT2_L[1:0] GOUT3_L[1:0] GOUT4_L[1:0]
nd END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
12 parameter 1 00
GOUT5_L[1:0] GOUT6_L[1:0] GOUT7_L[1:0] GOUT8_L[1:0]
rd END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
13 parameter 1 00
GOUT9_L[1:0] GOUT10_L[1:0] GOUT11_L[1:0] GOUT12_L[1:0]
th END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
14 parameter 1 00
GOUT13_L[1:0] GOUT14_L[1:0] GOUT15_L[1:0] GOUT16_L[1:0]
th END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
15 parameter 1 00
GOUT17_L[1:0] GOUT18_L[1:0] GOUT19_L[1:0] GOUT20_L[1:0]
th END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
16 parameter 1 00
GOUT1_R[1:0] GOUT2_R[1:0] GOUT3_R[1:0] GOUT4_R[1:0]
th END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
17 parameter 1 00
GOUT5_R[1:0] GOUT6_R[1:0] GOUT7_R[1:0] GOUT8_R[1:0]
th END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
18 parameter 1 00
GOUT9_R[1:0] GOUT10_R[1:0] GOUT11_R[1:0] GOUT12_R[1:0]
th END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
19 parameter 1 00
GOUT13_R[1:0] GOUT14_R[1:0] GOUT15_R[1:0] GOUT16_R[1:0]
th END_1_SEL_C END_1_SEL_C END_1_SEL_C END_1_SEL_C
20 parameter 1 00
GOUT17_R[1:0] GOUT18_R[1:0] GOUT19_R[1:0] GOUT20_R[1:0]
st END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
21 parameter 1 00
GOUT1_L[1:0] GOUT2_L[1:0] GOUT3_L[1:0] GOUT4_L[1:0]
nd END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
22 parameter 1 00
GOUT5_L[1:0] GOUT6_L[1:0] GOUT7_L[1:0] GOUT8_L[1:0]
rd END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
23 parameter 1 00
GOUT9_L[1:0] GOUT10_L[1:0] GOUT11_L[1:0] GOUT12_L[1:0]
th END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
24 parameter 1 00
GOUT13_L[1:0] GOUT14_L[1:0] GOUT15_L[1:0] GOUT16_L[1:0]
th END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
25 parameter 1 00
GOUT17_L[1:0] GOUT18_L[1:0] GOUT19_L[1:0] GOUT20_L[1:0]
th END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
26 parameter 1 00
GOUT1_R[1:0] GOUT2_R[1:0] GOUT3_R[1:0] GOUT4_R[1:0]
th END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
27 parameter 1 00
GOUT5_R[1:0] GOUT6_R[1:0] GOUT7_R[1:0] GOUT8_R[1:0]
th END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
28 parameter 1 00
GOUT9_R[1:0] GOUT10_R[1:0] GOUT11_R[1:0] GOUT12_R[1:0]
th END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
29 parameter 1 00
GOUT13_R[1:0] GOUT14_R[1:0] GOUT15_R[1:0] GOUT16_R[1:0]
th END_2_SEL_C END_2_SEL_C END_2_SEL_C END_2_SEL_C
30 parameter 1 00
GOUT17_R[1:0] GOUT18_R[1:0] GOUT19_R[1:0] GOUT20_R[1:0]
Bank2 GAS_0_SEL_C GAS_0_SEL_C GAS_0_SEL_C GAS_0_SEL_C
st 1 00
1 parameter GOUT1_L[1:0] GOUT2_L[1:0] GOUT3_L[1:0] GOUT4_L[1:0]
nd GAS_0_SEL_C GAS_0_SEL_C GAS_0_SEL_C GAS_0_SEL_C
2 parameter 1 00
GOUT5_L[1:0] GOUT6_L[1:0] GOUT7_L[1:0] GOUT8_L[1:0]

Himax Confidential -P.256-

INIT_1_SEL_CGOUTn_L: Set CGOUTL_n output state of second frame or second time

interval when D[1:0]=01.
INIT_1_SEL_CGOUTn_R: Set CGOUTR_n output state of second frame or second time
interval when D[1:0]=01.
n=1~20

END means SLPOUT to SLPIN

END_0_SEL_CGOUTn_L: Set CGOUTL_n output state of first frame or first time interval
when D[1:0]=01.
END_0_SEL_CGOUTn_R: Set CGOUTR_n output state of first frame or first time interval
when D[1:0]=01.
n=1~20

END_1_SEL_CGOUTn_L: Set CGOUTL_n output state of second frame or second time

Description
interval when D[1:0]=01.
END_1_SEL_CGOUTn_R: Set CGOUTR_n output state of second frame or second time
interval when D[1:0]=01.
n=1~20

END_2_SEL_CGOUTn_L: Set CGOUTL_n output state of third frame or third time interval
when D[1:0]=01.
END_2_SEL_CGOUTn_R: Set CGOUTR_n output state of third frame or third time interval
when D[1:0]=01.
n=1~20

GAS means abnormal power off

GAS_0_SEL_CGOUTn_L: When abnormal power off happens,set CGOUTL_n output
state.
GAS_0_SEL_CGOUTn_R: When abnormal power off happens,set CGOUTR_n output
state.
n=1~20

GIP output state:

“00”: Keep normal GIP output.
“01”: Keep normal GIP output.

Himax Confidential -P.257-

Himax Confidential -P.258-

SETGPO
D9H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 1 0 0 1 D9
st
1 parameter 1 - - - - TE_GPO[3:0] 00
nd
2 parameter 1 - - - - TE1_GPO[3:0] 01
rd
3 parameter 1 - - - - CABC_GPO[3:0] 02
th
4 parameter 1 - - - - SDO_GPO[3:0] 07
TE_GPO[3:0]: Set the output pin TE.
TE1_GPO[3:0]: Set the output pin TE1.
CABC_GPO[3:0]: : Set the output pin CABC_PWM_OUT.
SDO_GPO[3:0]: Set the output pin SDO.

TE_GPO[3:0]/ TE1_GPO[3:0]/ CABC_GPO[3:0]/ TE/ TE1/ CABC_PWM_OUT/ SDO

SDO_GPO[3:0] Output signal
0 0 0 0 TE
Description 0 0 0 1 TE1
0 0 1 0 CABC
0 0 1 1 HSYNC
0 1 0 0 VSYNC
0 1 0 1 DE
0 1 1 0 DSI_ERR_RPT
0 1 1 1 SDO
Others Inhibited
Restrictions SETEXTC turn on to enable this command
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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SETSCALING
DDH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 1 1 0 1 DD
SCALI SCALI
st
1 parameter 1 - - - - - - NG_T NG_E 00
YPE N
SCALING_EN: Set”1” enable scaling function.

SCALING_TYPE:
Description 0: 2x scaling
1: 1.5x scaling

Restrictions SETEXTC turn on to enable this command

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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SETIDLE
D9H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 0 1 1 1 1 1 DF
st 1BRA
1 parameter 1 - - - - NW_I[2:0] 00
M_EN
nd
2 parameter 1 BP_I[7:0] 1C
rd
3 parameter 1 FP_I[7:0] 0B
th
4 parameter 1 RTN_I[7:0] 45
th
5 parameter 1 VCMC_F_I[7:0] 34
h
6 parameter 1 VCMC_B_I[7:0] 34
th VCMC VCMC
7 parameter 1 AP_I[2:0] - - - _B_I[8]
83
_F_I[8]
th
8 parameter 1 FS0_I[3:0] FS1_I[3:0] 23
th
9 parameter 1 FS2_I[3:0] - - - - 30
Set Idle mode related setting.

1BRAM_EN: Idle mode 1Bit RAM enable.

“0”: Idle mode bypass RAM(using video mode display).
“1”: Idle mode display 1 Bit RAM data(using command mode write GARM)

NW_I[2:0]: Inversion type setting in idle mode.

NW_I[2:0] Inversion type
0 0 0 Column inversion
0 0 1 1-dot inversion
0 1 0 2-dot inversion
0 1 1 4-dot inversion
1 0 0 8-dot inversion
1 0 1 Zig-zag inversion
1 1 0 2-dot-2 inversion
1 1 1 3-dot inversion

BP_I[7:0] : Specify the amount of scan line for back porch(BP) in idle mode.
FP_I[7:0]: Specify the amount of scan line for front porch (FP) in idle mode.
Description
FP[7:0]_I / BP_I[7:0] Number of front porch/ back porch Lines
8h’00 2 lines
8h’01 3 lines
8h’02 4 lines
8h’03 5 lines
8h’04 6 lines
8h’05 7 lines
: :
8h’FB 253 lines
8h’FC 254 lines
8h’FD 255 lines
8h’FE 256 lines
8h’FF 257 lines
Note: Set BP_I[7:0] = VS + VBP – 2, and FP_I[7:0] = VFP – 2.

RTN_I[7:0]: A cycle time of line width in idle mode.

(1 TCON clock period= 1/22MHz)
RTN_I[7:0] Clock per Line
8h’00 97 TCON CLK
8h’01 98 TCON CLK

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VCMC_F_I[8:0]: Forward scan VCOM voltage control in Idle mode.

VCMC_B_I[8:0]: Backward scan VCOM voltage control in Idle mode.

VCMC_F_I[8:0]/VCMC_B_I[8:0] VCOM
0 0 0 0 0 0 0 0 0 VSSA
0 0 0 0 0 0 0 0 1 -4.00V
0 0 0 0 0 0 0 1 0 -4.00V
0 0 0 0 0 0 0 1 1 -4.00V
0 0 0 0 0 0 1 0 0 -4.00V
0 0 0 0 0 0 1 0 1 -4.00V
0 0 0 0 0 0 1 1 0 -4.00V
0 0 0 0 0 0 1 1 1 -4.00V
0 0 0 0 0 1 0 0 0 -4.00V
0 0 0 0 0 1 0 0 1 -3.99V
0 0 0 0 0 1 0 1 0 -3.98V
0 0 0 0 0 1 0 1 1 -3.97V
: :
1 1 0 0 1 0 1 1 0 -0.02V
1 1 0 0 1 0 1 1 1 -0.01V
1 1 0 0 1 1 0 0 0 VSSA
1 1 0 0 1 1 0 0 1 0.01V
1 1 0 0 1 1 0 1 0 0.02V
1 1 0 0 1 1 0 1 1 0.03V
: :
1 1 1 1 1 1 0 1 0 0.98V
1 1 1 1 1 1 0 1 1 0.99V
1 1 1 1 1 1 1 0 0 1V
1 1 1 1 1 1 1 0 1 1V
1 1 1 1 1 1 1 1 0 1V
1 1 1 1 1 1 1 1 1 HZ

AP_I[2:0]: Adjust the amount of fixed current from the fixed current source for the operational
amplifier in idle mode.
AP_I[2:0] Constant Current of Operational Amplifier
0 0 0 Stop
0 0 1 0.5A
0 1 0 1.0A

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FS0_I[3:0]:Set the operating frequency of the step-up circuit for VSP/VSN voltage generation
in Idle mode. (Fosc_pump=4.89MHz)
FS0_I[3:0] Operation Frequency of Step-up Circuit
0 0 0 0 Fosc_pump/2
0 0 0 1 Fosc_pump/4
0 0 1 0 Fosc_pump/8
0 0 1 1 Fosc_pump/16
0 1 0 0 Fosc_pump/32
0 1 0 1 Fosc_pump/48
0 1 1 0 Fosc_pump/64
0 1 1 1 Fosc_pump/80
1 0 0 0 Fosc_pump/96
1 0 0 1 Fosc_pump/112
1 0 1 0 Fosc_pump/128
1 0 1 1 Fosc_pump/144
1 1 0 0 Fosc_pump/160
1 1 0 1 Fosc_pump/176
1 1 1 0 Fosc_pump/192
1 1 1 1 Fosc_pump/208

FS1_I[3:0]: Set the operating frequency of the step-up circuit for VGH/VGL voltage generation
in Idle mode. (Fosc_pump=4.89MHz)
FS1_I[3:0] Operation Frequency of Step-up Circuit
0 0 0 0 Fosc_pump/72
0 0 0 1 Fosc_pump/96
0 0 1 0 Fosc_pump/128
0 0 1 1 Fosc_pump/160
0 1 0 0 Fosc_pump/192
0 1 0 1 Fosc_pump/224
0 1 1 0 Fosc_pump/256
0 1 1 1 Fosc_pump/336
1 0 0 0 Hsync*4
1 0 0 1 Hsync*2
1 0 1 0 Hsync
1 0 1 1 Hsync/2
1 1 0 0 Hsync/4
1 1 0 1 Hsync/8
1 1 1 0 Hsync/16
1 1 1 1 Inhibited

FS2_I[3:0]: Adjust the charge pump frequency of internal VCI_REG voltage in Idle mode.
(Fosc_pump=4.89MHz)
FS2_I[3:0] Operation Frequency of Step-up Circuit
0 0 0 0 Fosc_pump/72
0 0 0 1 Fosc_pump/96
0 0 1 0 Fosc_pump/128
0 0 1 1 Fosc_pump/160
0 1 0 0 Fosc_pump/192
0 1 0 1 Fosc_pump/224
0 1 1 0 Fosc_pump/256
0 1 1 1 Fosc_pump/336

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Himax Confidential -P.264-

SETGAMMA ( Set Gamma Curve Related Setting )

E0H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 1 0 0 0 0 0 E0
st
1 Parameter 1 - VHP0[6:0] 00
nd
2 parameter 1 - VHP1[6:0] 04
rd
3 parameter 1 - VHP2[6:0] 08
th
4 parameter 1 - VHP3[6:0] 0C
th
5 parameter 1 - VHP4[6:0] 10
th
6 parameter 1 - VHP5[6:0] 14
th
7 parameter 1 - VHP6[6:0] 18
th
8 parameter 1 - VHP7[6:0] 1C
th
9 parameter 1 VMP0[7:0] 20
th
10 parameter 1 VMP1[7:0] 24
st
11 parameter 1 VMP2[7:0] 28
nd
12 parameter 1 VMP3[7:0] 2C
rd
13 parameter 1 VMP4[7:0] 30
th
14 parameter 1 VMP5[7:0] 34
th
15 parameter 1 VMP6[7:0] 38
th
16 parameter 1 VMP7[7:0] 3C
th
17 parameter 1 VMP8[7:0] 40
th
18 parameter 1 VMP9[7:0] 44
th
19 parameter 1 VMP10[7:0] 48
th
20 parameter 1 VMP11[7:0] 4C
st
21 Parameter 1 VMP12[7:0] 50
nd
22 parameter 1 - VLP0[6:0] 54
rd
23 parameter 1 - VLP1[6:0] 58
th
24 parameter 1 - VLP2[6:0] 5C
th
25 parameter 1 - VLP3[6:0] 60
th
26 parameter 1 - VLP4[6:0] 64
th
27 parameter 1 - VLP5[6:0] 68
th
28 parameter 1 - VLP6[6:0] 6C
th
29 parameter 1 - VLP7[6:0] 7F
th
30 parameter 1 - VHN0[6:0] 00
st
31 Parameter 1 - VHN1[6:0] 04
nd
32 parameter 1 - VHN2[6:0] 08
rd
33 parameter 1 - VHN3[6:0] 0C
th
34 parameter 1 - VHN4[6:0] 10
th
35 parameter 1 - VHN5[6:0] 14
th
36 parameter 1 - VHN6[6:0] 18
th
37 parameter 1 - VHN7[6:0] 1C
th
38 parameter 1 VMN0[7:0] 20
th
39 parameter 1 VMN1[7:0] 24
th
40 parameter 1 VMN2[7:0] 28
st
41 Parameter 1 VMN3[7:0] 2C
nd
42 parameter 1 VMN4[7:0] 30
rd
43 parameter 1 VMN5[7:0] 34
th
44 parameter 1 VMN6[7:0] 38
th
45 parameter 1 VMN7[7:0] 3C
th
46 parameter 1 VMN8[7:0] 40
th
47 parameter 1 VMN9[7:0] 44
th
48 parameter 1 VMN10[7:0] 48
th
49 parameter 1 VMN11[7:0] 4C
th
50 parameter 1 VMN12[7:0] 50
st
51 Parameter 1 - VLN0[6:0] 54
nd
52 parameter 1 - VLN1[6:0] 58
Himax Confidential -P.265-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015
HX8398-A
1080RGBx1920dots, a-Si TFT Mobile Single Chip Driver
Temporary DATA SHEET V00.04
rd
53 parameter 1 - VLN2[6:0] 5C
th
54 parameter 1 - VLN3[6:0] 60
th
55 parameter 1 - VLN4[6:0] 64
th
56 parameter 1 - VLN5[6:0] 68
th
57 parameter 1 - VLN6[6:0] 6C
th
58 parameter 1 - VLN7[6:0] 7F
This command is to set gamma register.

Register Positive Negative

Description
Groups Polarity Polarity
VHP0 6-0 VHN0 6-0 128-to-1 selector (voltage level of grayscale 0)
VHP1 6-0 VHN1 6-0 128-to-1 selector (voltage level of grayscale 1)
VHP2 6-0 VHN2 6-0 128-to-1 selector (voltage level of grayscale 3)
Up Edge VHP3 6-0 VHN3 6-0 128-to-1 selector (voltage level of grayscale 5)
adjustment VHP4 6-0 VHN4 6-0 128-to-1 selector (voltage level of grayscale 7)
VHP5 6-0 VHN5 6-0 128-to-1 selector (voltage level of grayscale 9)
VHP6 6-0 VHN6 6-0 128-to-1 selector (voltage level of grayscale 12)
VHP7 6-0 VHN7 6-0 128-to-1 selector (voltage level of grayscale 15)
VMP0 7-0 VMN0 7-0 255-to-1 selector (voltage level of grayscale 20)
VMP1 7-0 VMN1 7-0 255-to-1 selector (voltage level of grayscale 28)
VMP2 7-0 VMN2 7-0 255-to-1 selector (voltage level of grayscale 40)
VMP3 7-0 VMN3 7-0 255-to-1 selector (voltage level of grayscale 52)
Description VMP4 7-0 VMN4 7-0 255-to-1 selector (voltage level of grayscale 76)
VMP5 7-0 VMN5 7-0 255-to-1 selector (voltage level of grayscale 100)
Center
VMP6 7-0 VMN6 7-0 255-to-1 selector (voltage level of grayscale 128)
adjustment
VMP7 7-0 VMN7 7-0 255-to-1 selector (voltage level of grayscale 156)
VMP8 7-0 VMN8 7-0 255-to-1 selector (voltage level of grayscale 180)
VMP9 7-0 VMN9 7-0 255-to-1 selector (voltage level of grayscale 204)
VMP10 7-0 VMN10 7-0 255-to-1 selector (voltage level of grayscale 216)
VMP11 7-0 VMN11 7-0 255-to-1 selector (voltage level of grayscale 228)
VMP12 7-0 VMN12 7-0 255-to-1 selector (voltage level of grayscale 236)
VLP0 6-0 VLN0 6-0 128-to-1 selector (voltage level of grayscale 240)
VLP1 6-0 VLN1 6-0 128-to-1 selector (voltage level of grayscale 243)
VLP2 6-0 VLN2 6-0 128-to-1 selector (voltage level of grayscale 246)
Down Edge VLP3 6-0 VLN3 6-0 128-to-1 selector (voltage level of grayscale 248)
adjustment VLP4 6-0 VLN4 6-0 128-to-1 selector (voltage level of grayscale 250)
VLP5 6-0 VLN5 6-0 128-to-1 selector (voltage level of grayscale 252)
VLP6 6-0 VLN6 6-0 128-to-1 selector (voltage level of grayscale 254)
VLP7 6-0 VLN7 6-0 128-to-1 selector (voltage level of grayscale 255)
Restriction SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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SETCHEMODE_DYN (Set color enhancement mode, dynamic)

E4H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 1 0 0 1 0 0 E4
st DYN_C
1 parameter 1 - - - - - - - EH_EN
01
nd
2 parameter 1 HUE_MODE[1:0] SE_MODE[1:0] BE_MODE[1:0] CE_MODE[1:0] 00
This command is to set color enhanment and dynamic mode.

DYN_CHE_EN: Select the color enhancement reload mode. 0: static mode, 1: dynamic mode.

CE_MODE[1:0]: Set color (saturation) enhancement.

BE_MODE[1:0]: Set brightness enhancement.

SE_MODE[1:0]: Set sharpness enhancement.

HUE_MODE[1:0]: Set hue enhancement.

In Static mode:
Enhancement level selection: when SE/BE/CE/HUE is turn on, the enhancement effect
depends on the gobal gain curve set.

CE_MODE[1:0]/ BE_MODE[1:0]/ SE_MODE[1:0]/ HUE_MODE[1:0] Enhance

0 0 Off
0 1
1 0 On
1 1

In Dynamic mode:
Enhance level selection. wWhen SE/BE/CE/HUE turn on, the enhancement gain setting will be
read from the ROM table. Three sets of enhancement gain are provide for selection.
Description
CE_MODE[1:0]/ BE_MODE[1:0]/ SE_MODE[1:0]/ HUE_MODE[1:0] Enhance
0 0 Off
0 1 Low
1 0 Medium
1 1 High

Color Enhancemet
Off Low Medium High

Brightness Enhancement
Off Low Medium High

Sharpness Enhancement
Off Low Medium High

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Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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SETI2C_SA(Set I2C Slave Address)

E8H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 1 0 1 0 0 0 E8
st
1 parameter 1 - I2C_SA[6:0] 00
This register is for setting I2C slave address.

I2C_SA[6 :0] Slave address (A6-A0)

000_0000 000_0000
000_0001~000_0111 Reserved
Description
000_1000 000_1000
: :
111_0110 111_0110
111_0111 111_0111
111_1xxx Reserved
Restrictions SETEXTC turn on to enable this command
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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SETCNCD/GETCNCD (Set/Get Continue Command)

FDH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 1 1 1 1 0 1 FD
st
1 parameter 1 WR_CMD_CN[7:0] -
This function is use to instead of Register-Content interface mode.
Description
The parameter for SETCNCD will continue to write or read from the last command address
automatically.
Restrictions SETEXTC turn on to enable this command
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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SET SPI READ INDEX (Set SPI READ Command Address)

FEH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 1 1 1 1 1 0 FE
st
1 parameter 1 CMD_ADD[7:0] -
Description SET SPI Read Command Address for User Define Command.
Restrictions SETEXTC turn on to enable this command
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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GETSPIREAD (Read Command Data)

FFH
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 1 1 1 1 1 1 1 FF
st
1 parameter 1 CMD_DATA1[7:0] -
: 1 : -
th
n parameter 1 CMD_DATAn[7:0] -
Description Read SPI Command Data for User Define Command.
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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Maximum series
Name Type Unit
resistance
VDD1 Power supply 5 Ω
VDD3 Power supply 5 Ω
VSSD Power supply 5 Ω
VSSD_P Power supply 5 Ω
VSSA Power supply 5 Ω
VSSAC Power supply 5 Ω
HS_VCC Power supply 5 Ω
HS_VSS Power supply 5 Ω
GIP_RGNDG1_L, GIP_RGNDG2_R Power supply 5 Ω
VGH1_RGND, VGH2_RGND Power supply 5 Ω
HS_CLKP, HS_CLKN Input 6 Ω
HS_D0P, HS_D0N Input + Output 6 Ω
HS_D1P, HS_D1N Input 6 Ω
HS_D2P, HS_D2N Input 6 Ω
HS_D3P, HS_D3N Input 6 Ω
CGOUTL_1~20, CGOUTR1~20 Output 10 Ω
VSP, VSN Capacitor Connection 10 Ω
VSPR, VSNR, VREF, Output 20 Ω
VDDD Capacitor Connection 5 Ω
HS_LDO Capacitor Connection 10 Ω
VCOM Capacitor Connection 10 Ω
VCI_REG Capacitor Connection 10 Ω
VGH, VGL, VGH1, VGH2, VGLO2 Capacitor Connection 10 Ω
C21P, C21N, C22P, C22N Capacitor Connection 5 Ω
C31P, C31N Capacitor Connection 5 Ω
C41P, C41N, C42P, C42N Capacitor Connection 5 Ω
IM[2:0] Input 100 Ω
PCCS[2:0] Input 100 Ω
DSWAP[1:0], PNSWAP Input 100 Ω
CSX, SCL, DCX, RESX Input 100 Ω
HSYNC, VSYNC, DE, PCLK Input 100 Ω
SDI_SDA Input + Output 100 Ω
SDO Output 100 Ω
DB[23:0] Input 100 Ω
FRM Input 100 Ω
IMAGE_UPDATE, LV_DETEC Input 100 Ω
TH0, TH1 Input 100 Ω
CABC_PWM_OUT, TE, TE1 Output 100 Ω
VCSW1, VCSW2 Output 100 Ω
GPO1~3, REQOUT Output 100 Ω
VSOUT, HSOUT Output 100 Ω
OSC Input 100 Ω
TEST[2:0] Input 100 Ω
TS0~7 Output 100 Ω
VTESTOUTP, VTESTOUTN Output 100 Ω
Table 7.1: Maximum Layout Resistance(include IC and FPC bonding)

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PFM Type A mode:

Typical
Pad Name Symbol Connection
Component Value
VDD1 C1 Connect to Capacitor (Max 6V): VDD1 ---(+)----| |--- (-)----- VSSA 2.2 μF
HS_VCC C2 Connect to Capacitor (Max 6V): HS_VCC ---(+)----| |--- (-)----- HS_VSS 2.2 μF
VDD3 C3 Connect to Capacitor (Max 6V): VDD3 ---(+)----| |--- (-)-----VSSA 2.2 μF
VDDD C4 Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 2.2 μF
HS_LDO C5 Connect to Capacitor (Max 6V): HS_LDO ---(+)----| |--- (-)----HS_VSS 2.2 μF
VSP C6 Connect to Capacitor (Max 10V):VSP ---(+)----| |--- (-)-----VSSA 2.2 μF
VSN C7 Connect to Capacitor (Max 10V):VSN ---(-)----| |--- (+)-----VSSA 2.2 μF
VCOM C8 Connect to Capacitor (Max 6V): VCOM ---(-)----| |--- (+)----- VSSA 2.2 μF
VGH C9 Connect to Capacitor (Max 25V): VGH ---(+)----| |--- (-)----- VSSA 2.2 μF
C10 Connect to Capacitor (Max 25V): VGL ---(-)----| |--- (+)----- VSSA 2.2 μF
VGL VF < 0.4V / 20mA @ 25C,
D1 Connect to Schottky Diode(VR≥30V): VSSA ---(-)----∫◄--- (+)---- VGL VR ≥30V (Recommended
diode: RB521S-30)
C21P-C21N C12 Connect to Capacitor (Max 16V): C21P ---(+)----| |--- (-)-----C21N 1.0 μF
C22P-C22N C13 Connect to Capacitor (Max 16V): C22P ---(+)----| |--- (-)-----C22N 1.0 μF
C31P-C31N C14 Connect to Capacitor (Max 16V): C31P ---(+)----| |--- (-)-----C31N 1.0 μF
PFM L1 Inductiance, reference PFM Type A connection -
PFM SW1 MOS switch, reference PFM Type A connection -
PFM SW2 MOS switch, reference PFM Type A connection -
VF < 0.4V / 20mA @ 25C,
PFM D2 Schottkey diode, reference PFM Type A connection VR ≥30V (Recommended
diode: RB521S-30)
VF < 0.4V / 20mA @ 25C,
PFM D3 Schottkey diode, reference PFM Type A connection VR ≥30V (Recommended
diode: RB521S-30)
Table 7.3: PFM Type A mode external components

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PFM Type C mode:

Typical
Pad Name Symbol Connection
Component Value
VDD1 C1 Connect to Capacitor (Max 6V): VDD1 ---(+)----| |--- (-)----- VSSA 2.2 μF
HS_VCC C2 Connect to Capacitor (Max 6V): HS_VCC ---(+)----| |--- (-)----- HS_VSS 2.2 μF
VDD3 C3 Connect to Capacitor (Max 6V): VDD3 ---(+)----| |--- (-)-----VSSA 2.2 μF
VDDD C4 Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 2.2 μF
HS_LDO C5 Connect to Capacitor (Max 6V): HS_LDO ---(+)----| |--- (-)----HS_VSS 2.2 μF
VSP C6 Connect to Capacitor (Max 10V):VSP ---(+)----| |--- (-)-----VSSA 2.2 μF
VSN C7 Connect to Capacitor (Max 10V):VSN ---(-)----| |--- (+)-----VSSA 2.2 μF
VCOM C8 Connect to Capacitor (Max 6V): VCOM ---(-)----| |--- (+)----- VSSA 2.2 μF
VGH C9 Connect to Capacitor (Max 25V): VGH ---(+)----| |--- (-)----- VSSA 2.2 μF
C10 Connect to Capacitor (Max 25V): VGL ---(-)----| |--- (+)----- VSSA 2.2 μF
VGL VF < 0.4V / 20mA @ 25C,
D1 Connect to Schottky Diode(VR≥30V): VSSA ---(-)----∫◄--- (+)---- VGL VR ≥30V (Recommended
diode: RB521S-30)
C21P-C21N C12 Connect to Capacitor (Max 16V): C21P ---(+)----| |--- (-)-----C21N 1.0 μF
C22P-C22N C13 Connect to Capacitor (Max 16V): C22P ---(+)----| |--- (-)-----C22N 1.0 μF
C31P-C31N C14 Connect to Capacitor (Max 16V): C31P ---(+)----| |--- (-)-----C31N 1.0 μF
PFM L1 Inductiance, reference PFM Type C connection -
PFM SW1 MOS switch, reference PFM Type C connection -
VF < 0.4V / 20mA @ 25C,
PFM D2 Schottkey diode, reference PFM Type C connection VR ≥30V (Recommended
diode: RB521S-30)
VF < 0.4V / 20mA @ 25C,
PFM D3 Schottkey diode, reference PFM Type C connection VR ≥30V (Recommended
diode: RB521S-30)
VF < 0.4V / 20mA @ 25C,
PFM D4 Schottkey diode, reference PFM Type C connection VR ≥30V (Recommended
diode: RB521S-30)
PFM C20 Capacitor, reference PFM Type C connection 1.0uF
Table 7.5: PFM Type C mode external components

Himax Confidential -P.275-

External VDD3/VSP/VSN mode:

Typical
Pad Name Symbol Connection
Component Value
VDD1 C1 Connect to Capacitor (Max 6V): VDD1 ---(+)----| |--- (-)----- VSSA 2.2 μF
HS_VCC C2 Connect to Capacitor (Max 6V): HS_VCC ---(+)----| |--- (-)----- HS_VSS 2.2 μF
VDD3 C3 Connect to Capacitor (Max 6V): VDD3 ---(+)----| |--- (-)-----VSSA 2.2 μF
VDDD C4 Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 2.2 μF
HS_LDO C5 Connect to Capacitor (Max 6V): HS_LDO ---(+)----| |--- (-)----HS_VSS 2.2 μF
VSP C6 Connect to Capacitor (Max 10V):VSP ---(+)----| |--- (-)-----VSSA 2.2 μF
VSN C7 Connect to Capacitor (Max 10V):VSN ---(-)----| |--- (+)-----VSSA 2.2 μF
VCOM C8 Connect to Capacitor (Max 6V): VCOM ---(-)----| |--- (+)----- VSSA 2.2 μF
VGH C9 Connect to Capacitor (Max 25V): VGH ---(+)----| |--- (-)----- VSSA 2.2 μF
C10 Connect to Capacitor (Max 25V): VGL ---(-)----| |--- (+)----- VSSA 2.2 μF
VGL VF < 0.4V / 20mA @ 25C,
D1 Connect to Schottky Diode(VR≥30V): VSN ---(-)----∫◄--- (+)---- VGL VR ≥30V (Recommended
diode: RB521S-30)
C21P-C21N C12 Connect to Capacitor (Max 16V): C21P ---(+)----| |--- (-)-----C21N 1.0 μF
C22P-C22N C13 Connect to Capacitor (Max 16V): C22P ---(+)----| |--- (-)-----C22N 1.0 μF
C31P-C31N C14 Connect to Capacitor (Max 16V): C31P ---(+)----| |--- (-)-----C31N 1.0 μF
Table 7.7: External VDD3/VSP/VSN mode external components

Himax Confidential -P.276-

Himax Confidential -P.277-

The absolute maximum ratings are list on Table 8.1. When used out of the absolute
maximum ratings, the LSI may be permanently damaged. Using the LSI within the
following electrical characteristics limit is strongly recommended for normal operation.
If these electrical characteristic conditions are exceeded during normal operation, the
LSI will malfunction and cause poor reliability.

Item Symbol Unit Value Note

(1),(2)
Power Supply Voltage 1 VDD1~ VSSD V -0.3 to +4 Note
(1) (3)
Power Supply Voltage 2 VDD3 ~ VSSA V -0.3 to +4 Note
HS_VCC ~ (1) (4)
Power Supply Voltage 3 V -0.3 to +4 Note
HS_VSS
(5)
Power Supply Voltage 4 VSP ~ VSSA V -0.3 to +6.6 Note
(6)
Power Supply Voltage 5 VSSA ~ VSN V 0 to -6.6 Note
(7)
Power Supply Voltage 6 VGH ~ VSSA V -0.3 to +22 Note
(8)
Power Supply Voltage 7 VSSA ~ VGL V 0 to -20 Note
(9)
Operating Temperature Topr C -40 to +85 Note
(10)
Storage Temperature Tstg C -55 to +110 Note
Note: (1) VDD1, VSSD must be maintained.
(2) To make sure VDD1 ≥ VSSD.
(3) To make sure VDD3≥ VSSA.
(4) To make sure HS_VCC ≥ HS_VSS.
(5) To make sure VSP ≥ VSSA.
(6) To make sure VSSA ≥ VSN
(7) To make sure VGH ≥ VSSA.
(8) To make sure VSSA ≥ VGL
VGH +|VGL| < 30V
(9) For die and wafer products, specified up to +85℃.
(10) This temperature specifications apply to the TCP package.

Table 8.1: Absolute maximum rating

Himax Confidential -P.278-

Himax Confidential -P.279-

Characteristics of SDA and SCL bus lines for I2C-bus devices

SDA
tbuf
tLOW tR tF tHD:SAT tSP

SCL

tHD:STA tSU:STO
tHD:DAT tHIGH tSU:DAT tSU:SAT
P S Sr P

Figure 8.1 I2C timing

Standard-Mode Fast-Mode
Parameter Symbol I2C-BUS I2C-BUS Unit
Min. Max. Min. Max.
SCL clock frequency f SCL 0 100 0 400 KHz
Bus free time between STOP and START condition t BUF 4.7 - 1.3 - μs
Hold time (repeated) START condition.
t HD : STA 4.0 - 0.6 - μs
After this period, the first clock pulse is generated
LOW period of the SCL clock t LOW 4.7 - 1.3 - μs
HIGH period of the SCL clock t HIGH 4.0 - 0.6 - μs
Set-up time for a repeated START condition t SU :STA
4.7 - 0.6 - μs
Data hold time t HD : DAT 0 - 0 0.9 μs
Data set-up time t SU : DAT 250 - 100 - ns
Rise time of both SDA and SCL signals tR - 1000 20+0.1 C b 300 ns
Fall time of both SDA and SCL signals tF - 300 20+0.1 C b 300 ns
Set-up time for STOP condition t SU : STO
4.0 - 0.6 - μs
Capacitive load for each bus line. Cb - 400 - 400 pF
Note: (1) All values are referred to VIH (0.7xVCCIO) and VIL (0.3xVCCIO) level.
(2) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
(3) The maximum t HD : DAT has only to be met if the device does not stretch the LOW period ( t LOW ) of the SCL
signal.
(4) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement t SU : DAT
≧
250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t R max
 t SU : DAT
= 1000+250=1250ns (according to the standard-mode I2C-bus specification) before
the SCL line is released.
(5) C b = total capacitance of one bus line in pF.
Table 8.3 I2C timing spec.

Himax Confidential -P.280-

CSX tCSS tCSH

DCX tAST tAHT

tWC/tRC
SCL tWRL/tRDL
tWRH/tRDH
tDS tDH
SDI
(Input)
tacc tod
SDO
(Output)
Figure 8.2: DBI Type C interface characteristics

(VSSA=0V, VDD1=1.8V, VDD3=2.8V, TA = 25°C)

Signal Symbol Parameter Min. Max. Unit Description
tCSS Chip select setup time (Write) 40 -
CSX tCSH Chip select setup time (Read) 40 -
ns -
tAST Address setup time 10 -
DCX tAHT Address hold time (Write/Read) 10 - ns -
tWC Write cycle 100 -
SCL
tWRH Control pulse “H” duration 40 - ns -
(Write) tWRL Control pulse “L” duration 40 -
tRC Read cycle 150 -
SCL
tRDH Control pulse “H” duration 60 - ns -
(Read) tRDL Control pulse “L” duration 60 -
SDI/SDO tDS Data setup time 30 -
tDT Data hold time 30 -
ns
(Input) For maximum CL=30pF
SDI/SDO tRACC Read access time 10 - For minimum CL=8pF
tOD Output disable time 10 50
ns
(Output)
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals.
Table 8.4: DBI Type C interface characteristics

Himax Confidential -P.281-

[Link] The Electrical Characteristics of D-PHY Layer

In general, the DSI - PHY may contain the following electrical functions: High-Speed Receiver
(HS-RX), Low Power Transmitter (LP-TX), a Low-Power Receiver (LP-RX), and the
Low-Power Contention Detector (LP-CD). Figure 8.3 shows the complete set of electrical
functions required for a fully featured PHY transceiver.

LP-TX

CLOCK
TX

Dn
DATA

Lane Control HS-RX RT

and
interface Logic

CONTROL
LP-RX

LP-CD

Figure 8.3: Electrical functions of a fully D-PHY transceiver

Where, the HS receiver utilize low-voltage swing differential signaling for signal transmission.
The LP transmitter and LP receiver serve as a low power signaling mechanism. The Figure
8.4 shows both the HS and LP signal levels on the left and right sides, respectively.

Because the HS signaling levels are below the LP low-level input threshold, Lane switches
between Low-Power and High-Speed mode during normal operation.

VOH,MAX

LP RX
INPUT HIGH

LP RX
VIHHS
Threshold Region

VIL,MAX

VIL,MAX VCMRXDC,MAX

LP Contention HS TX HS-RX
LP RX
Fault Threshold Input Range Common mode
INPUT HIGH
input Range
VIL,MIN
VCMRXDC,MIN
VOL,MAX
GND GND
VOL,MIN VILHS

Low Power Low Power Low Power High Speed

TX RX CD RX
Figure 8.4: Shows both the HS and LP signal levels

Himax Confidential -P.282-

The Low-Power transmitter shall be a slew-rate controlled push-pull driver. It is used for
driving the Lines in all Low-Power operating modes It is therefore important that the static
power consumption of a LP transmitter be as low as possible. Under tables list DC and AC
characteristic for LP-TX

Parameter Description Min. Typ. Max. Unit Note

VOL Thevenin output low level -50 - 50 mV -
VOH Thevenin output high level 1.1 1.2 1.3 V -
ZOLP Output impedance of LP-TX 110 - - Ω (1)
Note: (1)Though no maximum value for ZOLP is specified, the LP transmitter output impedance shall
ensure the tRLP/tFLP specification is met.
Table 8.5: LP Transmitter DC Specifications

Parameter Description Min. Typ. Max. Unit Note

tRLP/tFLP 15%-85% rise time and fall time - - 25 ns (1)
Slew rate @ CLOAD = 0pF 30 - 500 mV/ns (1),(3),(5),(6)
Slew rate @ CLOAD = 5pF - - 300 mV/ns (1),(3),(5),(6)
Slew rate @ CLOAD = 20pF - - 250 mV/ns (1),(3),(5),(6)
Slew rate @ CLOAD = 70pF - - 150 mV/ns (1),(3),(5),(6)
Slew rate @ CLOAD = 0 to 70pF
δV/δtSR 30 - - mV/ns (1),(2),(3)
(Falling Edge Only)
Slew rate @ CLOAD = 0 to 70pF
30 - - mV/ns (1),(3),(7)
(Rising Edge Only)
Slew rate @ CLOAD = 0 to 70pF 30 – 0.075 *
- - mV/ns (1),(8),(9)
(Rising Edge Only) (VO,INST- 700)
CLOAD Load capacitance - - 70 pF -
Note: (1) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and
RX are assumed to always be <10pF. The distributed line capacitance can be up to 50pF for a transmission
line with 2ns delay.
(2) When the output voltage is between 400 mV and 930 mV.
(3) Measured as average across any 50 mV segment of the output signal transition.
(4) This parameter value can be lower than TLPX due to differences in rise vs. fall signal slopes and trip levels
and mismatches between Dp and Dn LP transmitters.
(5) This value represents a corner point in a piecewise linear curve.
(6) When the output voltage is in the range specified by VPIN(absmax).
(7) When the output voltage is between 400 mV and 700 mV.
(8) Where VO,INST is the instantaneous output voltage, VDP or VDN, in millivolts.
(9) When the output voltage is between 700 mV and 930 mV.
Table 8.6: LP Transmitter AC Specifications

Himax Confidential -P.283-

This part will contain two parts which High-Speed Receiver and Low-Power Receiver.
Because their have differential DC and AC characteristic, describe HS-RX first then describe
LP-RX.

[Link] High-Speed Receiver

The HS receiver is a differential line receiver. It contains a switch-able parallel input

termination, ZID, between the positive input pin Dp and the negative input pin Dn. Under
Tables list DC and AC characteristic for HS-RX.

Parameter Description Min. Typ. Max. Unit Note

VIDTH Differential input high threshold - - 70 mV -
VIDTL Differential input low threshold -70 - - mV -
VILHS Single-ended input low voltage -40 - - mV (1)
VIHHS Single-ended input high voltage - - 460 mV (1)
VCMRXDC Common-mode voltage HS receive mode 70 - 330 mV (1),(2)
ZID Differential input impedance 80 100 125 Ω -
Note: (1) +/-70mV only for reference, related to power and ground noise on system environment, this spec need to check on
panel performance to fine tune.
(2) Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz.
(3) This table value includes a ground difference of 50mV between the transmitter and the receiver, the static
common-mode level tolerance and variations below 450MHz
Table 8.7: HS Receiver DC Specifications

HS-1 HS-0
TX output high
Signal Integrity Decay
VIDTH

0V (Differential)

VIDTL
Signal Integrity Decay
TX output Low

undefined
Figure 8.5: Differential HS signals for HS receive

Parameter Description Min. Typ. Max. Unit Note

ΔVCMRX(HF) Common mode interference beyond 450 MHz - - 100 mVPP (1)
CCM Common mode termination - - 60 pF (2)
Note: (1) ΔVCMRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs.
(2) For higher bit rates a 14pF capacitor will be needed to meet the common-mode return loss specification.
Table 8.8: HS Receiver AC Specifications

Himax Confidential -P.284-

The low power receiver is an un-terminated, single-ended receiver circuit. The LP receiver is
used to detect the Low-Power state on each pin. For high robustness, the LP receiver shall
filter out noise pulses and RF interference. It is recommended the implementer optimize the
LP receiver design for low power. The LP receiver shall reject any input glitch when the glitch
is smaller than eSPIKE. The filter shall allow pulses wider than TMIN to propagate through
the LP receiver. The related diagram shows as Figure 8.6 Input Glitch Rejection of
Low-Power Receivers. Besides, under tables list DC and AC characteristic for LP-RX.

2*TLPX
eSpike eSpike

VH
INPUT
VL

TMIN-RX

OUTPUT

Figure 8.6: Input Glitch Rejections of Low-Power Receivers

Parameter Description Min. Typ. Max. Unit Note

VIL Logic 0 input threshold - - 550 mV -
VIH Logic 1 input threshold 880 - - mV -
Table 8.9: LP Receiver DC Specifications

Parameter Description Min. Typ. Max. Unit Note

eSPIKE Input pulse rejection - - 300 [Link] 1, 2, 3
TMIN Minimum pulse width response 20 - - ns 4
VINT Peak-to-peak interference voltage - - 200 mV -
fINT Interference frequency 450 - - MHz -
Note: (1) Time-voltage integration of a spike above VIL when being in LP-0 state or below VIH when being in LP-1 state
(2) An impulse less than this will not change the receiver state.
(3) In addition to the required glitch rejection, implementers shall ensure rejection of known RF-interferers.
(4) An input pulse greater than this shall toggle the output.
Table 8.10: LP Receiver AC Specifications

Himax Confidential -P.285-

Contention can be inferred from any of the following conditions:

A. An LP high fault shall be detected when the LP transmitter is driving high and the pin
voltage is less than VIL.
B. An LP low fault shall be detected when the LP transmitter is driving low and the pad pin
voltage is greater than VILF.

Parameter Description Min. Typ. Max. Unit Note

VIHCD Logic 1 contention threshold 450 - - mV -
VILCD Logic 0 contention threshold - - 200 mV -
Table 8.11: Contention Detector DC Specifications

Himax Confidential -P.286-

This section specifies the required timings on the high-speed signaling interface independent
of the electrical characteristics of the signal. The PHY is a source synchronous interface in
the Forward direction. In either the Forward or Reverse signaling modes there shall be only
one clock source. In the Reverse direction, Clock is sent in the Forward direction and one of
four possible edges is used to launch the data.

The Master side of the Link shall send a differential clock signal to the Slave side to be used
for data sampling. This signal shall be a DDR (half-rate) clock and shall have one transition
per data bit time. All timing relationships required for correct data sampling are defined
relative to the clock transitions. Therefore, implementations may use frequency spreading
modulation on the clock to reduce EMI.

The DDR clock signal shall maintain a quadrature phase relationship to the data signal. Data
shall be sampled on both the rising and falling edges of the Clock signal. The term “rising
edge” means “rising edge of the differential signal, i.e. CP – CN, and similarly for “falling
edge”. Therefore, the period of the Clock signal shall be the sum of two successive
instantaneous data bit times. This relationship is shown in Figure 8.7.

CN
1 Data Bit Time=1UI 1 Data Bit Time=1UI
UIINST(1) UIINST(2)

1 DDR Clock Period = UIINST(1) + UIINST(2)

Figure 8.7: DDR Clock Definition

The same clock source is used to generate the DDR Clock and launch the serial data. Since
the Clock and Data signals propagate together over a channel of specified skew, the Clock
may be used directly to sample the Data lines in the receiver. Such a system can
accommodate large instantaneous variations in UI.

The allowed instantaneous UI variation can cause large, instantaneous data rate variations.
Therefore, devices shall either accommodate these instantaneous variations with appropriate
FIFO logic outside of the PHY or provide an accurate clock source to the Lane Module to
eliminate these instantaneous variations.

Himax Confidential -P.287-

Parameter Symbol Min. Typ. Max. Unit Note

(1), (2),
UI instantaneous UIINST 1 - 12.5 ns
(3)
Note: (1) This value corresponds to a minimum 80 Mbps data rate.
(2) The minimum UI shall not be violated for any single bit period, i.e., any DDR half cycle within a data burst.
(3) Maximum total bit rate is 4Gbps of 4 data lanes 24-bit data format/ 3Gbps of 4 data lane 18-bit data format/
2.67Gbps of 4 data lane 16-bit data format.
Table 8.12: HS Data Transmission Timing Parameters

The timing relationship of the DDR Clock differential signal to the Data differential signal is
shown in Figure 8.8. Data is launched in a quadrature relationship to the clock such that the
Clock signal edge may be used directly by the receiver to sample the received data.

The transmitter shall ensure that a rising edge of the DDR clock is sent during the first
payload bit of a transmission burst such that the first payload bit can be sampled by the
receiver on the rising clock edge, the second bit can be sampled on the falling edge, and all
following bits can be sampled on alternating rising and falling edges.

All timing values are measured with respect to the actual observed crossing of the Clock
differential signal. The effects due to variations in this level are included in the clock to data
timing budget.

Receiver input offset and threshold effects shall be accounted as part of the receiver setup
and hold parameters.

Reference Time

TSETUP THOLD

0.5UIINST +
TSKEW

1 UIINST

TCLKp
Figure 8.8: Data to Clock Timing Definitions

Himax Confidential -P.288-

The Data-Clock timing specifications are shown in Table 8.13. Implementers shall specify a
value UIINST,MIN that represents the minimum instantaneous UI possible within a
High-Speed data transfer for a given implementation. Parameters in Table 8.13 are specified
as a part of this value. The skew specification, TSKEW[TX], is the allowed deviation of the
data launch time to the ideal ½ UIINST displaced quadrature clock edge. The setup and hold
times, TSETUP[RX] and THOLD[RX], respectively, describe the timing relationships between
the data and clock signals. TSETUP[RX] is the minimum time that data shall be present
before a rising or falling clock edge and THOLD[RX] is the minimum time that data shall
remain in its current state after a rising or falling clock edge. The timing budget specifications
for a receiver shall represent the minimum variations observable at the receiver for which the
receiver will operate at the maximum specified acceptable bit error rate.

The intent in the timing budget is to leave 0.4*UIINST, i.e. ±0.2*UIINST for degradation
contributed by the interconnect.

Parameter Symbol Min. Typ. Max. Unit Note

Data to Clock Setup Time [Receiver] TSETUP[RX] 0.15 - - UIINST 1
Clock to Data Hold Time [Receiver] THOLD[RX] 0.15 - - UIINST 1
Note: (1) Total setup and hold window for receiver of 0.3*UIINST.
(2) 0.15UI is only for reference, related to the signal jitter caused by the transmittion path, this spec need to
check on panel performance to fine tune.
Table 8.13: Data to Clock Timing Specifications

Data at TX side

Transmittion

Data at RX side

Jitter
Figure 8.9: Skew window of transmittor and receiver

Himax Confidential -P.289-

VS
VFP VS VBP VFP

DB[23:0]
VBL VDISP
DE
VP

DSI V H
B S B S B
H H
B
H H H H V
B S B S B S B
S B S S B RGB date B S B RGB date
Packets P S P S P
S P S
P
S P P S P P S P S P S P

Figure 8.10: Vertical Timings for RGB I/F

Vertical Resolution=528+8xNL(VDD1=1.8V, VDD3=2.8V, T A=25°C)

Item Symbol Condition Min. Typ. Max. Unit
534+8xN
Vertical cycle VP - L
- - Line
Vertical low pulse width VS - 2 - Note(1) Line
Vertical front porch VFP - 2 - - Line
Vertical back porch VBP - 2 - Note(1) Line
Vertical data start point - VS+VBP 4 - Note(1) Line
Vertical blanking period VBL VS+VBP+VFP 6 - - Line
528+8xN
Vertical active area - VDISP - L
- Line
Vertical Refresh rate VRR - - 60 - Hz

Note: (1) The VS and VBP pulse width are related to GSP and GCK timing. The GSP and GCK must be set at
corresponding position for LCD normal display.

Table 8.14: Vertical Timings for RGB I/F

Himax Confidential -P.290-

DSI Packets BP HSS BP Packed Pixel Stream BP HSS BP

(24-bit RGB)

HFP HS HBP HFP

HS
HDISP

DB[23:0] Invalid data Valid data Invalid data

PCLK
(PCLK depend on DSI
clock and data lanes)

Figure 8.11: Horizontal Timing for DSI Video mode I/F

Horizontal Resolution=H_RES(1080/1024/960/900/800/720) pixels (VDD1=1.8V, VDD3= 2.8V,

TA=25°C)
Item Symbol Condition Min. Typ. Max. Unit
HS cycle HP - H_RES+15 - - DCK
HS low pulse width HS - 5 - - DCK
Horizontal back porch HBP - 5 - - DCK
Horizontal front porch HFP - 5 - - DCK
Horizontal data start point - HS+HBP 10 - - DCK
Horizontal blanking period HBLK HS+HBP+HFP 15 - - DCK
Horizontal active area HDISP - - H_RES - DCK

Table 8.15: Horizontal Timings for DSI Video mode I/F

Himax Confidential -P.291-

Shorter than 5µs

tRESW

RESX
tREST

Initial Condition
Internal Status Normal Operation Resetting
(Default for H/W reset)

Figure 8.12: Reset input timing

Spec.
Symbol Parameter Related pins Unit Note
Min. Typ. Max.
(1)
tRESW Reset low pulse width RESX 10 - - µs -
(2)
tREST Reset complete time - - - 50 ms -
Note: (1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the
table below.
RESX Pulse Action
Shorter than 5 µs Reset Rejected
Longer than 10 µ s Reset
Between 5 µ s and 10 µ s Reset Start

(2) During Reset Complete Time, OTP will be latched to internal register during this period. This loading is done
every time when there is H/W reset complete time (tREST) within 50ms after a rising edge of RESX.
(3) Spike Rejection also applies during a valid reset pulse as shown below:

Table 8.16: Reset timing

Himax Confidential -P.292-

Himax Confidential -P.293-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2015

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