9052 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO.

9, SEPTEMBER 2022

A Novel Nonisolated GaN-Based Bidirectional

DC–DC Converter With High Voltage Gain
Longyang Yu , Student Member, IEEE, Laili Wang , Senior Member, IEEE,
Chengzi Yang , Student Member, IEEE, Lei Zhu , Student Member, IEEE,
Yongmei Gan , Member, IEEE, and Hong Zhang

Abstract—A nonisolated bidirectional dc–dc converter is topologies achieving a high conversion ratio can be divided into
proposed for energy storage systems in this article. The two categories: 1) isolated topologies; 2) nonisolated topologies.
proposed converter is composed of three active switches, The isolated bidirectional topologies utilize a high-frequency
two synchronous rectifiers, two clamping capacitors, and
two inductors. The proposed converter has advantages of transformer to achieve a high voltage conversion ratio. There-
being a simple structure, a fewer number of components, fore, their voltage gain of these converters mainly depend on the
a common ground, lower voltage stress, and wide voltage turn ratio of the transformer utilized in full-bridge or half-bridge.
gain range. Compared with the conventional buck convert- As one of the most popular isolated bidirectional topologies, the
ers, the novel converter triples the effective duty cycle and
CLLC converter [3], [4] is a very promising candidate, because
lowers voltage stresses across the active switches. A 300-
W/500-kHz GaN-based experimental prototype is built and it can achieve both zero-voltage switch operation of primary side
tested to verify the correctness and validity, demonstrating and zero-current switch operation of secondary side. However,
a peak efficiency of 94.54% in step-down mode and a peak this kind of resonant converters are relatively complex in terms of
efficiency of 94.88% in step-up mode. control strategy, drive scheme of the synchronous rectifier, and
Index Terms—Gallium nitride, high voltage gain, low volt- parameter design. The bidirectional dc–dc flyback topologies
age stress, switched-capacitor. [5] have simple structure and can be controlled easily, but if
the energy of the leakage inductance cannot be recycled, active
switches will suffer from high voltage stress and large voltage
I. INTRODUCTION spike. In order to recycle the energy of the leakage inductance
HE development of renewable energy, such as wind energy and reduce voltage stresses across active switches, the clamp
T and solar energy via photovoltaic, is an inevitable trend in
future since fossil fuel reserve will be depleted and environmen-
technology is applied to the flyback topologies, which makes the
structure and control more complex. In addition, another popular
tal protection is required by policy. Renewable energy storage topology is called the dual active bridge (DAB) [6], [7], which
systems have been widely used in numerous applications, such as also has a relative simple structure and control compared with
uninterrupted power supplies, satellite, and microgrids [1]–[2]. the CLLC converter. However, it needs eight active switches
In order to charge and discharge the battery in these applications, to stay the steady-state operation. Hence, DAB is difficult to
the bidirectional dc–dc topologies, which have bidirectional implement a high efficiency due to the switching loss caused by
capabilities of power transfer and conversion, are required and many active switches and the existing circulating power loss [8].
play an important role in these applications. A challenge for Nonisolated bidirectional dc–dc topologies have simpler
energy storage systems is that the voltage of low side is very structure and control strategy, higher efficiency, and higher
low, and the voltage of high side is very high. Therefore, power density than isolated topologies. Therefore, the noniso-
the bidirectional dc–dc topologies with high step-down/step-up lated bidirectional dc–dc converters with high voltage gain are
voltage gain are desired for energy storage systems to connect promising candidates for these applications. The conventional
the higher side of dc bus and the lower side of the battery. These buck–boost converters due to simple structure and low cost
are widely applied to low voltage applications. However, the
disadvantages of narrow voltage conversion ratio, high voltage
Manuscript received March 26, 2021; revised July 8, 2021 and August stress, and extremely small duty cycle make them unsuitable
21, 2021; accepted August 31, 2021. Date of publication September 30, for these energy storage systems. The bidirectional three-level
2021; date of current version April 1, 2022. This work was supported by
the Science and Technology Plan of Guangdong Province, China under dc–dc converter can achieve low voltage stress, and is half
Grant 2017B010112002. (Corresponding author: Laili Wang.) that of the conventional buck–boost converters. Unfortunately,
The authors are with the State Key Laboratory of Electrical Insulation its voltage gain is identical with the conventional buck–boost
and Power Equipment, Xi’an Jiaotong University, Xi’an 710049, China
(e-mail: yulongyang530@[Link]; llwang@[Link]; converters. The nonisolated topologies using coupled inductor
lemonyang@[Link]; jasmine@[Link]; ymgan@mail. techniques [9]–[12] are an important research orientation, in
[Link]; mhzhang@[Link]). which high voltage gain can be achieved by turn ratio of coupled
Color versions of one or more figures in this article are available at
[Link] inductors. Nevertheless, its disadvantage like flyback topologies
Digital Object Identifier 10.1109/TIE.2021.3113015 is that active switches suffer from large voltage spike caused

0278-0046 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See [Link] for more information.

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YU et al.: NOVEL NONISOLATED GAN-BASED BIDIRECTIONAL DC–DC CONVERTER WITH HIGH VOLTAGE GAIN 9053

by the leakage inductance of coupled inductors. These non-

isolated converters based on switched-inductor [13]–[15] can
achieve high voltage gain (high voltage gain is obtained by the
charge and discharge of multiple inductors in different series and
parallel combinations). However, the use of multiple inductors
will degrade the power density of the converters. The converter
based on series capacitor in [16] can extend the duty cycle, but
it causes imbalance of two-phase inductor currents. Although
the converter based on series capacitor and coupled inductor in
Fig. 1. Proposed topology.
[17] on the basis of [16] can achieve soft-switching technique,
the imbalance problem of two-phase inductor currents is still
not solved, which will degrade efficiency and output current it can also be divided into D ≤ 0.5 and D > 0.5 according
ripple. Besides, some transformerless converters [18]–[21] are to the duty cycle. It can be noted that whether the converter is
also developed to achieve high voltage gain, extend duty cycle, used in step-down mode or step-up mode depends on the input
and low voltage stress across the active switches, but they have no source and load location and cannot operate in both modes. The
common ground. The low voltage and high voltage side grounds active switches S1 , S2 , and S3 are main switches and the active
are connected by one or two active switches. Therefore, there switches S4 and S5 are synchronous rectifiers (SRs) under the
is a high-frequency PWM between the two grounds, which will duty cycle D ≤ 0.5 in the step-down mode. The active switches
result in electromagnetic interference problem and limit their S1 and S2 are main switches and the active switches S3 , S4 , and
applications. The switched-capacitor converters [21]–[25] due S5 are SRs under the duty cycle D > 0.5 in the step-down mode.
to simple structures and control strategies are considered to The active switches S4 and S5 are main switches and the active
be an effective solution for these applications. Smaller size, switches S1 , S2 , and S3 are SRs under the duty cycle D > 0.5 in
lighter weight, and higher power density and efficiency are the step-up mode. The active switches S3 , S4 , and S5 are main
advantages due to no magnetic components. In these converters, switches and the active switches S1 and S2 are SRs under the
the clamping capacitors are regarded as energy storage elements, duty cycle D ≤ 0.5 in the step-up mode. The operating principles
and they utilize different charging and discharging paths to of the step-down mode and the step-up mode are similar, thus,
transfer energy to extend the duty cycle. the step-down mode of the proposed converter is only analyzed.
The novelty of this article is to present a bidirectional dc–dc To simplify the steady-state analysis of the proposed converter,
converter with high voltage gain. The high voltage gain can be some assumptions are taken into account as follows.
achieved by using two clamping capacitors. Moreover, due to 1) All power semiconductors and energy storage compo-
the voltage division of two clamping capacitors, the low voltage nents of the converter are considered as ideal.
stresses across active switches are achieved in the proposed 2) Dead time can be ignored between these active switches
converter. Subsequently, the proposed converter employing GaN during one steady-state switching period.
devices reduces switching loss and then the high efficiency can 3) Two clamping capacitances are large enough to imple-
be achieved. In addition, the proposed converter has a wide ment the constant voltage.
voltage gain range. More importantly, the number of components
in the proposed converter is the fewest compared with [25] and
[27]. At present, the number of components in the proposed A. D ≤ 0.5
converter is the lowest level when the voltage gain equals to The typical waveforms (D ≤ 0.5) at continuous conduction
D/3. mode (CCM) are shown in Fig. 2(a), and the proposed topology
The proposed converter is further studied and analyzed on the can be divided into four modes during one switching period as
basis of the conference [26] in this article. This article can be shown in Fig. 3. The operating principle is presented as follows.
arranged as follows. The proposed converter is introduced and its Mode 1 [t0 < t < t1 ]: During this interval, switches S1 , S3 ,
operating principle is presented in detail in Section II. Section III and S4 are turned ON, while switches S2 and S5 are turned OFF.
discusses the steady-state analysis of the proposed converter, The current flow paths of the proposed topology are presented in
including voltage gain, voltage stress across active switches, Fig. 3(a). It can be seen from Fig. 3(a) that the inductor current
current stress through active switches, and performance compar- iL1 freewheels through the SR S4 , and L1 is releasing stored
ison with other similar topologies. The experimental results are energy to the inductor L2 and the output load RL . The inductor
shown in Section IV. Finally, Section V concludes this article. current iL2 provides three separate current paths through L1 ,
C2 , and Vin . The first current flow path starts from C2 , through
S3 , L2 , Co , RL , and S4 and then backs to C2 . Hence, the stored
II. OPERATING PRINCIPLE energy of the clamping capacitor C2 is discharged to the inductor
The proposed converter is shown in Fig. 1, which is composed L2 and the output load RL . The second current flow path starts
of five active switches S1 , S2 , S3 , S4 , and S5 ; two clamping from Vin , through S1 , C1 , L2 , Co , and RL , and then backs to Vin .
capacitors C1 and C2 ; and two inductors L1 and L2 . The pro- The clamping capacitor C1 , the inductor L2 , and the output load
posed converter is a bidirectional dc–dc converter, which can RL are charged by Vin . The third current flow path starts from
be divided into step-down mode and step-up mode. Meanwhile, L1 , through L2 , Co , RL , and S4 , and then backs to L1 . Thus, the

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9054 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 9, SEPTEMBER 2022

inductor current iL2 is increasing and the inductor current iL1 is

decreasing
Vin = VC1 + VL2 + Vo (1)
Vin = VC1 − VL1 (2)
Vin = VC1 + VC2 . (3)
Mode 2 [t1 < t < t2 ]: During this interval, the switches S1 and
S3 are turned OFF, while the switch S5 is turned ON. The current
flow paths of the proposed topology are presented in Fig. 3(b).
It can be seen from Fig. 3(b) that the inductor current iL1 keeps
constant current. The inductor current iL2 freewheels through
the SR S5 , and L2 starts releasing stored energy to the output
load RL . Thus, the inductor current iL2 are decreasing linearly
VL1 = 0 (4)
VL2 = − Vo . (5)
Mode 3 [t2 < t < t3 ]: During this interval, the switch S2 is
turned ON and the switch S5 is still turned on, while the switch S4
is turned OFF. The current flow paths of the proposed topology
are presented in Fig. 3(c). It can be seen from Fig. 3(c) that
the inductor current iL2 freewheels through the SR S5 , and L2
is releasing stored energy to the output load RL . The inductor
current iL1 provides one separate current path through C1 . The
path starts from C1 , through S2 , C2 , and L1 and then backs to
C1 . Therefore, the stored energy of C1 is discharged to L1 and
Fig. 2. Typical waveforms of the proposed topology at CCM. C2 . The inductor L1 and the clamping capacitor C2 are charged
(a) D ≤ 0.5. (b) D > 0.5. by C1 . Thus, the inductor current iL1 is increasing, while the
inductor current iL2 is decreasing

VC1 = VC2 + VL1 (6)

VL2 = − Vo . (7)
Mode 4 [t3 < t < t4 ]: For this interval, the corresponding
current flow paths are identical with mode 2.

B. D > 0.5
The typical waveforms (D > 0.5) at CCM are presented in
Fig. 2(b), and the proposed topology can also be divided into
four modes during one switching period as shown in Fig. 4. The
operating principle is presented in detail as follows.
Mode 1 [t0 < t < t1 ]: During this interval, the switches S1 , S3 ,
and S4 are turned ON, while the switches S2 and S5 are turned OFF.
The current flow paths of the proposed topology are presented in
Fig. 4(a). It can be seen from Fig. 4(a) that the inductor current
iL1 freewheels through the SR S4 , and L1 is releasing stored
energy to the inductor L2 and the output load RL . The inductor
current iL2 provides three separate current paths through L1 ,
C2 , and Vin . The first current flow path starts from C2 , through
S3 , L2 , Co , RL , and S4 , and then backs to C2 . Hence, the stored
energy of the clamping capacitor C2 is discharged to the inductor
L2 and the output load RL . The second current flow path starts
Fig. 3. Current flow paths of the proposed converter under D ≤ 0.5.
(a) Mode 1. (b) Modes 2 and 4. (c) Mode 3.
from Vin , through S1 , C1 , L2 , Co , and RL , and then backs to
Vin . The capacitor C1 , the inductor L2 , and the output load RL
are charged by Vin . The third current flow path starts from L1 ,

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YU et al.: NOVEL NONISOLATED GAN-BASED BIDIRECTIONAL DC–DC CONVERTER WITH HIGH VOLTAGE GAIN 9055

inductor current iL2 is decreasing

VC1 = VC2 + VL1 (13)
VL2 = −V0 . (14)
Mode 4 [t3 < t < t4 ]: For this interval, the corresponding
current flow paths are identical with mode 2.

III. STEADY-STATE ANALYSIS

The steady-state analysis of the proposed converter is pre-
sented in this section. It contains voltage gain derivation, voltage
stresses across active switches, current stresses through switches
and performance comparison.

A. Voltage Gain (Step-Down Mode)

1) D ≤ 0.5: According to mode 1 and mode 3 in Fig. 3, using
the volt–second balance principle on inductors L1 and L2 , the
following voltage equations can be derived:
D (VC1 − Vin ) + D (VC1 − VC2 ) = 0 (15)
D (Vin − VC1 − Vo ) + (1 − D) (−Vo ) = 0. (16)
Combining (3), (15), and (16), the clamping capacitors C1
Fig. 4. Current flow paths of the proposed converter under D > 0.5. and C2 and the voltage gain M of the proposed converter can be
(a) Mode 1. (b) Modes 2 and 4. (c) Mode 3. written as follows:
2
VC1 = Vin (17)
through L2 , Co , RL , and S4 , and then backs to L1 . Thus, the 3
inductor current iL2 is increasing, while the inductor current iL1 1
VC2 = Vin (18)
is decreasing 3
Vo D
Vin = VC1 + VL2 + Vo (8) M= = . (19)
Vin 3
Vin = VC1 − VL1 (9) 2) D > 0.5: According to mode 1 and mode 3 in Fig. 4, using
the volt–second balance principle on inductors L1 and L2 , the
Vin = VC1 + VC2 . (10)
following voltage equations can be derived:
Mode 2 [t1 < t < t2 ]: During this interval, the switches S3 and D (VC1 − VC2 ) + (1 − D) (VC1 − Vin ) = 0 (20)
S4 are turned OFF, while the switch S2 is turned ON. The current
flow paths of the proposed topology are presented in Fig. 4(b). D (Vin − VC1 − Vo ) + (1 − D) (−Vo ) = 0. (21)
It can be seen from Fig. 4(b) that the inductor currents iL1 and Combining (10), (20), and (21), the clamping capacitors C1
iL2 are charged by Vin . Thus, the inductor currents iL1 and iL2 and C2 and the voltage gain M of the proposed converter can be
are increasing linearly written as follows:
1
VC1 = VC2 + VL1 (11) VC1 = Vin (22)
1+D
Vin = VC1 + VL2 + Vo . (12) D
VC2 = Vin (23)
1+D
Mode 3 [t2 < t < t3 ]: During this interval, the switch S5 is
turned ON and the switch S2 is still turned ON, while the switch S1 Vo D2
M= = . (24)
is turned OFF. The current flow paths of the proposed topology Vin 1+D
are presented in Fig. 4(c). It can be seen from Fig. 4(c) that
the inductor current iL2 freewheels through the SR S5 , and L2 B. Voltage Gain (Step-Up Mode)
is releasing stored energy to the output load RL . The inductor 1) D > 0.5: According to mode 1 and mode 3 in Fig. 3,
current iL1 provides one separate current path through C1 . The using the volt–second balance principle on inductors L1 and L2 ,
path starts from C1 , through S2 , C2 , and L1 , and then backs to the following voltage equations can be derived:
C1 . Therefore, the stored energy of C1 is discharged to L1 and
C2 . The inductor L1 and the clamping capacitor C2 are charged DVc2 + D (VC1 + VC2 ) + (1 − 2D) (VC2 − VC1 ) = 0
by C1 . Thus, the inductor current iL1 is increasing, while the (25)

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9056 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 9, SEPTEMBER 2022

Vin
Vds3 = (38)
1+D
D (Vin − VC2 ) + DVin
Vin
+ (1/2 − D) (Vin + VC1 − Vo ) = 0. Vds4 = (39)
1+D
(26)
DVin
Vds5 = . (40)
The voltage gain M of the proposed converter can be written 1+D
as follows:
Vo 2−D D. Current Stress of Power Semiconductors
M= = . (27)
Vin (1 − D)2 1) D ≤ 0.5: It can be seen from Fig. 1 that the load current Io
2) D ≤ 0.5: According to mode 1 and mode 3 in Fig. 4, using is transferred from the average inductor current IL2 . And their
the volt–second balance principle on inductors L1 and L2 , the relationship can be described by (41) in terms of ampere–second
following voltage equations can be derived: balance principle on output capacitor Co

(1 − D) VC2 + (1 − D) (VC2 − VC1 ) = 0 (28) Io = IL2 . (41)

DVin + (1 − D) (Vin − VC2 ) = 0. (29) Meanwhile, the average inductor currents IL1 and IL2 can
be given by utilizing ampere–second balance principle on the
The voltage gain M of the proposed converter can be written
capacitors C1 and C2 , thus yielding
as follows:

Vo 3 (IL2 − IL1 − IC2 )DT During mode 1
M= = . (30) QC1 = (42)
Vin 1 − D IL1 DT During mode 3

(IL2 − IL1 − IC1 )DT During mode 1
C. Voltage Stress of Power Semiconductors QC2 = (43)
IL1 DT During mode 3
In order to simplify analysis of voltage stresses across active
switches, voltage ripples on clamping capacitors C1 and C2 can IL2 = 3IL1 . (44)
be ignored.
Substituting (44) into (41), the average inductor currents IL1
1) D ≤ 0.5: The voltage stress across every switch in one
and IL2 can be derived as follows:
steady-state switching period can be given as follows:
1
Vin IL1 = Io (45)
Vds1 = (31) 3
3
2Vin IL2 = Io . (46)
Vds2 = (32)
3 According to Fig. 3, (45), and (46), the current stresses
2Vin through S1 , S2 , S3 , S4 , and S5 can be described as follows:
Vds3 = (33)
3
Vin Id1 = iL1 (47)
Vds4 = (34)
3 Id2 = iL1 (48)
Vin
Vds5 = . (35) Id3 = iL1 (49)
3
Id4 = iL2 − iL1 (50)
Note that from (34) to (35) that voltage stresses across
switches S4 and S5 reach one-third of the input voltage. Thus, Id5 = iL2 . (51)
MOSFETs with lower voltage rating can be employed to reduce
conduction losses and switching losses. It can be seen from (31) Based on (22)–(26), it can be noted that the current stresses
to (33) that the maximum voltage stresses on active switches S2 of S4 and S5 are larger than that of S1 , S2 , and S3 . Thus, higher
and S3 reach two-third of the input voltage. The voltage stress on rated drain current MOSFETs can be employed for SRs S4 and
the switch S1 is Vin /3. Hence, lower voltage rating MOSFETs S5 . Lower rated drain current MOSFETs can be employed for
with lower FOM can be employed to further reduce conduction switches S1 , S2 , and S3 .
losses and switching losses. 2) D > 0.5: The average inductor currents IL1 and IL2 can
2) D > 0.5: The voltage stress across every switch in one be derived by using ampere–second balance principle on the
steady-state switching period can be given as follows: capacitors C1 and C2 , thus yielding
⎧
Vds1 =
DVin
(36) ⎨ (IL2 − IL1 − IC2 )(1 − D)T During mode 1
1+D QC1 = (IL2 − IL1 )(2D − 1)T During mode 2 and 4
⎩
Vin IL1 (1 − D)T During mode 3
Vds2 = (37) (52)
1+D

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YU et al.: NOVEL NONISOLATED GAN-BASED BIDIRECTIONAL DC–DC CONVERTER WITH HIGH VOLTAGE GAIN 9057

TABLE I
COMPARISON OF THE PROPOSED TOPOLOGY AND OTHER CONVERTERS

⎧
⎨ (IL2 − IL1 − IC1 )(1 − D)T During mode 1
QC2 = IL1 (2D − 1)T During mode 2 and 4 (53)
⎩
IL1 (1 − D)T During mode 3
3 − 2D
IL2 = IL1 = Io . (54)
2 − 2D
Referring to Fig. 4 and (54), the current stresses through S1 ,
S2 , S3 , S4 , and S5 can be described as follows:

Id1 = Io (55)
Id2 = iL1 (56)
2DIo
Id3 = (57)
(3 − 2D)
2Io
Id4 = (58)
(3 − 2D)
Id5 = iL2 . (59)

E. Performance Comparison
The comparison investigation among the proposed converter
and the other similar converters is implemented to evaluate Fig. 5. Voltage gain versus the duty cycle. (a) Step-down gain.
(b) Step-up gain.
performance of the proposed converter. For the sake of fair
comparison, these dc–dc converters employing coupled inductor
and transformer are excluded, since these converters include
the parameter of turn ratio. However, the proposed converter gain of the proposed converter is higher than the converters
belongs to a nonisolated dc–dc converter based on switched- in [20]–[22]. Although the voltage gain in [23] is higher than
capacitor technique, in which the parameter of turn ratio is the proposed one when duty cycle D < 0.32, both the current
not included. These recently published topologies based on ripple and voltage stress in [23] are larger, which limit low
switched-capacitor technique are compared with the proposed voltage high current applications. However, it can be seen from
converter as shown in Table I. The voltage gain among the Fig. 5(b) that the step-up gain of the proposed converter is
proposed converter and the other similar converters are shown the highest compared with similar topologies. The conventional
in Fig. 5. Fig. 5(a) shows step-down gain and Fig. 5(b) shows bidirectional buck–boost converter is the simplest topology, but
step-up gain. It can be seen from Fig. 5(a) that the step-down its voltage gain is the lowest, and voltage stress and current

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9058 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 9, SEPTEMBER 2022

TABLE II
SPECIFICATIONS AND COMPONENTS OF THE CONVERTER

stress are very high. In the proposed configuration, the voltage

stress on SRs is lower than other topologies. The efficiency of
the proposed configuration is at medium level compared with
the other topologies. The converters in [20] and [27] have very
high efficiency and the current ripples are also low due to its
interleaving structure. However, the input and output sides do
not share a common ground, which will limit the converter Fig. 6. 300 W GaN-based experimental prototype and platform.
(a) Prototype. (b) Platform.
applied in many applications. The current ripple can be divided
into large, medium, and low. The resonant converters such as
CLLC and LLC converters belong to large current ripple level.
The converters with interleaving structure belong to low current
ripple level. The current ripple in the proposed converter is at
an intermediate level under same filter inductor and capacitor
parameters.
On the number of components, although the cascaded buck
converter has fewer active switches and fewer component courts
than the proposed converter, the voltage stresses of active
switches in the first stage is very high. The proposed converter
is at low level compared with the other converters. The voltage Fig. 7. Block diagram of the control system.
gain of the converters in [20]–[22] is D/2, and counts of active
switches in [20] and [22] are four, however, counts of active
switches in [21] is five (the component counts are the same as The block diagram of control strategy is shown in Fig. 7. This
the proposed converter). The voltage gain of the converters in block diagram of control strategy like conventional buck–boost
[24] and [25] is D/3 (the voltage gain is same as the proposed converters is very simple, since it has only one proportional
converter), and counts of active switches in [24], [25], and [27] integral (PI) controller to control the output voltage. The output
are five, eight, and five, respectively. In addition, the proposed voltage is sensed, conditioned by sampling circuit, and then sub-
converter has a wide voltage gain range compared with the range tracts the reference voltage. Then the error signal is compensated
in [24] and [25] in Fig. 5. The number of components in the by utilizing a digital PI controller. Its output signal is sent to the
proposed converter and the converters in [24] are identical and internal PWM module of the DSP28335 by a digital saturation
are the fewest. At present, the number of components in the block.
proposed converter is lowest level when the voltage gain equals
to D/3.
A. D ≤ 0.5
The input voltage is 400 V and the output voltage is 48 V.
IV. EXPERIMENTAL VERIFICATIONS Therefore, according to (19), the duty cycle can be calculated as
In order to verify the performance of the proposed topology, a
300 W prototype which operates at 500 kHz switching frequency 3Vo
D = = 0.36. (60)
is built and tested as shown in Fig. 6. The GaN device GS66508B Vin
from GaN systems is employed to implement this circuit oper-
ated in high-frequency condition. The detailed parameters of the The inductance can be designed by using the integral form of
prototype is listed in Table II. the current equation on inductors L1 and L2 , the current ripples

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YU et al.: NOVEL NONISOLATED GAN-BASED BIDIRECTIONAL DC–DC CONVERTER WITH HIGH VOLTAGE GAIN 9059

of inductors L1 and L2 can be derived by

 DTs
1 Vin D
iL1 (DTs ) = iL1 (0) + VL1 (t)dt ⇒ ΔiL1 =
L1 0 3L1 fs
(61)
 DTs
1
iL2 (DTs ) = iL2 (0) + VL2 (t)dt ⇒ ΔiL2
L2 0
Vin D(1 − D) Fig. 8. Experimental waveforms of voltage stresses. (a) Voltage
= . (62)
3L2 fs stresses across active switches. (b) Voltage stresses across active SRs.
The current ripple is 40%Io , thus, the inductance value can be
described as follows:

Vin D
L1 = 3Δi L1 fs
= 24 μF
Vin D(1−D) . (63)
L2 = 3ΔiL2 fs = 15.36 μF
Hence, the inductance values L1 and L2 of this prototype can
be determined as follows:

Vin D
L1 = 3Δi L1 fs
= 22 μF
Vin D(1−D) . (64)
L2 = 3ΔiL2 fs = 10 μF Fig. 9. Experimental waveforms of the voltage on clamping capacitors
C1 and C2 .
According to (17) and (18), the voltage across the clamping
capacitors C1 and C2 can be described by charge and discharge
balance principle of capacitors, and desirable voltage ripple
ΔVC
CΔVC = q (65)
where q represents electric charge. The capacitances C1 and C2
can be calculated by (42) and (43)
DIo
C1 = C2 = C ≥ . (66)
3ΔVC fs
The voltage ripple is set to be 2 V, hence, capacitances C1 and Fig. 10. Experimental waveforms of inductor currents iL1 and iL2 .
C2 can be determined as follows: (a) Step-down mode. (b) Step-up mode.

C1 = C2 = 1.2 μF. (67)

The output filter capacitance Co depends on the output current The maximum voltage stresses on SRs S4 and S5 reach 133 V,
ripple Δio and the output voltage ripple ΔVo . Its capacitance can which is equivalent to one-third of Vin . The respective voltage
be designed as follows: stress can be predicted by (34) and (35). The experimental
waveforms of the voltage on clamping capacitors VC1 and VC2
Δio
Co ≥ . (68) are presented in Fig. 9. VC1 equivalents to two-thirds of the
8fs ΔVo input voltage, which can be predicted with (17) and is kept
Hence, the output filter capacitance value Co of this prototype constant. Meanwhile, VC2 equivalents to one-third of Vin , which
can be determined as follows: can be predicted with (18) and is kept constant. The experimental
waveforms of the inductor currents iL1 and iL2 are presented
Co = 2 μF. (69)
in Fig. 10. Fig. 10(a) is step-down mode and Fig. 10(b) is
Since the series equivalent resistance effect of the output step-up mode. The current ripples ΔiL1 and ΔiL2 are 4 and 5
capacitance is not considered, the capacitance value of the A, respectively, which follows the expressions in (55) and (56).
prototype is set to 88 μF. The experimental waveforms of measured step-load response
Experimental waveforms of voltage stresses on active by using a single-voltage closed-loop controller are presented
switches are presented in Fig. 8(a). Note that the maximum in Figs. 11 and 12. Fig. 11(a) presents loading transient of 4 A
voltage stresses on switches S2 and S3 reach 266 V, which are and Fig. 11(b) presents unloading transient of 4 A. Fig. 12(a)
equal to two-thirds of Vin . The maximum voltage stress on the shows 2–7 A loading transient performance of voltage on the
switch S1 reaches 133 V, which equivalents to one-third of Vin . clamping capacitors C1 and C2 , and Fig. 12(b) shows 7–2 A un-
Voltage stresses on active switches S2 and S3 are predicted by loading transient performance, demonstrating that the proposed
the expressions (32) and (33) and the maximum voltage stress on topology in step-down mode has better transient performance for
the switch S1 is predicted by the expression (31). The waveforms load change. Fig. 13 shows transient performance of stepping
of voltage stresses on SRs S4 and S5 are presented in Fig. 8(b). the input voltage when D ≤ 0.5. Fig. 13(a) shows input voltage

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9060 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 9, SEPTEMBER 2022

Fig. 15. Experimental waveforms of voltage stresses. (a) Voltage

Fig. 11. Experimental waveforms of 4 A load transients. (a) 0.5–4.5 A
stresses across active switches. (b) Voltage stresses across SRs.
loading transient. (b) 4.5–0.5 A unloading transient.

Fig. 12. Voltages on the clamping capacitors C1 and C2 of 5 A load

transients under D ≤ 0.5. (a) 2–7 A loading transient. (b) 7–2 A unload- Fig. 16. Experimental waveforms of the voltage on clamping capaci-
ing transient. tors C1 and C2 .

loss distribution of components of this converter are presented

in Fig. 14(b). It should be noted that conduction losses and
switching losses are dominant loss factors.

B. D > 0.5
In order to verify the operating principle of the proposed
converter under D > 0.5, the specification is set to test this
prototype. The input voltage is set to be 400 V and the output
Fig. 13. Experimental waveforms of 100 V input voltage transients
under D ≤ 0.5. (a) Input voltage 300 to 400 V. (b) Input voltage 400
voltage is set to be 100 V. Therefore, according to (24) the voltage
to 300 V. gain can be calculated as follows:
D = 0.64. (70)
Experimental waveforms of voltage stresses on active
switches are presented in Fig. 13(a). The experimental wave-
forms of voltage stresses on SRs S4 and S5 are presented in
Fig. 13(b). The experimental waveforms of the voltage VC1
and VC2 on clamping capacitors are presented in Fig. 14. The
experimental waveforms of the inductor currents iL1 and iL2 are
presented in Fig. 15, Fig. 15(a) is step-down mode and Fig. 15(b)
is step-up mode. It should be noted that the experimental results
Fig. 14. Efficiency curve and power loss distributions under D ≤ 0.5. are consistent with theoretical analysis. The experimental wave-
(a) The measured efficiency curve. (b) Calculated power loss distribu-
tions for the converter under full load condition.
forms of the voltage on clamping capacitors VC1 and VC2 are
presented in Fig. 16. VC1 equivalents to two-thirds of the input
voltage, which can be predicted with (17) and is kept constant.
steps from 300 to 400 V, and Fig. 13(b) shows input voltage Meanwhile, VC2 equivalents to one-third of Vin, which can
steps from 400 to 300 V. be predicted with (18) and is kept constant. The experimental
Fig. 14(a) shows the measured efficiency curve of 300 W waveforms of the inductor currents iL1 and iL2 are presented in
prototype in the step-down mode and the step-up mode under Fig. 17. Fig. 17(a) is step-down mode and Fig. 17(b) is step-up
D ≤ 0.5. The maximum efficiency of 94.54% can be obtained mode. The current ripples and are 4 A and 5 A, respectively,
when the output power reaches 135 W in the step-down mode, which follows the expressions in (55) and (56). The performance
and the peak efficiency of 94.88% can be obtained when the under the load transients when D > 0.5 are shown in Figs. 18,
output power reaches 146 W in the step-up mode. The power 19, and 20. Fig. 18 shows transient performance of stepping the

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YU et al.: NOVEL NONISOLATED GAN-BASED BIDIRECTIONAL DC–DC CONVERTER WITH HIGH VOLTAGE GAIN 9061

Fig. 17. Experimental waveforms of inductor currents iL1 and iL2 .

(a) Step-down mode. (b) Step-up mode.
Fig. 21. Efficiencies of the proposed converter in step-up and step-
down modes under different voltage gain range (Vhigh = 400 V, Vlow =
30–150 V, Po = 300 W).

Fig. 18. Experimental waveforms of 100 V input voltage transients

under D > 0.5. (a) Input voltage 300 to 400 V. (b) Input voltage 400
to 300 V.

Fig. 22. Efficiency curve and power loss distributions under D > 0.5.
(a) The measured efficiency curve. (b) Calculated power loss distribu-
tions for the converter under full load condition.

(shown in Fig. 21), when the high-side voltage Vhigh is 400 V and
the low-side voltage Vlow varies from 30 to 150 V or 150 to 30
V continuously. According to Fig. 21, the measured efficiencies
range from 90.08% to 94.39% in the step-up mode and from
Fig. 19. Experimental waveforms of 5 A load transients under D > 0.5. 90.32% to 94.46% in the step-down mode when output power
(a) 2–7 A loading transient. (b) 7–2 A unloading transient. is 300 W. It is seen from Fig. 21 that the efficiencies when Vlow
is at 70–110 V is slightly low, which results from the higher
loss caused by the critical point between two modes (D ≤ 0.5
and D > 0.5). The efficiencies is above 90% in the step-up and
step-down modes under different voltage gain, which verifies
wide voltage gain range of the proposed converter.
Fig. 22(a) shows the measured efficiency curve of 300 W
prototype in the step-down mode and the step-up mode in D
> 0.5 condition. The maximum efficiency of 94.7% can be
achieved when the output power reaches 224 W in step-down
Fig. 20. Voltages on the clamping capacitors C1 and C2 of 5 A load
transients under D > 0.5. (a) 2–7 A loading transient. (b) 7–2 A unload-
mode, and the peak efficiency of 95.2% can be achieved when
ing transient. the output power reaches 210 W in step-up mode. The power
loss distribution of components of this converter are presented
in Fig. 22(b).
input voltage while keeping a regulated output voltage when
V. CONCLUSION
D > 0.5. Fig. 18(a) shows input voltage steps from 300 to 400
V, and Fig. 18(b) shows input voltage steps from 400 to 300 A novel nonisolated bidirectional dc–dc circuit topology with
V. Fig. 19 shows load transient performance when D > 0.5. high voltage gain was proposed in this article. Voltage gain of the
Fig. 19(a) shows 2–7 A loading transient, and Fig. 19(b) shows topology was three times higher than the conventional converter.
7–2 A unloading transient. Fig. 20 shows transient performance In addition, low voltage stress on active switches was also an
of voltages on the clamping capacitors C1 and C2 of 5 A load advantage. This salient feature allows the utilization of low volt-
transients when D > 0.5. Fig. 20(a) shows 2–7 A loading age rating MOSFETs, resulting in a significant reduction of the
transient, and Fig. 20(b) shows 7–2 A loading transient. Figs. 18, conduction loss. Besides, the proposed topology presents simple
19, and 20 have good transient performance when the proposed circuit structure which is composed of five active switches, two
converter is operated in D > 0.5. The efficiencies of the proposed inductors, and two capacitors. A comprehensive analysis of the
converter in the step-up and step-down modes were measured operating principle, steady-state analysis, dynamic response,

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9062 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 9, SEPTEMBER 2022

6) Core losses of inductors

Pv = kf α ΔB β (76)
Pcore = Pv × Ve (77)

where Pv is the power loss density; f is the switching frequency;

Fig. 23. Equivalent circuits of the proposed topology in nonideal ΔB is the peak flux density; k, α, β are the coefficients related
condition. to the magnetic core; and Ve is effective volume.

and loss analysis was presented in detail. The proposed con-

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YU et al.: NOVEL NONISOLATED GAN-BASED BIDIRECTIONAL DC–DC CONVERTER WITH HIGH VOLTAGE GAIN 9063

[18] C.-T. Pan, C.-F. Chuang, and C.-C. Chu, “A novel transformerless inter- Chengzi Yang (Student Member, IEEE) was
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with wide conversion ratios,” IEEE Trans. Ind. Electron., vol. 66, no. 9, versity, Xi’an, China.
pp. 7067–7078, Sep. 2019. His research interests include gate drive
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IEEE Trans. Ind. Electron., vol. 67, no. 2, pp. 1415–1424, Feb. 2020. Anhui, China, in 1995. She received the B.S.
[23] H. Ardi, A. Ajami, F. Kardan, and S. N. Avilagh, “Analysis and im- degree in electrical engineering from Xi’an Jiao-
plementation of a nonisolated bidirectional DC-DC converter with high tong University, Xi’an, China, where she is cur-
voltage gain,” IEEE Trans. Ind. Electron., vol. 63, no. 8, pp. 4878–4888, rently working toward the Ph.D. degree with the
Aug. 2016. School of Electrical Engineering.
[24] O. Kirshenboim and M. M. Peretz, “High-efficiency nonisolated converter Her research interests include wireless power
with very high step-down conversion ratio,” IEEE Trans. Power Electron., transfer, high frequency and high power density
vol. 32, no. 5, pp. 3683–3690, May 2017. dc–dc converters, signal processing, and digital
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IEEE Workshop Wide Bandgap Power Devices Appl. Asia (WiPDA Asia), Yongmei Gan (Member, IEEE) was born in
Suita, Japan, Sep. 2020, pp. 1–6. 1971. She received the B.S. and M.S. degrees
[27] L. Y. Yu, L. Wang, C. Yang, and M. Wu, “Analysis and implementation in control engineering from the Xi’an University
of a single-stage transformer-less converter with high step-down voltage of Technology, Xi’an, China, in 1993 and 1996,
gain for voltage regulator modules,” IEEE Trans. Ind. Electron., vol. 68, respectively, and the Ph.D. degree in control
no. 12, pp. 12239–12249, Dec. 2021. theory and control engineering from Northwest-
ern Polytechnical University, Xi’an, in 1999.
Since 2000, she has been with the School
Longyang Yu (Student Member, IEEE) was of Electrical Engineering, Xi’an Jiaotong Uni-
born in 1992. He received the B.S. degree in versity, Xi’an, where she is currently an Asso-
electrical engineering from the Xi’an University ciate Professor. From February 2008 to Febru-
of Technology, Shaanxi, China, in 2015. He is ary 2009, she was a Visiting Scholar with the Electrical and Computer
currently working toward the Ph.D. degree in Engineering, University of Toronto, Toronto, Ontario, Canada. Her re-
electrical engineering with Xi’an Jiaotong Uni- search interests include package and integration, energy harvesting,
versity, Xi’an, China. and supervisory control of discrete event systems.
His research interests include power elec-
tronic topology, applications of power semicon-
ductor devices, and magnetic component inte-
gration based on wide.
Hong Zhang received the B.S. degree in elec-
tronic materials and components from XiDian
Laili Wang (Senior Member, IEEE) received the University, Shaanxi, China, in 1991, and the
B.S., M.S., and Ph.D. degrees in electric en- M.S. and Ph.D. degrees in biomedical engineer-
gineering from Xi’an Jiaotong University, Xi’an, ing from Xi’an Jiaotong University, Xi’an, China,
China, in 2004, 2007, and 2011, respectively. in 1996 and 2006, respectively.
Since 2011, he has been a Postdoctoral Re- She is currently a Full Professor with the
search Fellow with the Electrical Engineering School of Electrical Engineering, Xi’an Jiaotong
Department, Queen’s University, Canada. From University. Her research interests include pack-
2014 to 2017, he was an Electrical Engineer age and integration, wireless power transfer and
with Sumida, Canada. In 2017, he joined Xi’an energy harvesting, design and development of
Jiaotong University as a Full Professor. His re- the medical instruments, and biomedical signal processing.
search interests include package and integra-
tion, wireless power transfer, and energy harvesting.
Dr. Wang serves as an Associate Editor of IEEE TRANSACTIONS
ON POWER ELECTRONICS and IEEE Journal of Emerging and Selected
Topics in Power Electronics. He is the Vice Chair of TC2 (Technical
committee of Power Conversion Systems and Components) in PELS,
Co-chair of System Integration and Application in ITRW (International
Technology Roadmap for Wide Band-gap Power Semiconductor) and
Chair of IEEE CPSS and PELS Joint Chapter in Xi’an, China.

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