NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

CHAPTER 5: FINITE STATE MACHINES

 Course outline
— Chapter 1: Introduction
— Chapter 2: Verilog Language Concepts
— Chapter 3: Structural modeling
— Chapter 4: Behavioral modeling
— Chapter 5: Finite State machines
— Chapter 6: Tasks and Functions
— Chapter 7: Functional Simulation/Verification (Testbench)
— Chapter 8: Synthesis of Combinational and Sequential Logic
— Chapter 9: Post-synthesis design tasks
— Chapter 10: VHDL introduction

UIT Digital Circuit Design with HDL - Chapter 4 2

 Introduction
— Finite State Machines (FSMs):
A useful abstraction for digital logic circuits with
-
centralized “states” of operation
- A main control block of any digital logic circuit
— Three basic components:
- Combinational logic – next states
- Sequential logic – store states (current states)
- Output logic

UIT Circuit Design with HDL - Chapter 8 3

FSM types
— There are two types of designing FSM

Moore type

Next state = F (current state, inputs)

Outputs = G (current state)

Mealy type

Next state = F (current state, inputs)

Outputs = G (current state, inputs)

UIT Circuit Design with HDL - Chapter 8 4

FSM types (con’t)
— implement at circuit level

Moore type

Mealy type

UIT Circuit Design with HDL - Chapter 8 5

FSM types (con’t)
Moore type example

UIT Circuit Design with HDL - Chapter 8 6

FSM types (con’t)
Mealy type example

UIT Circuit Design with HDL - Chapter 8 7

Constructing State Machines
— Current state logic
- Register to hold: always @(posedge/negedge clock) block

— Next state logic

- State by state case analysis: next state determined by current
state and given inputs

— Output logic
State by state analysis:
- Moore: output determined by current state only
- Mealy: output determined by current state and inputs

UIT Circuit Design with HDL - Chapter 8 8

 Constructing State Machines (con’t)
— Model FSM:
§ Decide how many states are needed, which transitions are
possible from one state to another
Using constants declaration like parameter or `define to
define name of states in FSM makes code more readable and easy
to manage.

§ Reset state

§ “always @ (pos/negedge clock)” defines the current state

§ Combinational logic defines the next state and output logic

UIT Circuit Design with HDL - Chapter 8 9

 Constructing State Machines (con’t)
— Encoding state style:
- Binary (usually used)
- One hot (usually used)
- One cold
- Almost one hot
- Almost one cold
- Gray

UIT Circuit Design with HDL - Chapter 8 10

 Constructing State Machines (con’t)
— Encoding state style:
v Binary encoding
- For N states, use ceil (log2N) bits to encode the state with each state
represented by unique combination of the bits.
- Tradeoffs: most efficient use of state registers, but requires more
complicated combinational logic to detect when in a particular state.

v One-hot encoding
- For N states, use N bits to encode the state where the bit corresponding to
the current state is 1, all the others 0.
- Tradeoffs: more state registers, but ofter much less combinational logic
since state decoding is trivial.

UIT Circuit Design with HDL - Chapter 8 11

FSM Coding Style – Simple model
— Example: 101 detector (Moore style)

UIT Circuit Design with HDL - Chapter 8 12

 FSM Coding Style – Simple model
Example: 101 detector (Moore style)
got1: begin
module moore_detector (input x, rst, clk, output z); if( x==1’b0 ) current <= `got10;
` define reset 2’b00 else current <= `got1;
` define got1 2’b01 end
` define got10 2’b10 got10: begin
` define got101 2’b11 if ( x==1’b1 ) current <= `got101;
reg [1:0] current; else current <= `reset;
//---Current state and Next state together end
always @ (posedge clk ) got101: begin
if ( rst ) current <= `reset; if (x==1’b1 ) current <= `got1;
else else current <= `got10;
case ( current ) end
reset: begin default: current <= `reset;
if( x==1’b1 ) current <= `got1; endcase
else current <= `reset; //--------- output ---------------
end assign z = (current==`got101) ? 1 : 0;
endmodule

UIT Circuit Design with HDL - Chapter 8 13

FSM Coding Style – Simple model
— Example: 101 detector (Mealy style)

UIT Circuit Design with HDL - Chapter 8 14

 FSM Coding Style – Simple model
— Example: 101 detector (Mealy style)

module mealy_detector (input x, rst, clk, output z);

localparam [1:0] reset = 0, got1 = 1, got10 = 2; got10:
reg [1:0] current; if( x==1’b1 ) current <= got1;
else current <= reset;
always @ (posedge clk ) begin default:
if (rst) current <= reset; current <= reset;
else endcase
case ( current ) end
reset:
if( x==1’b1 ) current <= got1; //--------- output ---------------
else current <= reset; assign z =
got1: (current==got10 && x==1’b1) ?1’b1 : 1’b0;
if( x==1’b0 ) current <= got10; endmodule
else current <= got1;

UIT Circuit Design with HDL - Chapter 8 15

FSM Coding Style – Huffman model
— Example: 101 detector (Moore style)

UIT Circuit Design with HDL - Chapter 8 16

FSM Coding Style – Huffman model
— Example: 101 detector (Moore style) got10: begin
if( x==1’b1 ) n_state = got101;
module moore_detector (input x, rst, clk, output reg z);
else n_state = reset;
parameter [1:0] reset=0, got1=1, got10=2, got101=3;
z = 1’b0;
reg [1:0] p_state, n_state;
end
got101: begin
//---Next state and Output circuit together --------
if( x==1’b1 ) n_state = got1;
always @ (*) begin
else n_state = got10;
case ( p_state )
z = 1’b1;
reset: begin
end
if( x==1’b1 ) n_state = got1;
default: begin
else n_state = reset;
n_state = reset;
z = 1’b0;
z = 1’b0;
end
end
got1: begin
endcase
if( x==1’b0 ) n_state = got10;
end
else n_state = got1; //--------- current state logic---------------
z = 1’b0;
always@(posedge clk )
end
if ( rst ) p_state <= reset;
else p_state <= n_state;
endmodule
UIT Circuit Design with HDL - Chapter 8 17
FSM Coding Style – more modular model
— Example: 101 detector (Moore style)

UIT Circuit Design with HDL - Chapter 8 18

FSM Coding Style – more modular model
— Example: 101 detector (Moore style)
module moore_detector( input x, rst, clk, output z); got101:
if (x == 1’b1) next_state = got1;
localparam [1:0] reset=0, got1=1, got10=2, got101=3; else next_state = got10;
reg [1:0] state, next_state; default:
next_state = reset;
//-- Combinational Next State Logic ---- endcase // case(state)
always @(*)
case (state) //--- State FF Transition (current state)-------
reset: always @(posedge clock)
if (x == 1’b1) next_state = got1; if (reset == 1’b0)
else next_state = reset; state <= reset;
got1: else
if (x == 1’b1) next_state = got1; state <= next_state;
else next_state = got10;
got10: //---- Combinational Output Logic ---
if (x == 1’b1) next_state = got101; assign z = (state == got101) ? 1: 0;
else next_state = reset;
endmodule

UIT Circuit Design with HDL - Chapter 8 19

FSM Coding Style – more modular model
— Example: 101 detector (Mealy style)

UIT Circuit Design with HDL - Chapter 8 20

 FSM Coding Style – more modular model
— Example: 101 detector (Mealy style)
module moore_detector (input x, rst, clk,
default:
output z);
next_state = reset;
parameter [1:0] reset=0, got1=1, got10=2;
endcase // case(state)
reg [1:0] state, next_state;
//----State FF Transition-----
//---Combinational Next State Logic----
always @(posedge clock)
always @(*)
if (reset == 1’b0)
case (state)
state <= reset;
reset:
else
if (x) next_state = got1;
state <= next_state;
else next_state = reset;
got1:
//---Combinational Output Logic---
if (x) next_state = got1;
assign z =
else next_state = got10;
(state == got10) && (x == 1);
got10:
if (x) next_state = got1;
endmodule
else next_state = reset;

UIT Circuit Design with HDL - Chapter 8 21

Design Example – Level-to-Pulse

Source: MIT
UIT Circuit Design with HDL - Chapter 8 22
Asynchronous Inputs in Sequential System

Source: MIT
UIT Circuit Design with HDL - Chapter 8 23
Asynchronous Inputs in Sequential System

Source: MIT
UIT Circuit Design with HDL - Chapter 8 24
Asynchronous Inputs in Sequential System
Ø Preventing metastability turns out to be an impossible problem
Ø Solution to metastability: allow time for signal to stabilize

How many registers are necessary?

- Depend on many design parameters (clock speed, design speed,…)
- A pair of synchronization registers is sufficient
Source: MIT
UIT Circuit Design with HDL - Chapter 8 25
Design Example – Level-to-Pulse

Source: MIT
UIT Circuit Design with HDL - Chapter 8 26
Design Example (cont.)

Source: MIT
UIT Circuit Design with HDL - Chapter 8 27
Design Example (cont.) – Moore FSM

Source: MIT
UIT Circuit Design with HDL - Chapter 8 28
Design Example (cont.) – Moore FSM

Source: MIT
UIT Circuit Design with HDL - Chapter 8 29
Design Example (cont.) – Mealy FSM

Source: MIT
UIT Circuit Design with HDL - Chapter 8 30
Design Example (cont.) – Mealy FSM

Source: MIT
UIT Circuit Design with HDL - Chapter 8 31
Typical Example of FSM
— Objectives:
- Build an electronic combination lock with a reset
button, two number buttons – 0 and 1, and an
unlock output.
- The unlock code should be 01011
— Step:
1. Design lock FSM: block diagram, state transitions
2. Write verilog module(s) for FSM

Source: MIT
UIT Circuit Design with HDL - Chapter 8 32
STEP 1A - Block Diagram

Source: MIT
UIT Circuit Design with HDL - Chapter 8 33
STEP 1B – State Transition Diagram

Source: MIT
UIT Circuit Design with HDL - Chapter 8 34
STEP 2 – Write Verilog

Source: MIT
UIT Circuit Design with HDL - Chapter 8 35
STEP 2A – Synchronize Buttons

Source: MIT
UIT Circuit Design with HDL - Chapter 8 36
STEP 2B – State Transition Diagram and Output

Source: MIT
37
STEP 2 – Final Implementation Verilog

Source: MIT

Circuit Design with HDL - Chapter 8

38
Real FSM Security System

Source: MIT
Circuit Design with HDL - Chapter 8
39
Tips on FSM
v Don’t forget to handle the “default” for case statement
v Use two different always blocks for next state and current
state circuit
Can do it in one big block but not as clear
v Outputs can be a mix of combin. and seq.
Moore machine: Output only depends on current state
Mealy machine: Output only depends on current state and inputs

UIT Circuit Design with HDL - Chapter 8 40