Program : B.

Tech
Subject Name: CMOS Design
Subject Code: EC-603
Semester: 6th
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Unit-I : Introduction: Introduction to CMOS VLSI circuit, VLSI design flow, Design strategies ,Hierarchy,
regularity, modularity, locality, MOS Transistor as a Switches, CMOS Logic, Combinational circuit, latches and
register, Introduction of CAD Tool , Design entry, synthesis, functional simulation.

Introduction to CMOS VLSI circuit:

The growth in the semiconductor industry has increased to a larger extent due to the shrinks in the
CMOS process technology. Many of the sophisticated multimedia based applications are integrated into
mobile electronics gadgets since last decade. The level of component integration into a single chip has been
classified as small-scale(SSI), medium-scale(MSI), large-scale (LSI) and very large scale(VLSI).
As CMOS transistors used in VLSI are faster, consume less power, and are cheaper to manufacture,
designers have come to rely on increasing levels of automation to seek corresponding gains. In the digital
circuits design the MOS transistor is used as a switch.

VLSI Design Flow: The VLSI design flow consists of three different domains, behavioral domain, structural
domain and geometrical layout domain. Most of the VLSI design use these design activities, which is illustrated
as Y-chart. The three axes represents each of the domain as shown in Fig.1.1

Structural Behavioral
Domain Domain

Processor
Resister ALU
Algorithm
Leaf Cell
Module
Transistor Description
Boolean
Equation
Mask
Finite State
Cell Machine
Placement

Module
Placement

Chip Floor plan

Geometrical
Layout Domain

Fig.1.1 : Y-Chart representation for VLSI Design Flow

(a) Behavioral Domain: The system description in this domain needs the knowledge of functionality of the
block used in the system. The behavior of the system is described using Boolean expressions, truth tables,
algorithms or circuit description written in HDL. The design is tested for its functionality by verifying the
simulation results.
(b) Structural Domain: In this domain the interconnection of the components is described by the designer. The
transistor level description is represented in this domain. The standard blocks are design and used as a
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library component. These blocks are called as standard cell. The designer needs to have the circuit
connection while describing the system in this domain. The standard cell modules are placed with a goal of
minimizing interconnects area and the signal delays using CAD tools.
(c) Geometrical Layout Domain: The third design domain is the geometrical layout. The tested circuit design is
described in terms of its geometrical view of the components on the silicon. The layout of the components
along with interconnects between them is described for the fabrication.
The concentric circles around the center of Y-chart are indicative of various levels of abstraction that are
common in design. The particular abstraction levels and design objects may differ slightly, depending on the
design method.
Simplified VLSI Design Flow :
The Fig.1.2 shows the simplified flow of
System Specification
VLSI design process. It consists of various
representations at different levels and layout
design. At each stage of design the
Functional verification is very important step to move
(Architecture) Design forward to the next step.
The design flow have many iterations and
described in linear fashion of simplicity. Both
Behavioral Functional Verification top-down and bottom-up approaches have to
Representation be combined for a successful design. The
descriptions mentioned in the architecture
level have to meet the availability of the chip
Logic Design area in the physical design. To match the
parameters at every level of abstract
description, it is important to pass the
Logic (Gate-level) Logic Verification previous level information to the next level. If
Representation there is any mismatch of the parameters,
then the design has to repeat the previous
step. Thus in the design flow many iterations
Circuit Design may be used to have a successful design.

Circuit Representation Circuit Verification

Physical Design

Layout Representation Layout Verification

Fabrication & Testing

Fig.1.2 : VLSI Design Flow Chart

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Design Hierarchy: In VLSI system design simple blocks called as cells are used to build the complex systems.
The concept of dividing the complex system into the simple blocks is called as design hierarchy. The cells
consists of logic gates, combinational logic cells which are created as a list of library components.
e.g., In the design of 4-bit parallel adder, full adder is one of the sub module and it is required to have 4 full
adders. Further the full adder is design using the logic gates. In the design hierarchy, logic gate is the cell for
building the full adder and for 4-bit adder the full adder is the cell. These cell are copied into the library and as
per the design requirements they are interconnected to get the desired complex design.

i)Regularity : Regularity means that the hierarchical decomposition of a large complex system should result in
not only simple, but also similar blocks, as much as possible. The advantage of regularity is reduction in
number of different modules that need to be designed and verified, at all levels of abstraction.
Example : Design of array structures consisting of identical cells, such as a parallel multiplication array.

ii)Modularity : Modularity in design means that the various functional blocks which make up the larger
complex system must have well-defined functions and interfaces. The concept of modularity enables the
parallelisation of the design process.
Example : Each block or module can be designed relatively independently from each other. All of the blocks
can be combined with ease at the end of the design process, to form the large system.

iii)Locality : The locality ensures that the connections are mostly between neighboring modules, avoiding long
distance connections as much as possible. Time critical operations should be performed locally, without the
need to access distant modules or signals.

MOS Transistor as a Switches:

Digital logic designs are built with transistors as a switch. The gate terminal of the MOS transistor
works as control signal. It allows the transistor to connect and disconnect. The characteristic and symbolic
representation of nMOS and pMOS are shown in Fig.1.3 .

VG

VS VD Input ‘a’ Input ‘a’

VG = 0 Output ‘b’ VG = 1 Output ‘b’
(a) nMOS Symbol (b) nMOS Switch (c) nMOS Switch
status for VG=0 status for VG=1
VG

VS VD Input ‘a’ Input ‘a’

VG = 1 Output ‘b’ VG = 0 Output ‘b’

(d) pMOS Symbol (e) pMOS Switch (f) pMOS Switch
status for VG=1 status for VG=0

Fig.1.3 : MOS transistor as a switch

nMOS Transistor as a Switch: The symbol used in the digital system design to represent the nMOS transistor is
as shown in the Fig. (a). If the gate voltage VG is low (Logic ‘0’), then there is no connection between drain
and source terminal and the switch is open. If the gate voltage V G is high (Logic ‘1’), then there is connection

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between drain and source terminal and the switch is closed. The nMOS transistor allows good logic ‘0’ and
poor logic ‘1’ to pass through from input to output.

pMOS Transistor as a Switch: The symbol used in the digital system design to represent the pMOS transistor is
as shown in the Fig. (d). If the gate voltage VG is high (Logic ‘1’), then there is no connection between drain
and source terminal and the switch is open. If the gate voltage V G is low (Logic ‘0’), then there is connection
between drain and source terminal and the switch is closed. The pMOS transistor allows good logic ‘1’ and
poor logic ‘0’ to pass through from input to output.

Transmission Gate (TG): It is the combination of n-switch and p-switch in parallel. Both the switch are
operated in the same state by connecting the complement gate signal as shown in the Fig.1.4. The good logic
‘0’ and good logic ‘1’ is possible to pass through either through nMOS or pMOS depending on the input signal.
The TG is used in the realization of XOR logic, multiplexer circuits.

S’
S’

Input ‘a’ Output ‘b’ Input ‘a’ Output ‘b’

S
S
(a) Parallel Combination (b) Symbol of TG
of nMOS and pMOS

Fig.1.4: Schematic diagram of Transmission Gate (TG)

Realization of Logic gates using CMOS Technology:

VDD VDD
VDD

A Y=A A Y = A.B A
B B
Y = A+B

(a) CMOS Inverter (b) CMOS 2-Input NAND Gate (c) CMOS 2-Input NOR Gate

Fig.1.5 : CMOS Logic Gate

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CMOS logic is the combination of both nMOS and pMOS components. The nMOS networks is called as pull
down network and pMOS network is called as pull up network.

Logic Implementation of AOI (And Or Inverter) Equations:

Draw the CMOS logic diagram for the given AOI Draw the CMOS logic diagram for the given AOI
equation equation
Y = A.B + C.D Y = A.(B + C)
VDD VDD

D P4 P3 C C P3

P1 A

B P2 P1 A B P2

Y= A.B + C.D Y= A.(B + C)

D N4 N2 B C N3 N2 B

C N3 N1 A N1 A

Fig.1.6 : CMOS Logic Diagram of Y=A.B+C.D Fig.1.7 : CMOS Logic Diagram of Y=A.(B+C)

Logic Implementation using TG:

B B’

A A

B’ Y=AB’ + A’B B Y=AB + A’B’

A’ A’

B B’

Fig.a: Schematic Diagram of 2 input XOR Gate using TG Fig.b: Schematic Diagram of 2 input XNOR Gate using TG

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S0

S1
A

S0’

B
S
S0 S1’
Y (Output)
A
C

S’ Y=AS’ + BS
S0’

B
D S1

S S0
Fig.c: Schematic Diagram of 2:1 MUX using TG Fig.d: Schematic Diagram of 4:1 MUX using TG

Fig.1.8 : Logic Implementation using Transmission Gate

Introduction of CAD Tool:

The CAD system includes the following tools (i) Design Entry (ii) Simulation (iii) Synthesis and
optimization (iv) Physical design.

(i) Design Entry : The integrated circuit can be design in different ways based on the knowledge of the
modeling of the system. The process of describing the circuit in the CAD system design is called as design
entry. There are three methods of design entry.
(a) Using Truth Table:
(b) Schematic Capture:
(c) Hardware Description Language:
(ii) Functional Simulation: The completed design entry is tested for its correct functionality using simulator.
The CAD tool that performs the testing of functionality is called functional simulator. The design is tested
by providing the test vectors for the inputs and compared the output values for its expected outputs. It is
also used to test the design after synthesis using logic gates or logic blocks. Post synthesis simulation
involve functional testing as well as timing constraints of the circuit are met.
(iii) Synthesis & Optimization: A synthesis tool translates the design description into physically realizable
circuit. The process of translating the design entry to a physically realizable circuit using logic gates or logic
blocks inside the PLD such as FPGA. The synthesis tool is also used to optimize the circuit. The basic
synthesis process is as shown in the Fig. .
(iv) Physical Design: This is the final step in the design process before actual hardware implementation of a
digital integrated circuit. This phase is also called as place & route where logic gates are interconnected to
complete the circuit. CAD tools allow the designer to capture circuit in the optimized way. It also capture
circuit to be simulated before actually constructing the integrated circuit. These captured information can
be stored, transported and modified by the designer. The HDL definitions of the design are independent of
the CAD tools used for testing the design.

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