AMPLIFIERS

Aloke Dutta/EE/IIT Kanpur 1

 Outline
• Amplification of ac signals (voltage,
current)
• Discrete and IC
• Single-Stage and Multi-Stage
• Modular approach
• Interested in:
 Voltage/Current Gain (Av/Ai)
 Input/Output Resistance (Ri/R0)

Aloke Dutta/EE/IIT Kanpur 2

 Midband Analysis
A

Amax
3-dB in
Bode plot
Amax/
midband
Midband

Bandwidth
bandwidth

0 fL fH
f

fL: Lower Cutoff Frequency

fH: Upper Cutoff Frequency
Bandwidth = f H – f L
Aloke Dutta/EE/IIT Kanpur 3
 Single-Stage Topologies
• BJT:
 Common-Emitter (CE)
 i/p to B, o/p from C, E common to both i/p and o/p
 Common-Base (CB)
 i/p to E, o/p from C, B common to both i/p and o/p
 Common-Collector (CC)
 i/p to B, o/p from E, C common to both i/p and o/p
 Common-Emitter (Degeneration) [CE(D)]
 Same as CE, but now with an emitter resistance
attached
Aloke Dutta/EE/IIT Kanpur 4
• MOSFET:
 Common-Source (CS)
 i/p to G, o/p from D, S common to both i/p and o/p
 Common-Gate (CG)
 i/p to S, o/p from D, G common to both i/p and o/p
 Common-Drain (CD)
 i/p to G, o/p from S, D common to both i/p and o/p
 Common-Source (Degeneration) [CS(D)]
 Same as CS, but now with a source resistance
attached

Aloke Dutta/EE/IIT Kanpur 1

• For MOSFETs, an additional topology
possible: i/p to Body, o/p from S/D
 Known as body-driven or bulk-driven stage
• Each of the topologies has specific
characteristics in terms of voltage/current
gain and input/output resistance
• Each of these will be treated as a module,
and will do a complete analysis for each of
these stages

Aloke Dutta/EE/IIT Kanpur 2

 Multi-Stage Topologies
• Also known as Compound Connections
• Combination of 2 or more stages
 A module by itself
• Some widely used topologies:
 Darlington
 Cascode
 Differential Amplifier/Differential Pair
(DA/DP)
Aloke Dutta/EE/IIT Kanpur 3
 Basic Structure
• Consists of a driver and a load
• Driver: Universally active devices, e.g.,
BJTs or MOSFETs
• Load: Can either be resistors (passive) or
transistors (active)
• Generally, discrete stages have passive
loads, while IC stages have active loads

Aloke Dutta/EE/IIT Kanpur 4

 Resistance Transformation
(Only for BJTs)
• A very useful technique
• For equivalence: C
B
IbR2 = IeR1 Ib C
B
 R2 = ( +1)R1 R1
Ie
R2
E
or R1 = R2/( +1) E

• Apply it freely!

Aloke Dutta/EE/IIT Kanpur 5

 Single-Stage Amplifiers
• Common-Emitter (CE):
VCC
ii
RC v0
vi
+
v0
vi v1 r gmv1 RC r0
Q
–
R0
Ri

ac Schematic ac Low-Frequency Equivalent

 Biasing circuit not shown

Aloke Dutta/EE/IIT Kanpur 1
 By inspection, Voltage Gain:
v0 g m v1  R C  r0 
Av    g m  R C  r0 
vi vi
 The negative sign in front implies 180 phase
shift between vi and v0
 vi and v0 are exactly out of phase
 For discrete circuits, in general, RC << r0
 Av =  gmRC   RC/rE (moderate to large)
 On the other hand, if r0 << RC:
Av =  gmr0 =  1/ =  VA/VT (can be huge!)
 Theoretical maximum voltage gain of this circuit

Aloke Dutta/EE/IIT Kanpur 2

 Current Gain:
Ai = ic/ib =  (large)
 Thus, Power Gain:
PG = Av  Ai (very large)
 Therefore, this circuit is designers’ favorite!
 Has primary use as audio amplifiers
 Input Resistance:
Ri = vi/ii = r (decent)
 Output Resistance:
R0 = RC||r0  RC
Aloke Dutta/EE/IIT Kanpur 3
• Common-Source (CS):
VDD

RD vi v0
v0
+
vi gmv1 RD r0
v1
M
R0 –
Ri
ac Schematic ac Low-Frequency Equivalent

 Biasing circuit not shown

 Body at ground  No body effect

Aloke Dutta/EE/IIT Kanpur 1

 By inspection, Voltage Gain:
v0 g m v1  R D  r0 
Av    g m  R D  r0 
vi vi
 The negative sign in front implies 180 phase
shift between vi and v0
 vi and v0 are exactly out of phase
 For discrete circuits, in general, RD << r0
 Av =  gmRD (moderate)
 Input Resistance: Ri → 
 Output Resistance: R0 = RD||r0  RD
 Note the remarkable similarity with CE stage
Aloke Dutta/EE/IIT Kanpur 2
 If RD >> r0:
Av =  gmr0 =  kNVGT/(ID) =  2/[(V)]
(assuming VDS < 0.1)
 Thus, for small  and small V, Av can be
large
 Keep in mind that V(min) = 3VT
 Also, Av  1/ID
 Lower ID, higher Av
 Recall: For CE stage, Av(max) was
independent of IC, and dependent only on T

Aloke Dutta/EE/IIT Kanpur 3

 • Common-Collector (CC):
 Also known as Emitter-Follower
ii
VCC vi vi
+ +
vi
Q v1 r gmv1 r0 v1 r gmv1
– –
v0 v0 v0
Ri
i0
RE RE RE||r0
R0

Simplified ac
ac Schematic ac Low-Frequency Equivalent
Low-Frequency Equivalent

 Biasing circuit not shown

Aloke Dutta/EE/IIT Kanpur 1

 Voltage Gain:
v0 i 0  R E  r0     1 ii  R E  r0 
Av   
vi v1  v 0 ii r     1 ii  R E  r0 
R E  r0 R E  r0
 
r    1  R E  r0 rE  R E  r0

 Now, in general, r0 >> RE

 Av = RE/(rE + RE)
 Two important observations:
 Av  1
 No phase shift between vi and v0
Aloke Dutta/EE/IIT Kanpur 2
 Current Gain:
Ai = ie/ib =  +1 (large)
 Input Resistance:
vi ii r  i 0  R E  r0 
Ri  
ii ii
ii r     1 ii  R E  r0 

ii
 r     1 R E  r0 

 If r0 >> RE, Ri = r + ( + 1)RE

Aloke Dutta/EE/IIT Kanpur 3

  Note that this result could have been written from
inspection from the ac schematic using the
technique of Resistance Transformation
 Output Resistance:
i t  i 0  g m v1  ii ii

vt vt +
  gm vt  v1 r gmv1
R E  r0 r –
it

 R0 = RE||r0||rE||r  rE i0
RE||r0 vt
 Note that this expression also
could have been written by
inspection

Aloke Dutta/EE/IIT Kanpur 4

 Output excited by a test voltage source vt:
 The current has two parallel paths: one going
through the parallel combination of r0 and RE, and
the other into the emitter of Q
 The resistance in the base lead of Q is r, which
needs to be transformed to emitter by dividing it by
( +1)  yields rE
 Thus, R0 becomes a parallel combination of r0, RE,
and rE, which will be typically equal to rE, since, in
general, it’s the least among the three
 Understand the inspection technique, it will
become immensely useful to analyze circuits

Aloke Dutta/EE/IIT Kanpur 5

 Some special properties of CC Stage:
 Av  1 (by proper design, it can be made to
approach unity very closely)
 Input and output in phase
 Quite large input resistance
 Very small output resistance
 These properties are highly desirable to
prevent loading effect of cascaded stages (to be
discussed later)
 Thus, this stage is also known as Buffer or
Isolator or Impedance Matcher

Aloke Dutta/EE/IIT Kanpur 1

• Common-Drain (CD):
 Also known as Source Follower
VDD vi

vi +
gmvgs gmbvbs r0
M vgs
v0 – v0
–
Ri vbs
RS RS +
R0

ac Schematic ac Low-Frequency Equivalent

 Biasing circuit not shown

Aloke Dutta/EE/IIT Kanpur 2

 Note: Body terminal at ground, but source is
at a floating potential (it’s the output terminal)
 Body effect will be very much present for M
 Can be avoided by putting M in its separate
island
 Voltage Gain:
 KCL at output node:
gmvgs + gmbvbs = v0/(RS||r0)
with vgs = vi  v0, and vbs = v0
v0 g m  R S  r0 
 Av  
vi 1   g m  g mb  R S  r0 

Aloke Dutta/EE/IIT Kanpur 3

 Simplification:
 In general, r0 >> RS:
gmRS
 Av 
1   g m  g mb  R S
 If body effect is neglected:
gmRS RS
 Av  
1  gmRS 1 gm  RS
Note the remarkable similarity with CC stage
 If (gm + gmb)RS >> 1:
gm 1
 Av  
g m  g mb 1  

Aloke Dutta/EE/IIT Kanpur 4

  Note:


2 2F  VSB
with VSB = V0 (DC level of v0)
 Typical values of  ~ 0.1-0.5
 Thus, Av can depart significantly from its ideal
value of unity
 No phase shift between input and output
 Input Resistance: Ri → 
 Output Resistance: By inspection:
R0 = (gm + gmb + g0 + gS)1 (g0 = 1/r0, gS = 1/RS)

Aloke Dutta/EE/IIT Kanpur 5

• Common-Emitter (Degeneration) [CE(D)]:
 Let’s attempt to analyze
VCC
this circuit by inspection
i c

 v0 =  icRC
RC

v0
vi = ie(rE + RE) R01
v
 Av = v0/vi
i
Q
i R0
  RC/(rE + RE)
b
i e
R i
RE
Piece of cake?
 Ai = ic/ib = 
 Ri = r + ( + 1)RE = ( + 1)(rE + RE)
Aloke Dutta/EE/IIT Kanpur 3
 R0 = R01||RC
Can you identify R01 by inspection?
R01 = r0[1 + gm(r||RE)]
Generally, R01 >> RC
 R0  RC
 Probe Av further:
Av =  RC/(rE + RE)  gmRC/(1 + gmRE)
For CE stage, Av = gmRC
For this stage, Av is lower by a factor (1 +
gmRE)  Gain Degeneration
Aloke Dutta/EE/IIT Kanpur 4
 (1 + gmRE) is known as the Degeneration
Factor
 Ri can also be written as:
Ri  r + RE = r(1 + gmRE)
Thus, Ri by the Degeneration Factor as
compared to the CE stage
 Interesting to note that the loss in gain is
returned by this circuit to its Ri by the same
factor!

Aloke Dutta/EE/IIT Kanpur 1

 Why do we sacrifice gain?
 Later on, we will see that this sacrifice in gain
leads to a commensurate increase in the bandwidth
of the circuit
 For a given DC bias point, the gain-
bandwidth product (GBP) of a circuit remains
constant (will be explored later)
 This is one of the famous paradoxes of analog
circuits:
 To increase gain, sacrifice bandwidth, and vice
versa

Aloke Dutta/EE/IIT Kanpur 2

 • Common-Source (Degeneration) [CS(D)]:
VDD

RD
i0
vi v0
v0
R01 +
vi gmvgs gmbvbs r0 RD
vgs
M
R0 –
–
+
vbs
RS vs RS +
Ri
–

ac Schematic ac Low-Frequency Equivalent

Aloke Dutta/EE/IIT Kanpur 3

 Defining Relations:
v0 =  i0RD
i0 = gmvgs + gmbvbs + (v0  vs)/r0
vs = i0RS
vgs = vi  vs
vbs =  vs
v0 gmR D
 Av  
vi 1   g m  g mb  R S   R S  R D  r0
 Pretty complicated expression, however,
simplifications can be made

Aloke Dutta/EE/IIT Kanpur 4

 Generally, (RS + RD)/r0 can be neglected:
v0 gmR D
 Av  
vi 1   g m  g mb  R S
 Neglect body effect:
gmR D RD
 Av   
1  gmRS 1 gm  RS
 Again, remarkable similarity with CE(D) stage
 Golden Observation:
 MOS stages, in absence of body effect, is absolutely
similar to BJT stages, with rE replaced by 1/gm , and
both  and r → 

Aloke Dutta/EE/IIT Kanpur 5

 Note that here the Degeneracy Factor is (1 +
gmRS)
 Ri → 
 R0 = R01||RD
R01 = r0[1 + (gm + gmb)RS] (Show!)
 Again gain is sacrificed in order to improve
the bandwidth by the same amount
 The complexity of analysis of this circuit is
slightly more than the others encountered so far

Aloke Dutta/EE/IIT Kanpur 6

• Common-Base (CB):
r0
gmv1
vi v0 vi – v1 + v0
Q
rE
RC RC
R01 R0
Ri

ac Schematic ac Low-Frequency Equivalent

Note that the alternate hybrid- model

appropriate for CB circuit has been used
 r0 appears between input and output
Aloke Dutta/EE/IIT Kanpur 1
 For now, neglect r0
 Noting that v1 =  vi:
v0 g m v1R C RC
Av    g m R C 
vi vi rE
 Note that the expression for Av is identical to
that for the CE stage, without the negative sign
in front
 For this circuit, input and output are in phase
 Ai = ic/ie = 
 Ri = rE

Aloke Dutta/EE/IIT Kanpur 2

 R0 = R01||RC
R01 →  (Why?)
 R0 = RC
 Ex.: Find Av and Ri with r0 included
 With r0 included, the circuit shows two
different values of R01:
 When excited by a voltage source, R01 = r0
 When excited by a current source, R01 = r0 (Show)
[Hint: For this derivation, need to use gmrE = ]
 Thus, possibility of huge R0 under the second case,
but RC ruins it!

Aloke Dutta/EE/IIT Kanpur 3

 • Common-Gate (CG):
D S
vi v0
M
gmvgs gmbvbs r0 (gm + gmb)vi r0
RD
Ri
R01 R0
S D
ac Schematic ac Low-Frequency Simplified ac Low-
Model for M Frequency Model for M
r0 vi r0 v0
S D
+ +
–1
vi (gm + gmb)vi (gm + gmb)vi vi (gm + gmb) (gm + gmb)vi RD
– –
G

Rerouting the current source Final ac Low-Frequency

between S and D to S to G Equivalent for CG Stage
and then from G to D

Aloke Dutta/EE/IIT Kanpur 1

 G and B both ground:
 vgs = vbs =  vi
 gmvgs and gmbvbs can be combined to a
single current source (gm + gmb)vi, flowing
from S to D
 Reroute this current source from S to G and
then from G to D (the circuit remains
invariant)
 Leads to the final ac low-frequency
equivalent of the CG stage
 Note again that r0 appears between input and
output (similar to CB stage)
Aloke Dutta/EE/IIT Kanpur 2
 Neglect r0 for now
 Noting that v1 = vi:
v0  g m  g mb  v1R D
Av      g m  g mb  R D
vi vi
 Identical result to a CB stage, if body effect is
neglected
 Ri = (gm + gmb)1
 R0 = R01||RD
R01 →  (Why?)
 R0 = RD

Aloke Dutta/EE/IIT Kanpur 3

 Ex.: Find Av and Ri with r0 included
 With r0 included, the circuit shows three
different values of R01:
 When excited by a voltage source, R01 = r0
 When excited by an ideal current source, R01 → 
(Show)
 If the current source is non-ideal with shunt
resistance RS:
R01 = r0[1 + (gm + gmb)RS] (Show)

Aloke Dutta/EE/IIT Kanpur 4

 Quick Reckoner for BJT Stages

Topology Av Ai PG Ri R0
Moderate
CE Large Large Moderate Moderate
to Large
CC 1 Large Moderate Large Small
Moderate
to Large 
CB 1 Moderate Small Moderate

CE(D) Moderate Large Moderate Large Moderate

Aloke Dutta/EE/IIT Kanpur 5

• The RC-Coupled Amplifier:
 Immensely popular, particularly for audio
circuits
 Can be designed to produce significant power
gain
 Several such stages can be cascaded to
produce very large gain
 Can be used either with single-supply or dual-
supply
 Used primarily in discrete designs (PCB)

Aloke Dutta/EE/IIT Kanpur 6

 VCC

RC
R1 4 k
v0
90 k
RS VC
v0
vi 1 k
CC RL
Q
VB 4 k vi RS vb
CB Q R4
VE
R2
RE R3
10 k CE
250 
R0
Ri Ri1

Complete Circuit ac Schematic

CB: Base Blocking Capacitor , CC: Collector Coupling Capacitor

CE: Emitter Bypass Capacitor , RS: Source Resistance , RL: Load Resistance

Aloke Dutta/EE/IIT Kanpur 7

 VCC
12 V

RC
R1 4 k
v0
90 k
RS VC
v0
vi 1 k
CC RL
Q
VB 4 k vi RS vb
CB Q R4
VE
R2
RE R3
10 k CE
250 
R0
Ri Ri1

Complete Circuit ac Midband Schematic

CB: Base Blocking Capacitor , CC: Collector Coupling Capacitor

CE: Emitter Bypass Capacitor , RS: Source Resistance , RL: Load Resistance

Aloke Dutta/EE/IIT Kanpur 1

 CB,CC: Used for DC isolation of the bias
circuit from the source and the load
 DC biasing becomes independent of source and
load
 CE: Plays no role in DC (opens up), but shorts
out RE in ac (will see its effects later)
 These 3 capacitors dictate the lower cutoff
frequency (fL) of the circuit
 Typically have values in the order of F to
100s of F in order to give fL as close to 0
(DC) as possible
Aloke Dutta/EE/IIT Kanpur 2
 First need to do the DC analysis to find the
operating point
 All capacitors open up for DC analysis
 RS and RL play no role
 Neglecting base current:
VB = VCCR2/(R1 + R2) = 1.2 V
 VE = VB  VBE = 0.5 V
 IE  IC = VE/RE = 2 mA
VC = VCC  ICRC = 4 V
VCE = 3.5 V (quite close to VCC /3)
 DC bias point analysis done!
Aloke Dutta/EE/IIT Kanpur 3
 Now we can move on to the ac analysis
 All capacitors get shorted due to their high
values, assuming frequency of operation is
beyond fL and less than fH, i.e., midband range
 CE bypasses RE
 Emitter of Q goes to ground
 RE plays no role in ac analysis
 Refer to the ac schematic
 R3 = R1||R2 = 9 k
 R4 = RC||RL = 2 k
 Need  for ac analysis (choose 100)
Aloke Dutta/EE/IIT Kanpur 4
 rE = VT/IC = 13 , and r = rE = 1.3 k
 Ri1 = r = 1.3 k
 Ri = Ri1||R3 = 1.14 k
 Total resistance seen by vi = RS + Ri = 2.14 k
 For calculation of voltage gain Av, apply chain
rule:
Av = v0/vi = (v0/vb)  (vb/vi)
v0/vb =  R4/rE =  153.85 (CE stage)
vb/vi = Ri/(Ri + RS) = 0.533
 Av =  82 (Very Good Gain!)

Aloke Dutta/EE/IIT Kanpur 5

 Note that vi and v0 are exactly out of phase,
which is expected from a CE stage
 R0 = r0||R4  R4 = 2 k
(since for discrete circuits, r0 is generally
neglected)
 This completes the analysis of the stage
 Summary:
 Av =  82
 Ri = 1.14 k
 Resistance seen by vi = 2.14 k
 R0 = 2 k
Aloke Dutta/EE/IIT Kanpur 6
 Now let’s explore what happens if CE were
absent, i.e., RE unbypassed
 Redraw the ac schematic:
v0

vi RS vb
Q R4

R3
RE
250 
R0
Ri Ri1

ac Midband Schematic for R E unbypassed

Aloke Dutta/EE/IIT Kanpur 1

 Note: Degeneration Factor = (1 + gmRE)  (1+
RE/rE) = 20.23
 Ri1 = r + ( +1)RE = 26.55 k
 Exactly 20.23 times of the previous case (1.3 k)
 Ri = Ri1||R3 = 6.72 k
 Total resistance seen by vi = RS + Ri = 7.72 k
 v0/vb =  R4/(rE + RE) =  7.6 [CE(D) Stage]
 Reduced by exactly 20.23 times of the previous
case ( 153.85)
 vb/vi = Ri/(Ri + RS) = 0.87
 Improvement as compared to previous case
(0.533)
Aloke Dutta/EE/IIT Kanpur 2
 Av =  6.6
 Compare with  82 obtained in previous case
(significant reduction)
 R0  R4 = 2 k (if r0 is neglected)
 If r0 is considered, analysis becomes
significantly complicated, since the Golden
Rule can’t be applied due to the presence of
resistance (apart from r) in the base of Q
 Summary:
 Av =  6.6
 Ri = 6.72 k
 Resistance seen by vi = 7.72 k
 R0 = 2 k
Aloke Dutta/EE/IIT Kanpur 3
 What if the output is taken from emitter?
 Redraw the ac schematic:

vi RS vb
Q R4

R3 R01
v0
RE
Ri Ri1 250 
R0

ac Midband Schematic for

Output Taken from Emitter

Aloke Dutta/EE/IIT Kanpur 4

 R4 actually redundant for this case (collector
of Q could have been connected to VCC directly)
 Ri1 = 26.55 k, Ri = 6.72 k, and resistance
seen by vi = 7.72 k (same as before)
 v0/vb = RE/(rE + RE) = 0.95 (CC Stage)
 vb/vi = Ri/(Ri + RS) = 0.87 (same as before)
 Av = 0.827 (<1, as expected, but could have
been made closer to unity by better design!)
 R0 = RE||R01
 Computation of R01 is slightly more involved,
but quite easy if the trick is understood!
Aloke Dutta/EE/IIT Kanpur 5
 First, short vi to ground
 R3 comes in parallel with RS (call this
combination R5)
 R5 = R3||RS = 900 
 R5 comes in series with r (call this
combination R6)
 R6 = R5 + r = 2.2 k
 Transform R6 to emitter by dividing it by (
+1)
 R01 = R6/( +1) = 21.8 

Aloke Dutta/EE/IIT Kanpur 2

 Thus, R0 = 20  (Easy?)
 Summary:
 Av = 0.827
 Ri = 6.72 k
 Resistance seen by vi = 7.72 k
 R0 = 20 
 Thus, this circuit has voltage gain close to
unity, ok input resistance, and very small
output resistance
 Ideal characteristics needed for a Buffer/Isolator/
Impedance Matcher

Aloke Dutta/EE/IIT Kanpur 3

• Loading Effect:
 Neglecting r0:
VCC
Av =  gm(RC||RL)
 RL has no role in DC biasing, RC
CC
v0
but comes into picture in vi
Q RL
ac calculations
 As RL  |Av|
 Known as Loading Effect
 Similar situation happens when a high output
resistance driver drives a low input resistance
load (e.g., CE stage driving a CB stage)
Aloke Dutta/EE/IIT Kanpur 4
 The gain of the CE stage will be severely
compromised due to low input resistance of the
CB stage
 Known as Impedance Mismatch between Driver and
Load
 Under such a situation, need an Isolator/Buffer/
Impedance Matcher between the two stages
 A CC stage perfectly fits the bill due to its high
input resistance and low output resistance, and
can be used to couple the CE stage to CB stage
 MOS circuits generally don’t have this problem

Aloke Dutta/EE/IIT Kanpur 5

 Compound Connections
• Multi-Stage
• Have some special properties
• Popular Topologies:
 Darlington
 Cascode
 DP (or DA)
• Modules by themselves

Aloke Dutta/EE/IIT Kanpur 6

• Darlington:
 Cascade of a CC stage, followed by either a
CE or a CC stage
 Two biggest advantages:
 Extremely large Ri
 Extremely large Ai
 These two advantages are automatic for MOS
stages
 MOS Darlington has no special use

Aloke Dutta/EE/IIT Kanpur 7

 VCC
VCC ii
VCC
Q1
vi
C C ii i0
B C vi RL i1
C
Q1 Q1 C
Ri Q2
v0 vb
R01
i1
Ri v0 C
Q2 Q2 Ri1 Q
vb R0 C
i0 B
RL
R0
C C
E E
Compact
Generic Circuit CC-CE Stage CC-CC Stage
Representation

 For DC biasing:
IC2 = 2IB2 = 2IE1  2IC1
 r2 = 2rE2 = 2VT/IC2 = VT/IC1 = rE1
Aloke Dutta/EE/IIT Kanpur 1
 For ac analysis:
CC-CE:
 i1 = (1 + 1)ii and i0 = 2i1 = 2(1 + 1)ii
 Ai = i0/ii = 2(1 + 1)  2 (Huge!)
 Ri = r1 + (1 + 1)r2  2r1
 IC2 ~ mA, IC1 ~ 10s of A, rE1 ~ k, r1 ~ 100s of
k (Huge!)
 v0/vb =  RL/rE2 and vb/vi = r2/(r2 + rE1) = 1/2
 Av = v0/vi =  RL/(2rE2) (Moderate)
 R0 = RL||r02  RL (Moderate)
 Thus, this stage has huge Ai and Ri, and
moderate Av and R0

Aloke Dutta/EE/IIT Kanpur 2

 For ac analysis:
CC-CC:
 i1 = (1 + 1)ii and i0 = (2 + 1)i1 = (2 + 1)(1 + 1)ii
 Ai = i0/ii = (2 + 1)(1 + 1)  2 (Huge!)
 Ri = r1 + (1 + 1) (2 + 1)(rE2 + RL)
 r1 + 2(rE2 + RL) (Astronomical!)
 Ri1 = r2 + (2 + 1)RL
 v0/vb = RL/(RL + rE2)
 vb/vi = Ri1/(rE1 + Ri1)
 Av = v0/vi  2RL/(2rE1 + 2RL) (Show!)
 Thus, this stage has extremely large Ai and Ri,
and Av is  1 with no phase shift
Aloke Dutta/EE/IIT Kanpur 3
 R0 = RL||R01
R01 = rE2 + rE1/(2 + 1) (by inspection)
 2rE2
 R0  RL||(2rE2) (Small)
 Above analysis is pretty straightforward, and
assumes that both 1 and 2 are high
 In reality, Q1 operates with a very low value
of IC (~ 10s of A)
 1 would drop significantly from its
nominal value  Full advantage of the
circuit can’t be exploited
Aloke Dutta/EE/IIT Kanpur 4
  Need to jack up 1
 How about using a keep-alive resistor?

VCC
C C
B C
i ib C i C
Q1 C C
vb
+
vb Q2 vb
gm2v2
R v2 r
= 2ib
Reff effi
R
–

C C C
E E E

Darlington with ac Midband Equivalent Simplified Equivalent

Keep-Alive Resistor R of Q 2-R Combination of Q 2-R Combination

Aloke Dutta/EE/IIT Kanpur 1

 R drains a constant DC current of ~ 0.7/R
 This current is supplied by Q1, along with IB2
 IC1  1
 However, this technique also changes 2
 Analysis:
ib = Ri/(R + r2)
 ic = 2ib = 2Ri/(R + r2) = gm2r2Ri/(R + r2)
= gm2(R||r2)i = gm2Reffi = effi
eff = gm2Reff < 2 (Reff = R||r2)
 Note: rE2,eff = Reff/eff = 1/gm2 = rE2 (unchanged)

Aloke Dutta/EE/IIT Kanpur 2

• npn Cascode:
R01
 CE, followed by CB v vb 0
Q
 Known as Wideband
2
v i
Q 1R L
Amplifier, due to its R 0

superior frequency R i
ac Schematic
response characteristic
 Generally, both Q1 and Q2 are biased with the
same IC
 Assuming Q1-Q2 have same :
rE1 = rE2 = rE and r1 = r2 = r

Aloke Dutta/EE/IIT Kanpur 3

 This circuit can be analyzed by inspection
 Ri = r1
 v0/vb = +gm2RL = RL/rE2 (CB Stage)
 vb/vi =  rE2/rE1 = 1
 CE Stage with Ri of Q2 (= rE2) as its load
 Thus, Av = v0/vi =  RL/rE2
 Note that Av is same as that for a CE stage,
however, the bandwidth of this circuit is far
superior than a CE stage

Aloke Dutta/EE/IIT Kanpur 4

R0 = RL||R01
 If r0 is neglected, then R01 → 
 If r0 is included, then R01 = r02 (very high)
 However, it comes in parallel with RL
 Overall R0 is still ~ RL
 Summary:
 Moderate voltage gain
 Moderate input resistance
 Potential of having very large output resistance
 Extremely large bandwidth
 Preferred over a simple CE stage

Aloke Dutta/EE/IIT Kanpur 2

 • NMOS Cascode:
r02
M2 v0 vi v0
+
+
vi M1 RL v1 gm1v1 r01 v2 RL
R01
R0 – –

–1
Ri (gm2 + gmb2) (gm2 + gmb2)v2

ac Schematic ac Midand Equivalent

 CS, followed by CG
 Generally, both M1 and M2 are biased with
the same ID
 M1 does not have body effect, but M2 has
Aloke Dutta/EE/IIT Kanpur 3
 By inspection, Ri →  and R0 = RL||R01
 With r02 present, the analysis becomes a little
complicated  neglect r02  R0 = RL
 Neglecting r02:
v0 = (gm2 + gmb2)v2RL
v2 =  gm1v1/(gm2 + gmb2 + g01) (g01 = 1/r01)
  gm1v1/(gm2 + gmb2)
[since, in general, g01 << (gm2 + gmb2)]
 Av = v0/vi =  gm1RL (since v1 = vi)
 This is same as the CS stage, however, here
broad-banding is happening!
Aloke Dutta/EE/IIT Kanpur 4
 Av gets affected a little if r01 and r02 were
included
 Since r01 comes in parallel with (gm2 + gmb2)1,
its effect on Av is less pronounced than that of
r02
 By inspection:
R01  (gm2 + gmb2)r01r02 (Show!)
 Note that if either of r01 or r02 → , R01 → 
(Why?)

Aloke Dutta/EE/IIT Kanpur 2

• Differential Amplifier (DA)/Differential
Pair (DP):
 Most versatile analog V /V CC DD

building block V i1
Vo1
 Immensely useful and DA
Vo2
V i2
widely used (particularly
V /V EE SS
for sensing/telemetry/
Symbol for DA
instrumentation applications)
 Two inputs (Vi1, Vi2)/Two outputs (Vo1, Vo2)
 Dual Supply (VCC/VDD, VEE/VSS)
Aloke Dutta/EE/IIT Kanpur 3
 Unique Property:
 Amplifies the difference between Vi1 and Vi2, while
rejecting/suppressing signals common to both Vi1
and Vi2
 Very efficient noise suppressor
 The stage can be direct coupled to the next
stage without the need for any coupling
capacitor
 In BJT technology, known as Emitter-
Coupled Pair (ECP)
 In MOS technology, known as Source-
Coupled Pair (SCP)
Aloke Dutta/EE/IIT Kanpur 4
• npn DA (ECP): VCC

 Q1-Q2 constitute a
Ic1 Ic2
RC RC
a matched pair, and have
Vo1 Vo2
their emitters connected
Q1 Q2
together, hence, the name Vi1 Ve Vi2

 IEE: DC bias current source

IEE
 All voltages and currents VEE
(apart from those used for
npn DA Topology
biasing) are instantaneous
(DC + ac)
Aloke Dutta/EE/IIT Kanpur 5
 Vbe1 = Vi1  Ve, and Vbe2 = Vi2  Ve
 KVL around Q1-Q2 BE loop:
Vi1  Vbe1 + Vbe2  Vi2 = 0
 Vbe1  Vbe2 = Vi1  Vi2 = Vid
Vid: Differential-Mode Input Voltage
 Neglecting Early effect:
Vid = VTln(Ic1/Ic2)
 Ic1/Ic2 = exp(Vid/VT) (1)
 Neglecting base currents:
Ic1 + Ic2 = IEE (always!) (2)
This is because IEE is an ideal current source
Aloke Dutta/EE/IIT Kanpur 6
 Solving Eqs.(1) and (2):
Ic1 = IEE/[1 + exp( Vid/VT)]
Ic2 = IEE/[1 + exp(Vid/VT)]
 Extremely interesting results:
 For Vid = 0, Ic1 = Ic2 = IEE/2
IEE shared equally between Q1 and Q2
 For positive Vid, Ic1 and Ic2
For negative Vid, Ic1 and Ic2
But for both cases, their sum is constant and equal
to IEE
 For Vid > 4VT, Ic1 → IEE and Ic2 → 0
For ve Vid, with |Vid| > 4VT, Ic2 → IEE and Ic1 → 0

Aloke Dutta/EE/IIT Kanpur 1

 Ic1,Ic2
IEE

Ic2 Ic1
IEE/2

0
–4VT –2VT 2VT 4VT Vid

The Current Transfer Characteristics

of an npn DA

 Linear Range of the circuit ~ 4VT (~  100

mV at room temperature)
 This range is known as the analog domain
Aloke Dutta/EE/IIT Kanpur 2
 For Vid out of this range, either Q1 or Q2
carries the entire IEE, with the other
remaining off  acts as a Current Switch
 This is the digital domain
 For analog applications, both devices must be
on and in the linear range of the Ic-Vid
characteristic
 The highest linearity, which is also the region
of the highest gm (= Ic /Vid ), occurs around
Vid = 0 (Vi1 = Vi2 )
 This is the most preferred DC bias point

Aloke Dutta/EE/IIT Kanpur 3

 At this point, IC1 = IC2 = IEE/2, and all small-
signal parameters of Q1 and Q2 are identical to
each other
 This particular biasing scheme leads to a
Balanced DA, having properties:
 Q1-Q2 completely matched
 RCs identically equal to each other
 Both inputs connected to DC ground or to the same
DC potential (ground is the best choice, obviously)
 Both Q1 and Q2 biased at IEE/2
 We will consider only Balanced DAs

Aloke Dutta/EE/IIT Kanpur 4

 Unbalanced DAs create anomalies in circuit
operation
 Now, the output voltages:
Vo1 = VCC  Ic1RC and Vo2 = VCC  Ic2RC
 Define Differential-Mode Output Voltage:
Vod = Vo1  Vo2 = IEERCtanh[Vid/(2VT)]
 Vod (positive maximum) = IEERC
 Vod (negative minimum) =  IEERC
 At Vid = 0, Vod = 0
 Permits direct coupling of stages without the need of any
coupling capacitor

Aloke Dutta/EE/IIT Kanpur 5

 IEERC Vod

Linear Range = 4VT

0 (~ 100 mV at
–4V T 4VT Vid room temperature)

–IEERC

The Voltage Transfer

Characteristics
of an npn DA

Aloke Dutta/EE/IIT Kanpur 6

 DC Biasing:
 Vi = VI + vi (VI: DC bias voltage, vi: ac small-
signal voltage)
 Ic = IC + ic (IC: DC bias current, ic: ac small-
signal current)
 The ideal DC bias point should be VI1 = VI2
 IC1 = IC2 = IEE/2
 Thus, any arbitrary DC voltage can be applied at
the bases of Q1-Q2, provided they are same
 Ideal choice: ground
 Necessitates a negative power supply for proper
biasing

Aloke Dutta/EE/IIT Kanpur 1

 Under this condition:
V01 = V02 = VCC  IEERC/2 and V0d = 0
 The simplest DC biasing IC1 IC2
scheme is to attach a resistor
REE from the common emitter Q1 Q2

point to VEE:
 IEE = ( 0.7  VEE)/REE IEE
REE
and IC1 = IC2 = IEE/2 VEE
 Both Q1 and Q2 have Simplest DC Biasing
same gm, rE, r, and r0 Scheme for npn DA
 To improve performance, any of the current sources
discussed earlier could be used in place of REE

Aloke Dutta/EE/IIT Kanpur 2

  A check is needed to see that Q1 and Q2 are biased in
the forward active region
 For this circuit, for best biasing:
VCE1 = VCE2 = (VCC + |VEE|)/3 (3-element o/p branch)
 ac Analysis:
 Balanced DAs have perfect symmetry around the
vertical cut-line going through the middle of the
circuit
 Can be analyzed using heuristics
 Known as the Half-Circuit Technique
 This technique is based on an algorithm
(Understand it thoroughly to get a clear grasp!)

Aloke Dutta/EE/IIT Kanpur 3

 Algorithm for the Half-Circuit Technique:
 Apply inputs vi1 and vi2 at the bases of Q1 and Q2
respectively
 Outputs vo1 and vo2 taken from the collectors of Q1
and Q2 respectively
 Define vid = (vi1  vi2) as the pure differential-
mode input
 Define vic = (vi1 + vi2)/2 as the pure common-mode
input
 Thus:
vi1 = vid/2 + vic
vi2 =  vid/2 + vic

Aloke Dutta/EE/IIT Kanpur 4

 Define vod = (vo1  vo2) as the pure differential-
mode output
 Define voc = (vo1 + vo2)/2 as the pure common-
mode output
 Thus:
vo1 = vod/2 + voc
vo2 =  vod/2 + voc
 Now, assuming that pure differential-mode and
pure common-mode signals are completely non-
interacting:
 Pure differential-mode output can only be caused by a
pure differential-mode input
 Pure common-mode output can only be caused by a
pure common-mode input

Aloke Dutta/EE/IIT Kanpur 5

 Based on these, define:
 Differential-Mode Gain: Adm = vod/vid
 Common-Mode Gain: Acm = voc/vic
 Thus, from the principle of superposition:
 vo1 = (Adm/2)vid + Acmvic
 vo2 =  (Adm/2)vid + Acmvic
 Thus, each output carries both differential- and
common-mode signals, however, the differential-
mode signals are out of phase, whereas the
common-mode ones are in phase
 Hence, the difference between the two outputs
carries only the differential-mode signal, with a
gain double that of a single output

Aloke Dutta/EE/IIT Kanpur 6

 The most important property of a DA is to be
able to reject common-mode signals (noise),
while amplifying the difference between the
two signals applied at its two inputs
 Characterized by a parameter known as the
Common-Model Rejection Ratio (CMRR)
(expressed in dB):
CMRR = 20log10(|Adm/Acm|)
 Ideal (Desirable) Properties:
 |Adm| →  (~ 103-105)
 |Acm| → 0 (< 1)
 CMRR →  (~ 40-120 dB)

Aloke Dutta/EE/IIT Kanpur 1

 The circuit has two inputs and two outputs:
 Four possible configurations:
 Single-ended i/p, single-ended o/p
 Single-ended i/p, double-ended o/p
 Double-ended i/p, single-ended o/p
 Double-ended i/p, double-ended o/p
 Tremendous flexibility
 Double-ended o/p eliminates the common-mode
signal completely
 However, at some point in the circuit, needs to be
converted to a single-ended o/p
 High CMRR is an absolute must!

Aloke Dutta/EE/IIT Kanpur 2

 Differential-Mode Half Circuit: Calculation
of Adm:
VCC

RC RC
ic1 ic2
vod/2 –vod/2 VCC

Q1 Q2 RC
vid/2 ve –vid/2
vod/2
ii
REE Q1
vid/2
VEE

npn DA Under Pure Differential-Mode

Differential-Mode Input Half-Circuit
Aloke Dutta/EE/IIT Kanpur 3
 Can be shown that ve = 0 in three ways:
 From the symmetry of the circuit:
Equal and opposite voltages applied at the bases of Q1 and
Q2
 The emitter potential ve got to be an average of the
inputs, which is zero
 ic1 = gm1(vid/2  ve) and ic2 = gm2( vid/2  ve)
Since gm1 = gm2, ic1 must equal  ic2 (circulating current)
(this is again from symmetry)
 ve = 0
 Drawing the complete ac low-frequency hybrid- model,
and summing currents at the common-emitter node:
Show that ve = 0
 Caution: ve = 0 will hold true only for a balanced DA

Aloke Dutta/EE/IIT Kanpur 4

 Thus, the left and right parts of the circuit become
absolutely symmetrical
 Either of the parts can be used
 Leads to the differential-mode half-circuit
 gm1 = gm2 = gm = IEE/(2VT), rE1 = rE2 = rE = 2VT/IEE,
and r1 = r2 = r = rE
 Can be easily identified to be a CE stage
 Adm = vod/vid = (vod/2)/(vid/2) =  RC/rE
 Differential-mode input resistance:
Rid = vid/ii = 2(vid/2)/ii = 2r
 The simplicity of the analysis is simply mind-
boggling!

Aloke Dutta/EE/IIT Kanpur 5

 Common-Mode Half-Circuit: Calculation of
Acm:
VCC

VCC
RC RC
RC
ic1 ic2
voc voc
voc
ii
Q1 Q2
vic ve vic Q1
vic
A
REE 2R EE

VEE

npn DA Under Pure Common-Mode

Common-Mode Input Half-Circuit

Aloke Dutta/EE/IIT Kanpur 3

 ic1 = ic2 = ic = gm(vic  ve)
 These two currents sum up at node A and flow
through REE, creating a voltage drop of 2icREE
across it
 Thus, REE can be split into two parts, 2REE each,
and each part put in the emitter leads of Q1 and Q2
 The lead connecting the two parts of REE would
not carry any current, and can be removed
 Thus, the circuit becomes perfectly symmetric
along a vertical cut-line going through the middle
of the circuit, and we can consider either of them
 Leads to the common-mode half-circuit

Aloke Dutta/EE/IIT Kanpur 4

 Can be easily identified to be a CE(D) stage
 Acm = voc/vic =  RC/(rE + 2REE)   RC/(2REE)
(since, in general, REE >> rE)
 Common-mode input resistance:
Ric = vic/ii = r + ( +1)2REE  2REE
(since, in general, REE >> r)
 Input resistance of the npn DA:
Ri = Rid||Ric  Rid = 2r (from superposition)
(since, in general, Ric >> Rid)
 CMRR = 20log10(|Adm/Acm|)  20log10(2REE/rE)

Aloke Dutta/EE/IIT Kanpur 5

 Some insights:
 Adm is independent of REE, however, Acm is a
strong function of REE
 Goal is to make Acm as close to zero as possible
 Make REE as large as possible
 High value of REE will automatically ensure high
value of CMRR (Highly desirable!)
 High CMRR can also be achieved by reducing rE
 Can be obtained by increasing the DC bias
current
 DC power dissipation of the circuit goes up
 Also, DC biasing may become suspect!

Aloke Dutta/EE/IIT Kanpur 6

 Increasing the Linear Range:
 Linear Range:  4VT (~  100 mV at room
temperature)
 For some applications, this may not be enough
 Linear Range can be increased by attaching two
identical resistors (RE) in the emitter branches of
Q1 and Q2
 Increases Linear Range by IEERE (Show!)
 This method decreases Adm (differential-mode
half-circuit becomes CE(D) topology)
 Has minimal effect on Acm
 CMRR suffers!  Not an optimal choice!

Aloke Dutta/EE/IIT Kanpur 7

• NMOS DA (SCP):
 M1-M2 constitute a VDD

perfectly matched pair, Id1 Id2

RD RD
and have their sources Vo1 Vo2
connected together, M1 M2
Vi1 Vs Vi2
hence, the name
 ISS: DC bias current ISS
source VSS

 All voltages and currents

NMOS DA Topology
are instantaneous
Aloke Dutta/EE/IIT Kanpur 1
 Vgs1 = Vi1  Vs, and Vgs2 = Vi2  Vs
 KVL around M1-M2 GS loop:
Vi1  Vgs1 + Vgs2  Vi2 = 0
 Vgs1  Vgs2 = Vi1  Vi2 = Vid
 Neglecting CLM Effect:
k N  W 
   Vgs1  VTN1  and
2
Id1 
2  L
k N  W 
   Vgs2  VTN 2 
2
Id 2 
2  L

Aloke Dutta/EE/IIT Kanpur 2

 Ran into a problem, since both M1 and M2
would have body effect present
 Both bodies connected to VSS, but the common
source node is at a floating potential Vs
 Analytical evaluation of Id1 and Id2 becomes
pretty tedious
 If the CLM effect is also included, then the
problem would need numerical solution!
 To get a first-order estimate, neglect body
effect
 VTN1 = VTN2 = VTN0

Aloke Dutta/EE/IIT Kanpur 3

 Thus:

Id1  Id 2
Vid  1
k N  W 
 
2  L

 Also:
Id1 + Id2 = ISS (2)
 Solving Eqs.(1) and (2):
Id1 = ISS/2 +  and
Id2 = ISS/2  
Aloke Dutta/EE/IIT Kanpur 4
 k N  W  4ISS
   id 
V  V 2

k N  W L
id
4  L

 For Vid = 0,  = 0, and Id1 = Id2 = ISS/2

 Most preferred DC bias point of the circuit
 For Vid > 0, Id1 and Id2
 For Vid < 0, Id1 and Id2
 But for both cases, the sum of Id1 and Id2
remains constant at ISS
 Linear Range of this circuit is defined by the
values of Vid, which turns either M1 or M2 off

Aloke Dutta/EE/IIT Kanpur 5

 To find the Linear Range, use Eq.(1) and put
either Id1 or Id2 equal to ISS:
2ISS  2Id1 
 Vid     2 
k N  W L   k N  W L  
  Vid 0
  2  V  V
id  0

since for Vid = 0, ISS = 2Id1 = 2Id2

V = Gate Overdrive for M1/M2 for Vid = 0
 Thus, the Linear Range is a function of ISS
and (W/L)  Tremendous flexibility!
 Recall: In npn DA, this Linear Range was
4VT, and depended only on temperature
Aloke Dutta/EE/IIT Kanpur 6
 ISS Id1,Id2

V increasing Id1
ISS/2
Id2

0
Vid

The Current Transfer Characteristics

of an NMOS DA

Aloke Dutta/EE/IIT Kanpur 7

 Differential Current:
Id = Id1  Id2 = 2
 Differential-Mode Output Voltage:
Vod = Vo1  Vo2 = (VDD  Id1RD)  (VDD  Id2RD)
= (Id)RD = 2RD
 Note:
 When Vid = 0,  = 0, Id = 0, and Vod = 0
 This is the perfect DC bias point
 No need for interstage coupling capacitor
 ID1 = ID2 = ISS/2
 VId = 0  Tie both gates to ground and use a
negative power supply
Aloke Dutta/EE/IIT Kanpur 1
 ac Analysis:
 The procedure adopted for npn DA can be lifted
verbatim
 Differential-Mode Half-Circuit: Calculation
of Adm:
VDD
 The common-source node is
RD
at ac ground (from symmetry)
 Body is also at ac ground vid/2
vod/2

 vbs = 0  gmbvbs = 0 M1

 Simple CS stage:
 Adm = vod/vid =  gmRD Differential-Mode
gm = kNV Half-Circuit

Aloke Dutta/EE/IIT Kanpur 2

 Common-Mode Half-Circuit: Calculation of
Acm: V DD

 CS(D) stage, but now with RD

body effect present
voc
 Acm = voc/vic vic
M1
=  gmRD/[1 + (gm + gmb)2RSS]
 Thus: 2R SS

CMRR = 20log10(|Adm/Acm|)
 20log10[2(gm + gmb)RSS] Common-Mode
 Again, RSS plays no role in Half-Circuit

Adm, but determines Acm and CMRR

 A high value of RSS highly desirable
Aloke Dutta/EE/IIT Kanpur 3
 Actual situation is not so rosy and hunky-dory
 The DA can become unbalanced if there is a
mismatch between the devices and/or the
resistors, and our analysis would fail!
 Gives rise to offset voltage (for both npn and
NMOS DA) and offset current (only for npn
DA)
 This mismatch is caused by technology and is
totally random
 Fortunately, the effect is not that severe, since
there are technological innovations to match
devices and/or resistors
Aloke Dutta/EE/IIT Kanpur 4
 Actively Loaded
Amplifier Stages
• Main Goal: To reduce usage of resistors as
much as possible and use transistors
instead as active load
• Interesting to note that transistors offer
much higher resistance than physical
resistors, while occupying much smaller
chip area
Aloke Dutta/EE/IIT Kanpur 5
• npn CE Stage With pnp Active Load:
 Q1: Driver, Q2: Load VCC

 Identify Q2-Q3 as a
pnp current mirror
Q2 Q3
 Q2-Q3 constitute a IC2
A
matched pair
IREF
IC1
 Neglecting base currents: Vo

IC2 = IREF Vi
Q1
Vi = VI + vi
 Biasing of the circuit is Vo = V0 + vo

tricky Circuit Diagram

Aloke Dutta/EE/IIT Kanpur 1

 There is a trivial solution of IC1 = IC2 = 0, and
the circuit collapses
 For proper biasing, IC1 must equal IC2 (= IREF)
 Thus, VI should be properly adjusted, such
that:
VI = VTln(IREF/IS1)
 Such a high precision in VI may not be
practically achievable
 Use a resistor in series with VI and self-
consistently solve for the bias point

Aloke Dutta/EE/IIT Kanpur 2

  ac Analysis:

–
gm2v2 r02 r v2 rE3
+
vi vi vo
A
vo
+ +
r v1 gm1v1 r01 r v1 gm1v1 r01 r02
– –
Ri R0

ac Midband Equivalent Simplified Equivalent

Aloke Dutta/EE/IIT Kanpur 3

 First, note that Q3 is diode-connected (BC short)
 The equivalent of Q3 is simply a resistor rE3
 Node A is a peculiar one, and can be considered
open or short both!
 Open because the current source IREF is ideal
 Short because the base of Q2-Q3 is at a fixed DC
potential, and thus ac ground
 In either case, v2 = 0  gm2v2 disappears!
 Leads to the simplified equivalent
 By inspection: Ri = r1 and R0 = r01||r02
 Av = vo/vi =  gm1R0 =  1/(n + p)
n = VT/VAN and p = VT/VAP
 Enormously large gain possible!

Aloke Dutta/EE/IIT Kanpur 4

 p-channel MOSFET (PMOS)
• Before moving to NMOS stages with active
load, it will be prudent to visit some details
regarding PMOS S
+ + +
• Substrate: n-type (ND) V
V SG
SB

 Bulk Potential: – –
G B VSD
F = VTln(ND/ni)
ID
• Source/Drain: p+ –
D
• Channel Carriers: Holes
PMOS
Aloke Dutta/EE/IIT Kanpur 1
• Threshold Voltage:
VTP  VTP0    2F  VBS  2F 
VTP0: Zero back-bias threshold voltage (negative)
 Body effect coefficient:
2qs N D

Cox
 VBS  0 (to prevent forward biasing of SB junction)
 With back bias, VTP becomes more negative
 VGS has to be less than VTP to turn device on

Aloke Dutta/EE/IIT Kanpur 2

• Current-Voltage Relation:
 Both VGS and VDS negative
 ID flows from source to drain (the same
direction of flow as holes)
 In saturation [|VDS| > (|VGS|  |VTP|)]:
k P W
  
2
ID  VGSp  VTP 1   p VDSp
2 L
 In non-saturation [|VDS| < (|VGS|  |VTP|)]:


W

VGSp  VTP VDSp  VDSp 2 
2
I D  k P
L  

Aloke Dutta/EE/IIT Kanpur 3

 k P   p Cox
 Process transconductance parameter
p = Channel hole mobility
• Based on the value of VTN0 and VTP0, there
are two classifications:
 Enhancement Mode: Normally Off (with VGS
= 0)
 VTN0 positive and VTP0 negative
 Depletion Mode: Normally On (with VGS = 0)
 VTN0 negative and VTP0 positive

Aloke Dutta/EE/IIT Kanpur 4

 Symbols
D S D S
+
+ +
ID VSG
VSB
VDS
– –
G B G B G B G B
+ +
VSD
ID
VGS VBS
–
– –
S D S D
Enhancement Enhancement Depletion Depletion
Mode NMOS Mode PMOS Mode NMOS Mode PMOS

• Note the thick band in the channel region

for depletion mode devices, which implies
that channel is present even with VGS = 0
Aloke Dutta/EE/IIT Kanpur 5
• Variants of Actively Loaded CS Stage:
 Saturated Enhancement Load
 Depletion Load
 Complementary PMOS Load
 Also known as CMOS Gain Stage
• The last one is the most popular

Aloke Dutta/EE/IIT Kanpur 1

• Saturated Enhancement Load:
 Both bodies tied to ground VDD

 For M1: VSB1 = 0 M2

 For M2: VSB2 = Vo Vo
 M2 is enhancement mode Vi
 VTN02 positive M1
 M2 is also diode-connected
 Always operates in saturation
Circuit Schematic
 M2 has a floating body effect
problem: Vo is a variable and VTN2 will
continuously change with a change in Vo
Aloke Dutta/EE/IIT Kanpur 2
 For M2 to remain on, its VGS2 (= VDD  Vo)
must be > VTN2
 Thus, there is a maximum possible Vo, beyond
which it cannot rise (M2 would cut off)
 To estimate this maximum Vo, for the time
being, neglect that 3VT cushion
 Then:
VDD  Vo,max > VTN2 (with VSB2 = Vo,max)
VTN2  VTN02    2F  Vo,max  2F 
Aloke Dutta/EE/IIT Kanpur 3
  Solution of this equation would give Vo,max
 Once Vo,max is obtained, the best bias point
would be at V0 = Vo,max/2
 Before doing ac analysis, let’s investigate M2:
short
G2 D2 G 2, D 2

+
vgs2 gm2vgs2 gmb2vbs2 r02
Reff =
B2 –1
(gm2 + gmb2 + g02)
+ vbs2 –

S2 vo vgs2 = vbs2 = –vo S2

Simplified
ac Midband Equivalent of M 2
Equivalent

Aloke Dutta/EE/IIT Kanpur 4

 Thus, the complete equivalent:
 By inspection: Reff
v
vo
 g m1  r01  R eff 
i

Av  +
vo
vi v gs1 gm1vgs1 r01

g m1
 –

g m2  g mb2  g 01  g 02
Complete Equivalent
 Now, in general,
(gm2 + gmb2) >> (g01 + g02)
g m1 g m1
 Av   
g m2  g mb2 g m2 1   2 

Aloke Dutta/EE/IIT Kanpur 3

 
2 
2 2F  V0Q
V0Q = Quiescent DC output voltage
 Now, if M2 can be put in its separate island,
then S2 and B2 can be connected together
 vsb2 = 0  gmb2vsb2 = 0

g m1  W L 1
 Av   
g m2  W L 2
 R0 = (gm2 + gmb2 + g01 + g02)1

Aloke Dutta/EE/IIT Kanpur 4

 Insights:
 Vo doesn’t go all the way to VDD
 Full rail-to-rail swing can’t be achieved
 When Vo falls below V of M1, it leaves the
saturation region, and enters non-saturation region
 Distortion will set in at the output
 Even for a moderate voltage gain of 10, the ratio of
the aspect ratios of M1 and M2 has to be 100!
 All these problems coupled together make this
circuit highly unattractive for practical use

Aloke Dutta/EE/IIT Kanpur 5

• Depletion Load:
VDD
 M2 is depletion mode,
having negative VTN0 M2
Vo
(denoted by VTD0)
Vi
 Back bias of M2:
M1
VSB2 = Vo
 With Vo, VTD2 changes
Circuit Schematic
 Maximum Vo desired = VDD
 This is also the maximum
back bias of M2

Aloke Dutta/EE/IIT Kanpur 6

 M2 has GS short  VGS2 = 0
 Even with Vo = VSB2(max) = VDD, VTD2 should
remain negative with a cushion of at least 100
mV
 VTD2 with VSB2 = VDD should be 100 mV
 VTD0 should be chosen based on this
 Now, VDS2(min) = VDD  Vo(max) = 0
 Under this condition, VGS2  VTD2 = V2 = 100
mV
 M2 is in the linear region (since VDS2 <
V2)
Aloke Dutta/EE/IIT Kanpur 7
  This has to be lived with, and slight distortion
would appear at the output as Vo → VDD
 For best biasing, V0Q = VDD/2
 Fixes the DC operating point
 Before doing ac analysis, let’s investigate M2:
D2 D2
vbs2 = –vo
gmb2vbs2 r02
Reff =
B2 –1
(gmb2 + g02)
+ vbs2 –
GS short vgs2 = 0
G2, S2 vo  gm2vgs2 = 0 G2, S2

ac Midband Equivalent of M 2 Simplified

Equivalent

Aloke Dutta/EE/IIT Kanpur 3

 Thus, the complete equivalent:
 By inspection:
vo Reff
Av   g m1  r01  R eff  v i

vi +
vo

v gm1vgs1 r01
g m1 gs1


g mb2  g 01  g 02 –

 Now, in general, Complete Equivalent

gmb2 >> (g01 + g02)

g m1 g m1 1  W L 1
 Av    
g mb2  2 g m2 2  W L 2
Aloke Dutta/EE/IIT Kanpur 4
 
2  1
2 2F  VDD 2
 Improvement as compared to previous stage
 Now, if M2 can be put in its separate island,
then S2 and B2 can be connected together
 vsb2 = 0  gmb2vsb2 = 0
g m1
 Av  
g 01  g 02
 Can be very large (a magnitude greater
than 100 is possible)

Aloke Dutta/EE/IIT Kanpur 5

 R0 = (gmb2 + g01 + g02)1 (with body effect)
 R0 = (g01 + g02)1 (without body effect)
 The latter case produces very high R0
 Thus, this circuit produces much superior
performance as compared to the saturated
enhancement load, in terms of:
 Rail-to-rail swing
 With island technology:
 Very large Av and R0
 Without island technogy:
 Moderate Av and R0

Aloke Dutta/EE/IIT Kanpur 6

• Complementary PMOS Load:
 Also known as CMOS Gain Stage
 CMOS (Complementary MOS: Having both
NMOS and PMOS in the circuit)
 The Ultimate: Much superior performance
and outclasses all other gain stages
 Widely used
 High Av and R0
 Easy to bias and easy to operate
 Design also extremely simple
 Doesn’t produce any anomalies
Aloke Dutta/EE/IIT Kanpur 7
 VDD

r02
M2 M3
vi vo
A
+
Vi Vo gm1vgs1 r01
IREF vgs1
M1
R0
–

Circuit Schematic ac Midband Equivalent

 M1 body connected to ground, M2-M3

bodies connected to VDD
 No body effect problem for any of the devices
(biggest advantage of this circuit)
Aloke Dutta/EE/IIT Kanpur 1
 Identify M2-M3 as a PMOS current mirror
(perfectly matched)
 ID1 = ID2 = ID3 = IREF
 This gives the required value of VI
 DC biasing of the circuit is pretty
straightforward
 For ac analysis, we note that node A is both
open and short at the same time (similar to npn
gain stage with pnp active load)
 Av = vo/vi =  gm1R0
R0 (= r01||r02): Output resistance of the circuit
Aloke Dutta/EE/IIT Kanpur 2
 Caution: r01  r02, even though M1 and M2 carry
the same DC bias current, since n  p (in
general)
 This circuit is immensely useful since it gives
extremely large voltage gain and output
resistance
 Only problem is that it needs a PMOS current
mirror, thus necessitating use of an extra PMOS
 An even better design exists, which eliminates
the need for this extra PMOS

Aloke Dutta/EE/IIT Kanpur 3

• A Better CMOS Gain Stage:
 No body effect issue VDD

 However, there are some Mp

design issues Vi Vo
 Mn-Mp have same magnitude
of the threshold voltage: Mn

VTN0 = |VTP0|
 Process transconductance
Circuit Schematic
parameters:
k N   n Cox and k P   p Cox

Aloke Dutta/EE/IIT Kanpur 4

 Oxide capacitance per unit area  Cox  ox t ox 
same for both devices, since they have same
tox
 However, n ~ 2p (for Si)
 Thus, k N  2k P
 Ideal DC bias point of the circuit is VI = V0 =
VDD/2 (yields VGSn = |VGSp| and VDSn = |VDSp|)
 Can be achieved only if the stage is completely
balanced (same threshold voltage magnitude
and same device transconductance parameter)
 Thus, kN and kP need to be matched

Aloke Dutta/EE/IIT Kanpur 5

 Can be achieved by making (W/L)p = 2(W/L)n
 If CLM effect is not that important, or if n =
p, then this procedure works out just fine
 However, if n  p, then for balancing the
circuit, the following relation must hold
(show!):
kP(1 + pVDD/2) = kN(1 + nVDD/2)
 Under this condition, kN  kP, but the circuit
will be perfectly matched and balanced
 Known as: Stage unmatched by nature, but
matched by performance

Aloke Dutta/EE/IIT Kanpur 6

 ac Analysis:

–
vgsp
gmpvgsp r0p
vi + vi vo
vo
+
R0 =
gmnvgsn r0n (gmn+g mp)vi
vgsn (r 0nr0p)
–

ac Midband Equivalent Simplified Equivalent

Aloke Dutta/EE/IIT Kanpur 4

 By inspection:
Av =  (gmn + gmp)R0
=  (gmn + gmp)/(g0n + g0p)
R0 = r0n||r0p = (g0n + g0p)1
 Very high Av and R0
 Extremely popular and widely used circuit
 Sometimes, level shifters are used at the input
for better ease of application

Aloke Dutta/EE/IIT Kanpur 5

• Actively Loaded DA:
VDD
VCC

Q3 Q4 M3 M4
i3 i4 i3 i4

i1 vo i1 vo
i2 i2
io io
vi1 vi2 vi1 vi2
Q1 Q2 M1 M2
ve vs

IEE ISS

VEE VSS

BJT Implementation MOS Implementation

Aloke Dutta/EE/IIT Kanpur 1

 Absolutely similar topologies for both BJT
and MOS implementations
 Produces double-ended to single-ended
conversion, i.e., from two inputs to a single
output
 Q1-Q2/M1-M2/Q3-Q4/M3-M4 perfectly matched
 Output should never be taken from
collector/drain of Q1/M1 (Why?)
 DC biasing is absolutely straightforward with
all branch currents equal to IEE/2 or ISS/2

Aloke Dutta/EE/IIT Kanpur 2

 Caution: Half-circuit technique can’t be used
for this circuit, since collector/drain circuits of
the two sides are coupled, i.e., i3 = i4 (always)
 This circuit can be analyzed by inspection
 Define vid = vi1  vi2
 Apply +vid/2 at the base of Q1/gate of M1
 Apply vid/2 at the base of Q2/gate of M2
 From symmetry of the circuit around the
BE/GS loops, the common emitter/source node
is at ac ground (i.e., ve = vs = 0)

Aloke Dutta/EE/IIT Kanpur 3

 Since vs = 0, M1-M2 won’t have any body
effect issue
 Now, i3 = i4 (mirror), i3 = i1 (same branch),
and i2 =  i1 (symmetry)
 Also, i1 = gmvid/2 and i2 =  gmvid/2
gm = IEE/(2VT) (BJT Implementation)
= (kNISS)1/2 (MOS Implementation)
 Hence, the short-circuit output current (with
the output terminal shorted to ground):
io = i4  i2 = i1  i2 = 2i1 = gmvid

Aloke Dutta/EE/IIT Kanpur 4

 To find the output voltage, we need to use the
Thevenin technique:
 Open-Circuit Voltage = Short-Circuit Current 
Thevenin Resistance
 Thevenin Resistance (looking from the output):
R0 = r02||r04
 Thus, the output voltage:
vo = ioR0 = gm(r02||r04)vid
 Hence, the differential-mode gain:
Adm = vo/vid = +gm(r02||r04)
 Ri = 2r (BJT Implementation)
Aloke Dutta/EE/IIT Kanpur 5
 Ex.: Prove the expressions for Adm and Ri
from the hybrid- model
 Acm for this circuit is a little difficult to
evaluate
 However, the CMRR can be safely
approximated as:
CMRR  20log10(2gmREE)
REE: Output resistance of the bias current
source IEE/ISS
 In order to improve CMRR, various current
source topologies can be used

Aloke Dutta/EE/IIT Kanpur 6

• Example: Simple npn CM
 One of the simpler choices To the common-
emitter node
 Q5-Q6 perfectly matched of the DA

 Neglecting base currents: VCC

V0
IREF
R
IREF = IEE = IC6 IEE = IC6

= (VCC  VBE  VEE)/R

Q5 Q6
 REE = r06 = VA/IEE
 Acts as a current source of
magnitude IEE with a shunt VEE

resistance REE

Aloke Dutta/EE/IIT Kanpur 7

• Insights:
 Recall: Adm independent of REE, but Acm and
CMRR strongly depend on REE
 To maximize CMRR, REE should be increased
as much as possible
 To increase REE, other current sources
discussed in class, e.g., ratioed mirror,
cascode, Widlar, etc., can be used
 Note that with more advanced architectures,
V0(min) increases, and may become a limiting
factor!

Aloke Dutta/EE/IIT Kanpur 8