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Complex Logic Circuits

To realize complex logic functions, the basic circuit structures used for simple NOR and NAND gates can be extended. Complex logic gates can be designed using a small number of transistors. As an example, a complex logic gate is shown that realizes the Boolean function Z = A(D+E)BC. The design principle is that OR operations use parallel connections and AND operations use series connections. Various input configurations lead to different resistances and output voltage levels (VOL), classified from lowest (Class 1) to highest (Class 4). Transistor sizing ensures the worst case Class 1 path meets the specified VOL level.

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Niveditha Nisanam
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830 views3 pages

Complex Logic Circuits

To realize complex logic functions, the basic circuit structures used for simple NOR and NAND gates can be extended. Complex logic gates can be designed using a small number of transistors. As an example, a complex logic gate is shown that realizes the Boolean function Z = A(D+E)BC. The design principle is that OR operations use parallel connections and AND operations use series connections. Various input configurations lead to different resistances and output voltage levels (VOL), classified from lowest (Class 1) to highest (Class 4). Transistor sizing ensures the worst case Class 1 path meets the specified VOL level.

Uploaded by

Niveditha Nisanam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Complex Logic Circuits

To realize arbitrary Boolean functions of multiple input variables, the basic circuit
structures and design principles developed for simple NOR and NAND gates in the previous
sections can easily be extended to complex logic gates. The ability to realize complex logic
functions using a small number of transistors is one of the most attractive features of nMOS
and CMOS logic circuits.
Consider the following Boolean function as an example.

The nMOS depletion-load complex logic gate that is used to realize this function is
shown in Figure below.

Inspection of the circuit topology reveals the simple design principle of the pull-down network:

 OR operations are performed by parallel-connected drivers.


 AND operations are performed by series-connected drivers.
 Inversion is provided by the nature of MOS circuit operation.
The design principles stated here for individual inputs and corresponding driver transistors can
also be extended to circuit sub-blocks, so that Boolean OR and AND operations can be
performed in a nested circuit structure. Thus, we obtain a circuit topology which consists of
series- and parallel-connected branches, as shown above.
In the circuit above, the left nMOS driver branch consisting of three driver transistors is used
to perform the logic function A(D + E), while the right-hand side branch performs the function
BC. By connecting the two branches in parallel, and by placing the load transistor between the
output node and the power supply voltage VDD, we obtain the complex function given in
equation Z. Each input variable is assigned to only one driver. For the analysis and design of
complex logic gates, we can employ the equivalent-inverter approach already used for the
simpler NOR and NAND gates. It can be shown for the circuit in Fig. above that, if all input
variables are logic-high, the equivalent-driver (WIL) ratio of the pull-down network consisting
of five nMOS transistors is

For calculating the logic-low voltage level VOL' we have to consider various cases, since the
value of VOL actually depends on the number and the configuration of the conducting nMOS
transistors in each case. All possible configurations are tabulated below. Each configuration is
assigned a class number which reflects the total resistance of the current path from V out node
to ground.

A- D Class 1
A- E Class 1
B-C Class 1
A-D-E Class 2
A-D-B-C Class 3
A-E-B-C Class 3
A-D-E-B-C Class 4
Assuming that all driver transistors have the same (WIL) ratio, a Class 1 path such as (B-
Circuits C) has the highest series resistance, followed by Class 2, Class 3, etc. Consequently,
the logic-low voltage levels corresponding to each class have the following order, where each
subscript numeral represents the class number.
VOLI > VOL 2 > VOL3 > VOL4

The design of complex logic gates is based on the same ideas as the design of NOR and NAND
gates. We usually start by specifying a maximum VOL value. The design objective is to
determine the driver and load transistor sizes so that the complex logic gate achieves the
specified VOL value even in the worst case. The given VOL value first allows us to find the
(W/L)Ioad and (WIL)driver, ratios for an equivalent inverter. Next, we have to identify all worst-
case (Class 1) paths in the circuit, and determine the transistor sizes in these worst-case paths
such that each Class 1 path has the equivalent driver ratio of (W/L) drive’.
In this example, this design strategy yields the following ratios for the three worst case paths.
The transistor sizes found above guarantee that, for all other input combinations, the logic-low
output voltage lever will be less than the specified VOL’.

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