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Design Guide: TIDA-010239

AC Level 2 Charger Platform Reference Design

Description Features
Electric vehicle service equipment (EVSE) facilitates • Ultra-low standby UCC28742-based isolated 29-W
power delivery to electric vehicles safely from the AC/DC stage to improve energy efficiency
grid. An EVSE control system consists of an auxiliary • Supercapacitor backup supplying up to 7.5 W for 3
power stage, an off-board AC/DC high-power stage seconds during energy storage release (AC mains
(only in DC charging stations), energy metering unit, failing)
AC and DC residual current detector, an isolation • Tight output voltage regulation (< ±5%) of low
monitor unit, relays and contactors with drive, two- dropouts (LDO) and the high slew rate of the
way communication over single wire, and service TLV1805 device for control pilot interface
and user interfaces. This reference design highlights • Ultra-low standby as well as cost-optimized
an ultra-low standby isolated AC/DC auxiliary power converters and linear regulators to power up
stage followed by converters and linear regulators, a points-of-load
comparator-based control pilot interface to meet the • DRV8220 current controller to drive high-current
IEC61851 standard, an efficient relay and contactor relays and contactors for thermal protection, RCD
drive, plug lock motor driver, flux gate circuit to AC and DC detection, and plug lock control
detect AC and DC currents for RCD applications, and • Isolated line voltage sensing using the ISO1212
isolated line voltage sensing across the relay and digital-input receiver for welded relay and
contactor. contactor detection

Resources Applications
• AC charging (pile) station
TIDA-010239 Design Folder
UCC28742, TLV1805 Product Folder
ISO1212, DRV8220 Product Folder
ADC122S051 Product Folder
TPS7A39, TPS7A20, ATL431, TL431 Product Folder
TPS563210A, TPS55330 Product Folder
TPS259470, TL7705A Product Folder

Ask our TI E2E™ support experts

Type 2 Electric
Connector Vehicle Inlet

RCD
A AC & DC A A 1

B B B
2

C C C
3

Neutral Neutral Neutral 4

Isolated Power
RCD Relay Driver MCU
Supply &
Weld Detect
Backup Supply
EVSE GND PE
5

Pilot
Pilot Wire Wire 6
MCU

Plug
Lock 7
Plug Lock Driver

Connector to AM62x Board

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1 System Description
Electric vehicles (EVs), including plug-in hybrid electric vehicles (PHEVs), receive energy from the electrical grid through electric vehicle supply
equipment (EVSE), more commonly known as EV chargers. To facilitate the power delivery to the vehicle, the EVSE sits between a stable grid
connection and the vehicle as shown in Figure 1-1.

Type 2 Electric
Connector Vehicle Inlet

RCD
A AC & DC A A 1

B B B
2

C C C
3

Neutral Neutral Neutral 4

Isolated Power
RCD Relay Driver MCU
Supply &
Weld Detect
Backup Supply
EVSE GND PE
5

Pilot
Pilot Wire Wire 6
MCU

Plug
Lock 7
Plug Lock Driver

Connector to AM62x Board

Figure 1-1. AC Level 2 Charger High-Level Block Diagram

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The primary EVSE functionality includes:

• Regulated electrical current - makes sure that the best possible current is provided and falls within the
maximum current the EV can handle.
• AC/DC residual current detection (RCD)
• Relay and contactor drive and latched contact detection
• Energy metering
• Automatic disconnect - when a hardware fault is detected, the power is shut off, to avoid risks like battery
damage, an electrical short, or a fire.
• Safety lock-out feature - prevents current from flowing when the charger is not connected to an EV.
An EVSE control system mainly consists of auxiliary power stage, off-board AC/DC high power stage (only in
DC charging stations), energy metering, AC and DC residual current detection, isolation monitor unit, relays and
contactors with drive, two-way communication, and service and user interfaces.
1.1 EV Charging Station Challenges
The EVSE design for EV charging stations presents several challenges including those presented in the
following sections.
1.1.1 SAE J1772 or Equivalent Standard Compliant EV Charging Stations
Many electric vehicle manufacturers have adopted the SAE J1772 standard for electrical connections to an EV.
The same specifications also translate into international localizations, with differing form factors. The control
pilot is the primary control conductor and is connected to the equipment ground through control circuitry on the
vehicle and performs the following functions:
• Verifies that the vehicle is present and connected
• Permits energization and de-energization of the supply
• Transmits supply equipment current rating to the vehicle
• Monitors the presence of the equipment ground
• Establishes vehicle ventilation requirements
Table 1-1 shows the SAE J1772 standard mandates control pilot circuit generator parameters.
Table 1-1. Control Pilot Signal Generator Parameters per SAE J1772
PARAMETER(1) MIN NOM MAX UNITS
Voltage high, open circuit 11.40 12.00 12.60 V
Voltage low, open circuit –11.40 –12.00 –12.60 V
Frequency 1000 Hz
Pulse width(2) 5 µs
Rise time(3) 2 µs
Fall time(3) 2 µs
Settling time(4) 3 µs

(1) Tolerances to be maintained over the environmental conditions and useful life as specified by the manufacturer
(2) Measured at 50% points of complete negative-to-positive or positive-to-negative transitions
(3) 10% to 90% of complete negative-to-positive transition or 90% to 10% of complete positive-to-negative transition measured between
the pulse generator output and R1. Note that the term generator refers to the EVSE circuitry prior to and driving the 1-kΩ source
resistor with a ±12-V square wave. This circuitry must have rise and fall times faster than 2 μs. Rise and fall times slower than 2 μs
begin to add noticeably to the output rise and fall times dictated by the 1-kΩ resistor and all the capacitance on the pilot line.
(4) To 95% of steady-state value, measured from the start of transition

1.1.2 AC and DC Leakage, Residual Current Detection (RCD)

The primary requirement in providing protection during EV charging is the ability to detect AC and DC residual
currents and thereby mitigate the risk of electric shock or fire.
1.1.3 Efficient Relay and Contactor Drive
In normal use cases, high-current relays or contactors can typically draw 10s to 100s of milliamps as an
inductive load, requiring specific drive architectures. Because of the amount of time that a relay or contactor
requires to remain powered, an efficient drive solution is preferred to avoid thermal problems.

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1.1.4 Contact Weld Detection

For safety reasons, detecting the output voltage of the relay and contactor is critical. The contacts can
experience arcing and become fused together, providing power to the plug even when not powered by the
system. Checking that the operation completed correctly is important and is to be done every time the relay is
opened.
This reference design showcases ultra-low standby isolated AC/DC auxiliary power stage followed by ultra-low
IQ as well as cost-optimized converters and linear regulators, comparator-based control pilot interface to meet
SAE J1772 standard, efficient relay and contactor driver design, and digital isolator based line voltage sensing to
detect fusing of relay and contactor contacts due to arcing.
1.2 Key System Specifications
Table 1-2. Key System Specifications
PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT DETAILS
INPUT CHARACTERISTICS
Input voltage,VIN 85 120, 230 460 VRMS Line voltage
Line frequency, fLINE 47 60, 50 63 Hz
OUTPUT CHARACTERISTICS
Output voltage, VOUT1 Flyback output 1 12 V UCC28742-based AC/DC flyback
power stage with 3 outputs
Output current, IOUT1 2.2 A
Output voltage, VOUT2 Flyback output 2 14 V
Output current, IOUT2 0.1 A
Output voltage, VOUT3 Flyback output 3 –14 V
Output current, IOUT3 0.1 A
Total output power, POUT Output power of flyback power
28.8 W
stage
POINT OF LOAD AND AUXILIARY SECTION CHARACTERISTICS
TPS7A3901 Dual LDO +12 V Nominal current = 100 mA
TPS7A3901 –12 V Nominal current = 100 mA
TPS76318 LDO +1.8 V Nominal current = 30 mA
TPS259470 eFuse +5 V Overcurrent protection = 4.5 A
TPS563210A Sync-Buck +5 V Nominal current = 1.2 A, 1.3 A max
TPS563210A Sync-Buck +3.3 V Nominal current = 0.8 A, 1.5 A max
TPS65130 Dual converter (Boost + Nominal current = 0.1 A
inverting-Buck/Boost)” active ± 14 V
during energy storage release
TPS55330 Non-sync Boost: active during Nominal current = 1.8 A
+11.5 V
energy storage release
SUPERCAPACITOR BACKUP CHARACTERISTICS
Supercap normal 2 × 2.5-μF supercapacitors Peak current = 4.06 A, for 1 s from
operating voltage in series. Charger charges to full rate voltage to half voltage.
7.8 V. Boost UVLO sets min
operating voltage to 4.3 V. +4.3 +7.8 V
Supplying 7.5 W for 3 s (after
boost) during energy storage
release (AC mains failing)
TL7705A Voltage supervisor for EoC of Threshold for End of Charge
2 × 2.5-μF supercapacitors in +7.49 V
series
Linear charger Charges supercapacitors from 0
V to 7.8 V in 81 s and from 4.3 V +120 mA
to 7.8 V in 36 s

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2 System Overview
2.1 Block Diagram
Type 2 Electric
Connector Vehicle Inlet

RCD
A AC and DC A A 1

B B B
2

C C C
3

Neutral Neutral
Neutral
4
12 V 12 V

12 V DRV8220 DRV8220
UCC28742 Single-Channel Single-Channel Drive
Constant-Voltage 14 V Relay Low-Side Relay Low-Side
Controller 3.3 V ISO1212
Constant-Current Controller
Isolated 24-V to 60-V
Flyback –14 V
Digital Input Receiver

MCU MCU
EVSE GND PE
5

14 V 12 V * -12 V *
12 V *
TPS7A39 ATL431
Dual, 150-mA, Wide 2.5-V low-IQ
-14 V VIN Positive and Adjustable Precision OPA189 and TLV172
Negative LDO -12 V * Precision and General 12 V *
Shunt Regulator
Purpose Op Amps for
RCD Filter
Pilot
Control Pilot
12 V TL7705A TLV1805 Monitoring
TPS563210A Wire 6
5-V Single-Supply µ-Power Circuit
17-V, 3-A Step- 5V
Voltage Supervisor
Down Converter
With Programmable 3.3 V
With Eco-mode
Delay Time 3.3 V
-12 V *
12 V ADC122S051
TPS563210A TPS259470Fault 200 kSPS to 500 kSPS
17-V, 3-A Step- 3.3 V 2.7-V to 23-V, 28-
Flag 12-bit ADC Pilot Control &
Down Converter m
, 5.5-A eFuse MSP430F5132 Proximity
With Eco-mode™
12 V

3.3 V TPS7A20 3.9 V Plug

TPS55330 DRV8220
300-mA, 24-V, 5-A, 11.5 V Lock
1.8 V Single-Channel 7
Ultra-Low-IQ, Wide Input Range Relay Low-Side
Ultra-Low-Noise Boost DC-DC AC Power
Controller
LDO GND
DC Input
POL Power Supply Super Cap Back-up Power Supply DC Output
Logic Signal
Isolation
Connector to AM62x Board Analog Signal

Figure 2-1. TIDA-010239 Block Diagram

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2.2 Design Considerations

2.2.1 Isolated AC/DC Power Supply Design
The isolated AC/DC power stage is multiple outputs winding flyback stage based on the UCC28742 device.
The UCC28742 controller provides constant-voltage (CV) using an optical coupler to improve transient response
to large-load steps. Constant-current (CC) regulation is accomplished through primary-side regulation (PSR)
techniques. This device processes information from the optocoupled feedback and an auxiliary flyback winding
for precise high-performance control of the output voltage and current. Figure 2-2 shows the system block
diagram for the power supply design and the design parameters are shown in Table 2-1.
These are the main components of the power supply:
• A three-phase input flyback with synchronous rectification supplies three voltages: 12 V (power) and ± 14 V
(low power)
• Two buck converters (based on TPS563210), one dual-LDO (TPS7A3901) and a second LDO (TPS7A2018)
take the power from the flyback and supply further 5 V, 3.3 V, 1.8 V, and ± 12 V
• Two supercapacitors, 2.5 μF each are connected in series and are charged by means of a 120-mA constant
current linear regulator, setting the charging voltage to 7.8 V
• A boost converter with TPS55330 supplies all voltages as soon as mains power is missing
• A further 12-V input port, protected against overcurrent and reverse polarity, is managed by the eFuse
TPS259470, useful during debug. This way the whole system can be supplied without the need of single or
three-phase high-voltage input
• An inverting buck-boost generates ±14 V for the dual-LDO during energy storage discharge, taking power
from the regulated 5-V rail

low power, low noise for RCD filters

+12 V
DC+ +14 V Dual LDO
85 VAC to 460 VAC
TPS7A39
–12 V
EMI filter

L1 SGND
L2 high power for motor drive, relay drive
L3 –14 V
Quasi-resonant 30-W +12 VP –14 V
N SPR Flyback Inverting
Buck-boost +14 V
UCC28742 TPS65130
Disable

Sync-FET EN
Driver Buck1
+5 V
UCC24612 TPS563210
PGND SGND PG

+3.3 V
Opto coupler Buck2 LDO2
+1.8 V
TPS563210 TPS7A2018
EN PG

12-V Bench eFuse

supply input TPS259470

Linear SuperCap
VCC Charger ATL431
FB
EOC RESET
To SuperCap
microcontroller Watchdog 4.3 V to 7.8 V
RESET Boost
TL7705A
TPS55330
+ SuperCap
Charging – 2.5 F Set point: 11.5
+ SuperCap
– 2.5 F

SGND SGND

Figure 2-2. Isolated AC/DC Power Supply Block Diagram

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Table 2-1. Design Parameters

PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT
INPUT CHARACTERISTICS
Input voltage,VIN 85 115, 230 460 VRMS
Maximum input current VIN = VIN(min), IOUT = IOUT(max) 0.8 ARMS
Line frequency 47 60, 50 63 Hz
Desired capacitor bulk voltage, 85 V
VBULK(desired)
No load input power VIN(min) ≤ VIN≤ VIN(max), IOUT = 0 A 500 mW
consumption
OUTPUT CHARACTERISTICS
Output voltage, VOUT1 VIN(min) ≤ VIN≤ VIN(max) 11.4 12 12.6 V
Output current, IOUT1 2.2 A
Output voltage, VOUT2 VIN(min) ≤ VIN≤ VIN(max) 10.5 12 12.1 V
Output current, IOUT2 0.1 A
Output voltage, VOUT3 VIN(min) ≤ VIN≤ VIN(max) –10.5 –12 –12.1 V
Output current, IOUT3 0.1 A
Total output power, POUT 28.8 W
Output voltage regulation Line regulation: VIN(min) ≤ VIN ≤ VIN(max), 0.1%
IOUT1 ≤ IOUT1(max)
Load regulation: 0 A ≤ IOUT1 ≤ IOUT1(max) 0.2%
Output voltage ripple VIN(min) ≤ VIN≤ VIN(max), 100 mVpp
0 A ≤ IOUT1≤ IOUT1(max)
Total output overcurrent, IOCC VIN(min) ≤ VIN≤ VIN(max) 2.4 A
Minimum output voltage, CC VIN(min) ≤ VIN≤ VIN(max), IOUT = IOCC 5 V
mode
Brown-out protection IOUT = IOUT(max) 49.9 55.9 61.8 VRMS
Transient response overshoot IOUT = IOUT(max) to 0-A load transient 0.2 V
Transient response time IOUT = IOUT(max) to 0-A load transient 5 ms
SYSTEMS CHARACTERISTICS
Switching frequency, fSW 1.2 40 kHz
Average efficiency 25%, 50%, 75%, 100% load average at 84.8 85.5 86.2 %
nominal input voltages
Operating temperature 25 °C

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2.2.1.1 Input Bulk Capacitance and Minimum Bulk Voltage

The minimum voltage on the input bulk capacitance is needed to determine the maximum primary-to-secondary
turns-ratio of the transformer. The input power of the converter based on target full-load efficiency, the minimum
input RMS voltage, and the minimum AC input frequency determine the input capacitance requirement.
Maximum input power is determined based on Equation 1:

V ×I 12 V × 2.2 A + −14 V × 0.1 A + +14 V × 0.1 A

PIN = OCV η OCC = 0.8 ≈ 36.5 W (1)

where
• VOCV is the regulated output voltage of the converter
• IOCC is the converter total output CC target
• η is the converter overall efficiency at full-power output
Equation 2 provides an accurate solution for the total input capacitance based on a target minimum bulk
capacitor voltage. Alternatively, to target a given input capacitance value, iterate the minimum capacitor voltage
to achieve the target capacitance value.

1 × arcsin VBULK desired

2PIN × 0.25 + 2π
2 × VIN min
CBULK = ≈ 58.9 μF (2)
2VIN min − VBULK desired 2 × fLINE min
2

CBULK selected = 68 μF (3)

Four 68-µF electrolytic capacitors were used at the input to create an equivalent 68-µF bulk capacitor to support
a maximum input voltage of 460 VRMS. This selection changes the minimum VBULK voltage to 90.7 V (also called
VBULK_VALLEY) per the UCC28742 design calculator.
2.2.1.2 Transformer Turns-Ratio, Primary Inductance, and Primary Peak Current
The target maximum switching frequency at full load, the minimum input-capacitor bulk voltage, and the
estimated DCM resonant time determine the maximum primary-to-secondary turns-ratio of the transformer.
Initially, determine the maximum-available total duty-cycle of the on-time and secondary conduction time based
on the target switching frequency (fMAX) and DCM resonant time (tR).
At the transition-mode operation limit of DCM, the interval required from the end of the secondary current
conduction to the first valley of the VDS voltage is ½ of the DCM resonant period (tR), or 1 µs assuming 500-kHz
DCM resonant frequency. The maximum allowable MOSFET on-time DMAX is determined using Equation 4:

tR 2 µs
DMAX = 1 − DMAGCC − 2 × fMAX = 1 − 0.475 − 38 kHz × 2 = 0.485 (4)

where
• tR is the estimated period of the LC resonant frequency at the switch node
• DMAGCC is defined as the duty cycle of the secondary-diode conduction during CC operation and is fixed
internally by the UCC28742 device at 0.475
When DMAX is known, the maximum primary-to-secondary turns ratio is determined with Equation 5. The total
voltage on the secondary winding must be determined, which is the sum of VOCV and VF.

D ×V
NPS max = MAX BULK_VALLEY
(5)
DMAGCC × VOCV + VF

Assuming VF = 0.8 V:

0.485 × 90.7 V
NPS max =   = 7.24 (6)
0.475 × 12 V + 0.8 V

NPS selected =  7 (7)

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A higher turns-ratio generally improves efficiency, but can limit operation at a low input voltage. Transformer
design iterations are generally necessary to evaluate system-level performance trade-offs.
The primary transformer inductance is calculated using the standard energy storage equation for flyback
transformers. The primary current, maximum switching frequency, output voltage and current targets, and
transformer power losses are included in Equation 8:

2 × VOCV + VF × IOCC
LP = =  627.7 μH (8)
ŋXFMR × I2PP max × fMAX

LP selected = 700 μH (9)

The UCC28742 CC regulation is achieved by maintaining DMAGCC at the maximum primary peak current setting.
The product of DMAGCC and VCST(max) defines a CC-regulating voltage factor VCCR which is used with NPS to
determine the current-sense resistor value necessary to achieve the regulated CC target, IOCC (see Equation
10).

V × NPS
RCS =   CCR
2 × IOCC × ŋXFMR (10)

RCS =   0.363 V×7

2 × 2.2 A × 0.9 = 0.547 Ω (11)

RCS selected =  0.5 Ω (12)

where
• VCCR is the CC regulation factor (from the UCC28742 High-Efficiency Flyback Controller with Optocoupler
Feedback data sheet)
• VCST is the CS-pin current-sense threshold (from the data sheet)

VCST max
IPP max = RCS = 0.83 V
0.5 Ω = 1.66 A (13)

VCST nom
IPP nom = RCS = 0.77 V
0.5 Ω = 1.54A (14)

NAS is determined by the lowest target operating output voltage while in CC regulation and by the VDD UVLO
turnoff threshold of the UCC28742 device. Additional energy is supplied to VDD from the transformer leakage-
inductance which allows a lower turns ratio to be used in many designs.

VDD off + VFA

NAS = VOCC + VF = 8.15 V + 0.8 V
5 V + 0.8 V = 1.54 (15)

where
• VDD(off) is UCC28742 turnoff threshold (from the data sheet)
• VOCC is the lowest output voltage target of the converter while in constant-current regulation
• VFA is voltage drop across rectifier diode on auxiliary side of flyback stage

NAS selected =  1.455 (16)

This implies:

NPA selected = 4.81 (17)

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Since the ±14-V rails are unregulated, the turn ratio determines their output voltage:

NPS 7
NPT = = = 6.05  (18)
VOV14 + VF / VOCV + VF 14 V + 0.8 V / 12 V + 0.8 V  

NPT selected = 5.92 (19)

2.2.1.3 Transformer Parameter Calculations: Primary and Secondary RMS Currents

With the primary inductance of 700 µH, the absolute maximum switching frequency is calculated from:

2 × 12 V + 0.8 V × 2.2 A
fMAX = 2 = 37.7 kHz (20)
0.9 × 1.54 A × 700 µH

The maximum switching period is:

tSW =   f 1 =   37.71kHz = 26.5 µs  (21)

MAX

The actual maximum on-time is given by:

IPP nom × LP 1.54 A × 700 µH

tON max =   V =  90.7 V = 11.88 µs (22)
BULK_VALLEY

The maximum duty cycle of operation (DMAX) is:

tON max 11.88 µs

DMAX =   tSW = 26.5 µs = 0.448 (23)

The transformer primary RMS current (IPRMS) is:

DMAX 0.448
IPRMS =  IPP max 3 = 1.66 A × 3 = 0.641 A  (24)

The transformer secondary peak current RMS current (ISEC(max)) is:

ISEC max =  IPP max × NPS = 1.66 A × 7 = 11.62 A  (25)

The transformer secondary RMS current (ISEC_RMS) is:

DMAX 0.448
ISEC_RMS =  ISEC max 3 = 11.62 A × 3 = 4.49 A (26)

Based on these calculations, a Würth Elektronik™ transformer was designed for this application (part number
750320029), which has the following specifications:
• NPS = 7 ±2% (primary to secondary turns-ratio)
• NPT = 5.92 ±2% (primary to tertiary turns-ratio)
• NPA = 4.81 ±2% (primary to auxiliary turns-ratio)
• LP = 700 ±10% μH (primary inductance)
• LLK = 10 μH (primary leakage inductance)
2.2.1.4 Main Switching Power MOSFET Selection
The drain-to-source RMS current, IDS_RMS, through switching FET is calculated using:

IDS_RMS =  IPRMS = 0.641 A (27)

Select a MOSFET with five times the IDS_RMS calculated. The maximum voltage across the FET can be
estimated using:

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VDSPK =   VIN max × 2 + VOCV + VF × NPS + VLK = 460 V × 2 + 12 V + 0.8 V × 7 + 63 V = 803.1 V (28)

Considering a de-rating of 15% and leakage spike of around 150 V, the voltage rating of the MOSFET must be
around 925-V DC. A 950-V MOSFET is selected.
2.2.1.5 Rectifying Diode Selection
Calculate the secondary output diode or synchronous rectifier FET reverse voltage or blocking voltage needed
(VDIODE_BLOCKING):

VIN_DC max 460 V × 2 

VDIODE_BLOCKING =   NPS + VOCV = 7 + 12 V = 104.9 V (29)

For this reference design, a 200-V, 24-A rated synchronous rectifier FET is selected for the +12-Vp rail to reduce
losses. For the ±14 rails, Schottky diodes with 200-V voltage and 1-A forward current ratings are selected.

VIN_DC max 460 V × 2 

VDIODE_BLOCKING_AUX =   NPA + VOCV + VF × NAS − VFA = 4.81 + 12 V + 0.8 V × 1.455 − 0.6 V =  153 V(30)

For the auxiliary rail, a Schottky diode with 400-V voltage and 1-A forward current ratings is selected. Here
normally a 200-V diode is sufficient, but spikes over 153 V must be considered. If a 300-V diode, is selected,
the diode does not bring any advantage because 300-V and 400-V small diodes have no difference in terms of
reverse recovery time, nor VF.
2.2.1.6 Output Capacitor Selection
For this reference design, the output capacitor (COUT) for output is selected to prevent VOUT (12 V) from dropping
below the minimum output voltage (VOTRM) during transients up to 0.1 V and ripple voltage less than 100 mV.

IOCC
2 × t
COUT ≥   V (31)
OCV − VOTRM

Assuming VOTRM = 11.9 V,

2.2 A
2 × 50 µs
COUT ≥   12 V − 11.9 V ≥ 550 µF (32)

COUT selected = 2  ×  680 µF (33)

Considering the allowable output ripple voltage of 100 mV (5%), the ESR and RMS current of the capacitor must
be:

V
ESR = OUT_RIPPLE
ISEC max = 200 mV
11.62 A = 17.2 mΩ (34)

2 2 2 2
ICOUT_RMS =   ISEC_RMS − IOCC =  4.49 A − 2.2 A = 5.0 A (35)

2.2.1.7 Capacitance on VDD Pin

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in CC regulation. The capacitance on VDD must supply the primary-side
operating current used during start-up and between low-frequency switching pulses. The largest result of two
independent calculations denoted in Equation 36 determines the value of CVDD.
At start-up, when VVDD(on) is reached, CVDD alone supplies the device operating current and MOSFET gate
current until the output of the converter reaches the target minimum operating voltage in CC regulation, VOCC.
Now the auxiliary winding sustains VDD for the UCC28742 device above UVLO. The total output current
available to the load and to charge the output capacitors is the CC-regulation target, IOCC. Equation 36 assumes
that all of the output current of the converter is available to charge the output capacitance until VOCC is achieved.

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For typical applications, Equation 37 includes an estimated qG × fSW(max) of average gate drive current and a 1-V
margin added to VVDD.

C × VOCC
IRUN + qGfSW max × OUT IOCC
CVDD ≥   (36)
VDD on − VDD off + 1 V

1360 µF × 12 V
2 mA + 10 nC × 37.7 kHz × 2.2 V
CVDD ≥   ≥ 0.128 µF (37)
21 V − 8.5 V + 1 V

The current design uses 10-µF and 0.1-µF capacitors.

2.2.1.8 Open-loop Voltage Regulation Versus Pin Resistor Divider, Line Compensation Resistor
The resistor divider at the VS pin determines the output voltage regulation point of the flyback converter. Also,
the high-side divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV
operation. RS1 is initially determined based on transformer auxiliary-to-primary turns ratio and desired input
voltage operating threshold.

VIN run × 2
RS1 = N × I (38)
PA VSL min

where
• NPA is the transformer primary-to-auxiliary turns ratio
• VIN(run) is the ACRMS voltage to enable turn-on of the controller (run); in case of DC input, leave out the √ 2
term in the equation
• VSL(run) is the run threshold for the current pulled out of the VS pin during the switch on-time (see the
Electrical Characteristics section of the UCC28742 data sheet)

80 V × 2
RS1 = 4.81 × 210 µA = 112 kΩ (39)

RS1 selected = 121 kΩ (40)

The low-side VS pin resistor is selected based on the desired VOUT regulation voltage in open-loop conditions
and sets the maximum allowable voltage during open-loop conditions.

RS1 × VOVPTH
RS2 =     (41)
NAS × VOV + VF − VOVPTH

where
• VOV is the maximum allowable peak voltage at the converter output
• VF is the output-rectifier forward drop at near-zero current
• NAS is the transformer auxiliary-to-secondary turns ratio
• VOVPTH is the overvoltage detection threshold at the VS input (see the Electrical Characteristics section of the
UCC28742 data sheet)

121 kΩ × 4.65 V
RS2 =   = 30.7 kΩ (42)
1.455 × 15 V + 0.8 V − 4.65 V

RS2 selected =  33.2 kΩ (43)

The UCC28742 device maintains tight CC regulation over varying input lines by using the line-compensation
feature. The line-compensation resistor (RLC) value is determined by the current flowing in RS1 and the total
internal gate drive and external MOSFET turn-off delay. Assuming an internal delay of 50 ns in the UCC28742
device:

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K × RS1 × RCS × tD × NPA

RLC =   LC L (44)
P

where
• tD is the current-sense delay including MOSFET turn-off delay
• KLC is a current-scaling constant (see the Electrical Characteristics section of the UCC28742 data sheet)

25 × 121 kΩ × 0.5 Ω × 46 ns + 50 ns × 4.81

RLC =   700 µH = 998 Ω (45)

RLC selected =  1 kΩ (46)

2.2.1.9 Feedback Elements

The output voltage is set through the sense network resistors RFB1 and RFB2. Select the value of the feedback
resistor based on the desired output voltage with:

V ×R
Vtℎ =   ROCV + RFB2 (47)
FB1 FB2

where
• Vth = 2.5 V
The op amp compensation network, ZFB, is determined using well-established design techniques for control-loop
stability. Typically, a type-II compensation network is used. See the UCC28742 data sheet and the design
calculator for details.
2.2.1.10 Backup Power Supply
There are three possible power scenarios:
1. Single or three-phase power available:
a. The converter supplies all voltages and charges the supercapacitors in a variable time between 1 minute
and 21 seconds as first charge, and 36 seconds as successive recharges.
b. The switching waveform present on the secondary side winding is peak-rectified and is used to disable
the inverting buck-boost.
c. At the same time, as the voltage on the supercapacitors is in the range 4.3 V–7.8 V, the boost converter
is active and delivers 11.5 V. This voltage level, slightly lower than 12 V, is on purpose to avoid delivering
current when mains is present. Keeping the boost converter active eliminates the delay due to the device
soft start.
d. When the supercapacitors are charged, a voltage supervisor TL7705A is enabling the flag “EOC” (end of
charge, useful for a digital output to uC) and turning an LED on.
2. Power unavailable:
a. Since the boost converter with TPS55330 is always active, the 12-Vp bus droops from 12 V to 11.5 V,
keeping all rails alive.
b. At the same time, both ± 14-V outputs from the flyback converter go to zero and the peak rectified
voltage used for the signal Disable goes to zero.
c. Then the inverting buck-boost starts and supplies ±14 V, which are connected by ORing diodes to the
input of the dual LDO, supplying ± 12 V.
d. The power is delivered until the supercapacitors are discharged below boost UVLO (4.3 V). At this point
all rails are off.
3. 12-V bench supply on:
a. Here the supercapacitors are not recharged because there is no voltage on auxiliary winding of the
flyback.
b. The 12 V from bench power is supplying all the rails normally. The inverting buck-boost is also supplying
±14 V for dual LDO.

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2.2.1.11 Supercapacitor Selection

The supercapacitors supplies the 12-V and the 5-V rails (AM62 SOM) in case of unexpected AC input shut down
to turn off the main relay and unlock the plug. Assume 1 s duration time as the initial specification.
• 12-V rail: Peak current 1.8 A for 200 ms (unlock plug and relay off)
• 12-V rail: Average current 1.8 A × 0.2 s + 0.1 A × 0.8 s = 0.44 A
• 5-V rail: Average current 0.275 A for 1 s
The total peak power required from supercap, PPK_SC:

PPK_SC = (V12Vp × IPK_1 + V5V × IPK_2 / ηBUCK) / ηBOOST (48)

PPK_SC = (12 V × 1.8 A + 5 V × 0.275 A / 0.9) / 0.85 = 27.2 W (49)

Total 27.2 W peak for 200 ms or a peak current of approximately 3.5 A (that is, 27.2 W / 7.8 V). Total average
power required from supercapacitor, PAVE_SC:

PAVE_SC = (V12Vp × IAVE_1 + V5V × IAVE_2 / ηBUCK) / ηBOOST (50)

PAVE_SC = (12 V × 0.44 A + 5 V × 0.275 A / 0.9) / 0.85 = 8 W (that is, 8 J in 1 s) (51)

Consider that the supercapacitor is charged up to 7.8 V and then discharged down to 4.3 V (that is, UVLO of the
TPS55330 boost converter):

CMIN_SERIES= 2 × (E) / ((V2)2 – (V1)2) = 2 × (8 J) / ((7.8 V)2 – (4.3 V)2) = 0.3778 F. (52)

CMIN = 2 × CMIN_SERIES = 0.76 F (for 1 s) (53)

where
• CMIN_SERIES is the minimum equivalent series capacitor
• CMIN is the minimum individual capacitance
Now, for 3 s we need CMIN = 3 × 0.76 = 2.28 F.
For this design, two 2.5-F in series that support up to 47.5 W and 4 A peak are selected.
Note that the TL7705 voltage supervisor monitors for charge completion at an slightly lower voltage of 7.49 V.
The supercapacitor energy available from 7.49 V to 4.3 V, ESC_7p5:

ESC_7p5 = 0.5 × C × (V1 2 – V2 2) = 0.5 × 1.25 F × (7.492 – 4.32) = 23.5 J (54)

The energy available after accounting for boost efficiency, ESC_7p5_BOOST:

ESC_7p5_BOOST = ESC_7p5 × ηBOOST = 23.5 J × 0.85 = 20 J (55)

The power available during 3 s, PSC_7p5:

PSC_7p5 = ESC_7p5_BOOST / time = 20 J / 3 s = 6.65 W (56)

The supercapacitor energy available from 7.8 V to 4.3 V, ESC_7p8:

ESC_7p8 = 0.5 × C × (V1 2 – V2 2) = 0.5 × 1.25 F × (7.82 – 4.32) = 26.5 J (57)

The energy available after accounting for boost efficiency, ESC_7p8_BOOST:

ESC_7p8_BOOST = ESC_7p8 × ηBOOST = 26.5 J × 0.85 = 22.5 J (58)

The power available during 3 s, PSC_7p8:

PSC_7p8 = ESC_7p8_BOOST / time = 22.5 J / 3 s = 7.5 W (59)

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2.2.1.12 Supercapacitor Charger Design

The shunt voltage reference (U6_P) sets the final charge voltage to 7.8 V. The NPN transistor (Q4_P) and
4.99-Ω resistor (R38_P) limit the charge current to approximately 120 mA (0.6 V / 4.99 Ω). The NMOS FET
(Q3_P) operates in saturation region to maintain the required charge voltage drop. U6_P pulls down the gate of
Q3_P as soon as Vbackup (as shown in the schematic) reaches 7.8 V. This way, Vbackup stays constant at the
nominal 7.8 V. There are two charging scenarios:
1. Charging time as first power supply turn-on: here Vbackup is zero. The ΔV that must be covered is from zero
to 7.8 V; therefore, the charging time is ΔT = C × ΔV / I = 1.25 F × 7.8 V / 120 mA = 81.25 seconds (1 minute
and 21 seconds).
2. Charging time after energy storage release: here Vbackup is the UVLO of the boost converter (4.3 V). The
ΔV that must be covered is from 4.3 V to 7.8 V; the charging time is ΔT = C × ΔV / I = 1.25 F × (7.8 V – 4.3
V) / 120 mA = 36.46 seconds.
In summary, the worst-case charging time is 1 minute and 21 seconds, while recharging between energy storage
releases is 36.46 seconds.
2.2.2 Control Pilot Signal Interface
The control pilot circuit is the primary control means to make sure of proper operation when connecting an EV
or PHEV to the EVSE. The pilot signal is the key method through which a J1772-compliant EVSE communicates
with a vehicle. The pilot signal is based on a 1-kHz, ±12-V PWM signal that is transmitted to a vehicle over the
charging chord. The vehicle can then respond by placing various loads on the line, affecting the voltage, which
the EVSE measures.
2.2.2.1 J1772 Duty Cycle
The duty cycle of the pilot signals communicate the limit of current the EVSE is capable of supplying to the
vehicle; the vehicle can then use up to that amount of current for the charging circuitry. This current rating is
primarily determined by the electromechanical components in the EVSE, such as conductors, relays, contactors,
and the service connection.
The relationship between duty cycle and current is defined by two different equations depending on the current
range specified; for a 6- to 51-A service, is:

Amps
Duty cycle
0.6 (60)

For a higher service in the 51- to 80-A range, is:

Amps
Duty cycle 64
2.5 (61)

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To demonstrate this relationship further, Table 2-2 shows some of the common service ratings.
Table 2-2. Pilot Signal Example Duty Cycle
AMPS DUTY CYCLE
5 8.3%
15 25%
30 50%
40 66.6%
65 90%
80 96%

In this design, the PWM is generated by a timer module on the MSP430™ MCU. The current rating can typically
be set as a permanent value in the firmware because the current rating is so tightly coupled to the external
hardware.
Advanced EVSEs with a human machine interface (HMI) can enable the current to be derated if the service line
is unable to provide enough current with a stable voltage. A significant voltage drop as a result of wire loss is
possible in these high-current applications.
2.2.2.1.1 Control Pilot Signal States
The EVSE connection and negotiation occurs through various states of the PWM signal and load resistances of
the vehicle. Table 2-3 highlights these states.
Table 2-3. Pilot Signal State Parameters
STATE PILOT HIGH VOLTAGE PILOT LOW VOLTAGE FREQUENCY RESISTANCE DESCRIPTION
State A 12 V N/A DC N/A Not connected
State B 9V –12 V 1 kHz 2.74 kΩ EV connected, ready to charge
State C 6V –12 V 1 kHz 882 Ω EV charging
State D 3V –12 V 1 kHz 246 Ω EV charging, ventilation required
State E 0V 0V N/A — Error
State F N/A –12 V N/A — Unknown error

States A, B, and C are the core functionality and define the normal operation. An EVSE typically performs
several self-tests upon initially powering on and then enters State A. When ready, the normal connection process
follows several steps:
1. The EVSE puts 12 V on the pilot wire. This transmission signals the vehicle when the plug is connected.
2. When the plug is connected, the vehicle places a 2.74-kΩ load on the pilot line, which drops the voltage to 9
V.
3. The EVSE moves to State B, where the EVSE enables the PWM, which signals the vehicle how much
current the vehicle can draw. The EVSE also closes the relays, providing power to the vehicle.
4. The vehicle starts to draw power and switches to the 822-Ω load, which drops the voltage to 6 V, signaling
the EVSE that charging has started.
5. Most vehicles continue to pull low amounts of power in state C, even when fully charged, so the charging
process is ended by unplugging the cable, which returns the voltage to 12 V. The EVSE measures this
process and closes the relays and returns to State A.
Additional error handling such as missing diodes in the vehicle or an improper connection can be detected and
handled by the EVSE by cutting the power, as well.

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2.2.2.1.2 Control Pilot Signal Circuit

The pilot signal is required to travel down several meters of cable and through a load resistance. The pilot
signal is also a bipolar ±12-V signal, which requires special consideration. To accommodate these parameters,
an amplifier with a wide input range and reasonable power output is selected. The TLV1805 device has a voltage
rating of ±18 V and a current rating of 475 mA, making the device a good match for the application. In addition,
while most EVSEs do not require an automotive qualification, a Q1-rated variant of the TLV1805-Q1 device
exists, if this feature is desired.
The amplification circuit is a simple rail-to-rail output configuration of the TLV1805 device, with the MCU I/O
driving the positive input. The output of the pilot amplifier is also fed into a simple voltage divider so that the
MCU can measure the voltage during operation and detect the load resistance of the vehicle. Figure 2-3 shows
the full schematic of this subsystem.

Figure 2-3. Control Pilot Signal Generator Circuit

To validate the architecture, the design was tested in the TINA-TI™ software from TI, which is a spice-based
simulation tool.

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2.2.3 Relay Drive and Weld Detect

The primary functionality of the EVSE is the reliable control of large currents directed toward an electric vehicle
at the mains voltage. In a normal use case, the relay or contactor must be held closed for several hours to
fully charge a vehicle; however, the relays cannot be welded because of safety concerns. If something fails in
the control system, the relays must fail open. These high current relays or contactors can typically draw tens to
hundreds of milliamps as an inductive load, requiring specific drive architectures.
Because of the amount of time that a relay or contactor requires to remain powered, an efficient drive device is
preferred to the typical Darlington array, or even discrete transistor configuration. For this reason, the DRV8220
current controller is selected to drive the relays or contactors in the design. The DRV8220 device is designed to
regulate the current with a well-controlled waveform to reduce power dissipation.
Relays and contactors use electromechanical solenoids for their operation. Activation starts when EN pin voltage
is pulled high either by an external driver or internal pullup. Once the EN pin is driven to GND, the DRV8220
device allows the solenoid current to decay to zero. The solenoid current is ramped up fast to enable opening
of the relay or contactor. After initial ramping, the solenoid current is kept at a peak value to maintain correct
operation, after which the current is reduced to a lower hold level to avoid thermal problems and reduce power
dissipation.
ISOLENOID (mA)

IPEAK

IHOLD

t
tKEEP

Enable

Figure 2-4. Typical Current Waveform Through the Solenoid

For safety reasons, detecting the output voltage of the primary relay is critical. The contacts can experience
arcing and become fused together, providing power to the plug even when the contacts are not enabled.
Checking that the operation completed correctly is important and must be done every time the relay is opened.
To implement this check, the ISO1212 fully-integrated, isolated digital-input receiver is used to sense line
voltage.
The outputs (OUT1 and OUT2) from the ISO1212 device are GPIO-level DC signals that are high when voltage
is present and are fed directly into the MCU for fault detection. For this reference design, the high and low
thresholds are set to 125 VRMS and 121 VRMS, respectively. The full circuit is shown in Figure 2-5. To learn
more about AC and DC detection with ISO1212, see ISO121x Threshold Calculator for 9V to 300V DC and AC
Voltage Detection.

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Weldin g Detection
Rela y Driver

Input Configur ation

Rthr Rshunt Rsense

VAC Vin_max R41+R42 R47 R43
J19 R45+R46 R49 R48
1 J20
LINE1_ IN
1
LINE1_OUT 110 148 33k 24k 560
74650073R K1
1 12 74650073R
LINE1 _IN LINE1 _OUT 240 300 60k 15k 560
J21
1 2 11 J22 3V3 R192 R193
LINE2 _IN LINE2 _IN LINE2 _OUT 1 L IN E1_OUT
LINE2_OUT 30k 30k
74650073R 3 10 MDB6S D800

3
LINE3 _IN LINE3 _OUT
74650073R D47
J23 4 9 U33 UFM15PL-TP

~
N_IN N_ OUT
1 J24
LINE3 _IN DNP
7 1 2 VCC1 SEN SE1 16 1
+ -
2
74650073R 6 R_MIR ROR_OUT LINE3_OUT
MIRR OR _IN R194
74650073R 4
OU T1 IN1
15 R 800

~
R ELAY_CH ECK_L 1 C156 R197 R195 R196
J25 5 8 560
1 R ELAY_OH J26 3 13 1nF 15k DNP LINE2_O
AHER4191 EN SU B1 30k 30k

4
N_IN 100 V
1

3
N_ OUT N_IN D801
74650073R P GND FGND1
14
74650073R C157 6 D48 UF M15PL-TP

~
NC
16V 7
NC
MDB6S DNP
0.1uF 11 1 2
SEN SE2 + -
5 10 R198
OU T2 IN2 R 801

~
R ELAY_CHECK_L 2 C158 R199
560
SU B2 12 1nF 15k DNP

4
1 100V
GND1 N_ IN
8 GND1 FGND2 9
12V
AHER4191: coil voltage12V, oper ating curr ent 333mA(36ohm), holding voltage 35 % - 50%
ISO1212DBQR
F5 PGND C 159
DNP R200 R201
L IN E3_OUT
30k 30k
044001.5WR 3V3 470pF

3
C160 C161 C162 D49 D802
25V 25V 25V U34 MDB6S UFM15PL-T P

~
leave OUT1 floating!
22µF 22µF 0.1uF DNP
U 35 2 16 1 2
VCC1 SEN SE1 + -
PGND
5 6 4 15
R202
TP27 R 802

~
VM OU T1 R ELAY_CH ECK_L 3 OU T1 IN1 C163 R205 R203 R204
R206 560 LINE1 _IN
1 4 3 13 1nF 15k DNP 30k 30k

4
I N1 O UT2 REL AY_ OH EN SU B1
0 100 V

3
N_IN D803
2 3 FGND1 14 D50
IN 2 GN D C164 UF M15PL-TP
P GND 6 MDB6S

~
NC
DRV8220DRL 16V 7 NC
DNP
0.1uF 11 1 2
SEN SE2 + -
3V3 P GND 5 10
R207
R 803

~
RELAY_STATE R ELAY_CHECK_ N OU T2 IN2 C165 R208
560
3V3 12 1nF 15k DNP

4
SU B2
1 100V
R209 GN D1 N_ OU T
8 GN D1 FGND2 9
R210 0
10k U36A R211 ISO1212DBQR
1 620
R CD_ FAULT
4 PGND C 166
AM62_ R_EN ABLE 2 DNP
SN74AUP1G08 DBVT
2

470pF
D51
3V3 Green 3V3 3V3 3V3 3V3
U36B
1

5 VC C GND 3

C167 SN74 AUP1G08DBVT R212 R213 R214 R215

3

25V P GND 620 620 620 620

0.1uF R216 1 Q10
R ELAY_STATE BC848CLT1G
20.0k
2

2
P GND D52 D53 D54 D55
Green Green Green Green
1

1
R217 P GND
3V3 MIR ROR_IN
620
TP28
3

3
R218 R219 1 Q11 R220 1 Q12 R221 1 Q13 R222 1 Q14
R_MIRR OR _OUT REL AY_ CHEC K_L1 BC848CLT1G RELAY_C HECK_ L2 BC848CLT1G RELAY_C HECK_ L3 BC848CLT1G R ELAY_CH ECK_N BC848CLT 1G
10k 20.0k 20.0k 20.0k 20.0k
2

2
P GND
MIRRO_OUT goes to MCU GPIO

P GND P GND P GND P GND

Figure 2-5. AC Weld Detect Circuit

2.2.4 Residual Current Detection

This reference design implements a discrete version of residual current detection (RCD) capable of detecting
two types of ground faults, AC current of 30 mARMS and DC current of 6 mA. This detection is enabled utilizing
an auto-oscillation circuit along with a receiver filter circuit. For the auto-oscillation circuit, the DRV8220 H-bridge
is used to drive the magnetic core in and out of saturation. In addition, a feedback circuit is used to determine
when the core reaches saturation and switches the drive coil current in the opposite direction. This enables the
design to detect small amounts of DC current with a single toroidal magnetic core. The receive filter stage is
used to filter the auto-oscillation driving frequency and signal condition the fault current signal. This filtered signal
is captured by the internal ADC of the MSP430 with a sampling rate of 25,000 samples per second. The signal
highest and lowest values are stored over 10 ms to determine if the fault type is AC or DC. The AC and DC
trip thresholds can be adjusted via software to support different regional specifications. If the stored values are
above trip thresholds, the MCU outputs a GPIO high, which is intended to interface with a relay driver to trip
the relay. The GPIO returns low when the fault current lowers below an adjustable hysteresis. A summary of the
sub-circuits follows for the AC and DC leakage current detection circuit.

Note
The following RCD description references component designators from the TIDA-010237 schematic.
For a more detailed RCD description see the TIDA-010237 user's guide.

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2.2.4.1 Auto-Oscillation Circuit

The auto-oscillation sub-circuit detects when the fluxgate sensor reaches saturation, then reverses the current direction. When saturation is reached,
current sense voltage exceeds the comparator threshold, which causes the DFF to flip control signals to the DRV8220 H-bridge. This drives the fluxgate
sensor core to saturation in the opposite direction.
3V3

2
C1 C2 C3 C4
16V 100nF 16V 100nF 16V 100nF 16V 100nF

1
3V3
3V3

2
R1 R2
56k 100k

12V U1

1
VREF_500mV VREF_Input_Midsupply
12V_In 5 6
R3
VM OUT1

2
FluxGate+
R4 0 ohm R5 R6
C5 FF_Q+ 1 4
C6 IN1 OUT2 FluxGate- 10k 100k
25V 0 ohm
22µF 25V FF_Q- 2 3
IN2 GND R7
0.1uF VSENSE 2 1

1
DRV8220DRLR

3V3 U2
3V3 8 5 R30 FF_Q+
VCC Q DC_SENSING
3V3 0 ohm R31
7
PRE Q
3 FF_Q-
R8 0 ohm
5
U3 VREF_500mV U4 FF_Q- 1 2 2 D
5

GND INA293A1IDBVR 4 TLV7011DCKR

4 V+ 1
1k 1
R9 CLK
1 1 2 3 V-
VSENSE 3 6
CLR GND
4
499k
2

3V3 SN74LVC2G74DCUR
2

R10
1 2

5
VREF_Input_Midsupply U5
1M 4 TLV7011DCKR
V+ 1
3 V-
3V3 R11
1 2 1

2
100k C10
16V 100nF
2

GND

Figure 2-6. Auto-Oscillation Circuit Schematic

This circuit monitors the current flowing through the fluxgate and reverses drive current direction once saturation is reached. The auto-oscillation circuit is
needed to detect DC faults.
The phase lines and neutral wires go through a fluxgate sensor. During normal operation without a fault condition, the sum of currents equals zero.
During a ground fault condition, the sum of currents is not equal to zero. During a DC fault, there is an imbalance of current flowing through the line and
current returning through the neutral wire. The fluxgate does not detect steady DC current. An oscillating drive current is pushed through the fluxgate
sensor coil. This DC fault current produces a magnetic field which opposes fluxgate drive in one direction, and assists fluxgate drive in the opposite
direction; resulting in a duty cycle shift. Under normal conditions, the duty cycle of the switching is 50%. During a DC fault, the duty cycle shifts.

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The oscillation frequency depends on the signal chain between R7 to pin 1 of the DFF. Match the current sense
amplifier gain and VREF voltage to make sure the core is driven to saturation. Driving the core deeper into
saturation reduces noise, removing the need for degaussing. When the core is fully saturated, all material within
the core is magnetically aligned. When all material is aligned, there are no stray fields within the material to
contribute noise.
2.2.4.2 DRV8220 H-Bridge
The DRV8220 is an integrated motor driver with four N-channel power FETs, charge pump regulator, and
protection circuitry. The device can supply up to 1.76 A of output current, operating on a supply voltage from
4.5 V to 18 V. The driver offers robust internal protection including undervoltage lockout, output overcurrent,
and device overtemperature. The DRV8220 drives current through the magnetic core to saturate the core. This
device is the smallest, most cost-effective device capable of driving enough current. The output of the DRV8220
is controlled by pins 1 and 2. The state of these pins determines which direction current flows through the
magnetic coil. When the saturation detection circuit threshold is passed, the control signals to pins 1 and 2 flip,
which flips the DRV8220 output. The low-side current sense resistor (R7) detects current through the DRV8220.
The current spikes when the core reaches saturation, which is read by the saturation detection circuit.
12V U1

12V_In 5 6
R3
VM OUT1 FluxGate+
R4 0 ohm
C5 FF_Q+ 1 4
C6 IN1 OUT2 FluxGate-
25V 0 ohm
22µF 25V FF_Q- 2 3
IN2 GND R7
0.1uF VSENSE 2 1
DRV8220DRLR

Figure 2-7. DRV8220 Schematic

2.2.4.3 Saturation Detection Circuit

The saturation detection circuit is made of the low-side current sense resistor (R7), current sense amplifier
INA293, and comparator TLV7011. The comparator outputs high when the fluxgate sensor coil saturation is
reached. The circuit shown in Figure 2-8 is used to determine when the fluxgate sensor has reached saturation.
3V3
3V3
5

U3 VREF_500mV U4
5

GND INA293A1IDBVR 4 TLV7011DCKR

4 R9 V+ 1
1 1 2 3 V-
VSENSE 3
499k
2
2

R10
1 2

1M

Figure 2-8. Saturation Detection Schematic

VSENSE is read from the low-side shunt resistor of the DRV8220. VSENSE gives the current through the fluxgate
sensor coil. This signal is gained up by current sense amplifier INA293, with a fixed gain of 20 V/V. The gained
signal is compared to a reference voltage VREF of 500 mV, which is sourced from a resistor divider. When
the current sense signal passes the VREF voltage, the core has saturated and the DRV8220 must switch the
output directions. The output of comparator TLV7011 feeds into a DFF which is explained more in the H-Bridge
Controlled by DFF section.

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Figure 2-9. Burden Resistor Going Into Saturation

2.2.4.4 H-Bridge Controlled by DFF

The output logic to control DRV8220 reverses output Q with each positive CLK edge. The DFF circuit reverses
output Q with each positive CLK edge. Inverted output Q is connected to input data D, so each positive clock
edge inverts the outputs.
3V3 U2
8 5 R30 FF_Q+
VCC Q DC_SENSING
0 ohm R31
7
PRE Q
3 FF_Q-
R8 0 ohm
FF_Q- 1 2 2 D
1k 1
CLK

6 4
CLR GND
3V3 SN74LVC2G74DCUR
5

VREF_Input_Midsupply U5
4 TLV7011DCKR
V+ 1
3 V-
3V3 R11
1 2
1

100k C10
16V 100nF
2

GND

Figure 2-10. DFF SN74LVC2G74 Circuit

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2.2.4.5 Filter Stage

The three goals of filter stage are to gain the ground fault detection signal, filter the noise created by the auto-oscillation circuit, and correct a DC
bias inherent to the fluxgate core. The filter filters noise in the signal path from the burden resistor to the ADC. Too much noise can trigger false trips.
The major source of noise is switching noise caused by the auto-oscillation circuit generating switching of the DRV8220. The auto-oscillation switching
frequency changes with fluxgate sensor permeability, burden resistance, or adjusting the saturation detection circuit. The Hitachi nanocrystalline cores
used for testing ranged from 600 Hz to 800 Hz with a 1-kΩ burden resistor.
During a fault, the filter stage outputs a detectable signal read by the ADC. A fault trip occurs when the filter stage output signal passes a threshold and
the MCU determines the fault type, as AC and DC faults have separate trip thresholds adjustable within software. In this design with a gain of 20 dB, a
DC fault of 6-mA outputs a 200-mV offset. An AC fault of 30-mARMS outputs a peak of 600 mV. The gain can be increased, make sure the trip threshold is
below the rail of op amps. The filter stage is designed to gain the fault signal by 20 dB and attenuate frequencies above 70 Hz. The filter stage consists of
four subsections: differential to single end, low-pass filter, full-wave rectifier, and a DC offset circuit in place of R23.
-12V +12V

2
C16 C17 C18 C19 C20 C21 C22 C23
16V 100nF 16V 100nF 16V 100nF 16V 100nF 16V 100nF 16V 100nF 16V 100nF 16V 100nF

1
GND
GND

R14 R15
1 2 1 2
1.3k C24 1.18k
R16 R17
1 2 C25 2 1 2 1
1 2
1k 1k
35V 1uF GND GND
35V 1uF -12V -12V

2
GND
+12V +12V
2

GND C26 C27

R18

1
C28 25V 0.1uF 25V 0.1uF

2
1

1
1 2 R19 25V 0.1uF C29 C30
AC_Sense+
1

1 2 25V 0.1uF U8 50V 47pF U9

1.3k D1
5

2
1
TLV172IDBVR TLV172IDBVR

2
4
1

-
5

2
750 4 U10 U11 4 D2 1
C31 R20 R21 -
AC_SENSING

1
R22 35V 2.2uF V+ 1 1 2 1 2 4 1 2 1 3 +
1.0k R23
2

3 V- V+ 1 3 +

5
OPA191IDBVR 118R 147R 3 V-

1
R24 0 ohm R25

5
1 2 OPA191IDBVR C32
1

1
R26 1k
2

1 2 C34 22uF
C33 C35 25V 0.1uF
AC_Sense- 750
2

16V GND

2
1

1.3k 25V 0.1uF CC0201KRX5R8BB104

+12V +12V
2

2
C36

2
C37 -12V 25V 0.1uF GND
GND GND -12V GND
2

1 2

35V 1uF
R27 GND
1 2 GND
1.3k
GND

Figure 2-11. Filter Stage Schematic

The filter topology used is the Multiple FeedBack (MFB) topology and is often preferred due to low sensitivity to component variations. The MFB topology
creates an inverting second-order stage. This inversion can be a concern in the filter application. The MFB filter circuit can be configured as a low-pass
filter, high-pass filter, or band-pass filter based on the component selection. For this application, a fourth-order low-pass filter with a Butterworth response
was used.

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2.2.4.6 Differential to Single-Ended Converter

The differential to single-end conversion is performed by the first part of the signal chain. The first op amp
converts the differential signal across the fluxgate burden resistor to a single-ended signal. This simplifies later
signal conditioning and allows the ADC to read a ground referenced signal. R22 is the burden resistor across the
coils of the fluxgate sensor.
Impedance matching to op amp inputs is important to minimize error. Mismatched impedance adds error to the
fault detection signal. Trace from R22 to U10 can be similar to reduce error. To increase the ground fault signal,
replace R18 and R26 with buffer op amps or resistors an order of magnitude larger. A higher impedance relative
to the burden resistor (R22) gives a higher ground fault signal due to the resistor divider effect.
R14
1 2
1.3k C24
1 2

35V 1uF
GND
+12V

2
R18 C28
1 2 R19 25V 0.1uF
AC_Sense+

1
1 2
1.3k

5
1
750 4 U10
C31
R22 35V 2.2uF V+ 1
1.0k

2
3 V-
R24 OPA191IDBVR
1 2

1
R26

2
1 2 C34
AC_Sense- 750
1.3k 25V 0.1uF

2
C37 -12V
1 2 GND

35V 1uF
R27
1 2
1.3k
GND

Figure 2-12. Differential to Single-Ended Schematic

2.2.4.7 Low-Pass Filter

The low-pass filter is optimized to attenuate auto-oscillation frequencies. The goal is to reduce noise to prevent
false trips. This design has a gain of 20 dB at 0 Hz and a cutoff frequency of 70 Hz. The auto-oscillation
frequency depends on many variables: magnetic core material, burden resistance, and the auto-oscillation signal
chain. This design with a nanocrystalline core material results an oscillation around 800 Hz. The low-pass filter is
optimized to attenuate noise created by the auto-oscillation circuit.
R15
1 2
1.18k
C25
1 2

35V 1uF
+12V
GND
2

C29
25V 0.1uF
1
5

U11
R20 R21
1 2 1 2 4
V+ 1
118R 147R 3 V-
OPA191IDBVR
2

22uF
C33
2

16V GND
1
1

C36
25V 0.1uF
GND -12V
2

GND

Figure 2-13. Low-Pass Filter Schematic

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2.2.4.8 Full-Wave Rectifier

The full-wave rectifier only flips negative voltage to positive. The full-wave rectifier allows the same trip threshold
for negative and positive fault current. The other reason for using the full-wave rectifier is to convert the negative
polarity of the signal to positive voltage within the input range of the ADC of the MCU and prevent Electrical
Overstress (EOS).
R16 R17
2 1 2 1
1k 1k
GND GND
-12V -12V

2
C26 C27

1
25V 0.1uF 25V 0.1uF

2
1

1
C30
U8 50V 47pF U9
D1

2
TLV172IDBVR TLV172IDBVR

2
4 -
2

4 - D2 1
AC_SENSING

1
1 2 1 3 +
3 +

1
R25
5

C32
1

1k
C35 25V 0.1uF

2
CC0201KRX5R8BB104
+12V +12V
2

2
GND
GND

GND

Figure 2-14. Full-Wave Rectifier Schematic

This precision full-wave rectifier can turn alternating current (AC) signals to single polarity signals. The op amps,
U8 and U9, buffer the input signal and compensate for the voltage drops across D1 and D2 allowing for small
signal inputs. The circuit is used in this application to quantify the absolute value of input signals which have both
positive and negative polarities.
This topology was chosen over other full-wave rectifier topologies for the simplicity while achieving the desired
performance. U1A and U1B control the biasing of D1 and D2 to change the signal path based on the polarity of
the input signal achieving the full-wave rectification. The input impedance of the circuit is set by the termination
resistor R4 and can be set to match the source impedance or as high as the input impedance of the U1A
amplifier.
R1 R2
1 k
1 k

C7 D1
1N4148 U1B
U1A 47 pF –
– VOUT
+
+ R3
D2
1N4148 1k
VIN R4
49.9 

Figure 2-15. Circuit Schematic

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Figure 2-16 and Equation 62 show the circuit schematic and transfer function for positive input signals. Positive
input signals reverse-bias D1 and forward-bias D2 making the components act like an open circuit and short
circuit, respectively. In this configuration, the U1A amplifier drives the non-inverting input of U1B such that the
voltage at the inverting input of U1A is equal to VIN. Because current does not flow into the high-impedance
inverting input of U1A, there is no current through R1 or R2 and U1B acts as a buffer. U1A must therefore also
act as a buffer and VOUT is simply equal to VIN.
R1 R2
1 k
1 k

C7 D1
1N4148 U1B
U1A 47 pF –
– VOUT
+
+ R3
D2
1N4148 1k
VIN R4
49.9 

Figure 2-16. Simplified Circuit for Positive Input Signals

VOUT = VIN (62)

Figure 2-17 and Equation 63 show the circuit and transfer function for negative inputs. Negative input signals
forward bias D1 and reverse bias D2. Therefore, U1A drives U1B like a standard inverting amplifier while R3
biases the non-inverting node of U1B to GND. In this configuration, the output is now positive for negative input
signals achieving the full-wave rectification.
R1 R2
1 k
1 k

C7 D1
1N4148 U1B
U1A 47 pF –
– VOUT
+
+ R3
D2
1N4148 1k
VIN R4
49.9 

Figure 2-17. Simplified Circuit for Negative Input Signals

VOUT R2
VIN = − R1 (63)

VOUT V
VIN = − 1 V (64)

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2.2.4.9 MCU Selection

For this design, the MSP430F5131 MCU is chosen for the high clock speed required for timer capture DC fault
detection. The timer capture method directly measured duty cycle changes by triggering a timer on each duty
cycle edge, so a high clock speed was required. This timer capture method is used in many existing RCD
modules. Alternatively, a lower BOM cost is possible by reading DC fault with an ADC instead of using the timer
capture method.
The most important specification of MCU selection is the integrated ADC. The ADC must have an effective
resolution small enough to consistently differentiate between a fault. This design sees a 200-mV filter output
during a 6-mA DC fault, and 600-mV maximum filter output during an 30-mARMS AC fault1. This design uses a
10-bit ADC with a full scale range of 1.5 V integrated in the MSP430F5131 MCU.
The ADC needs a sample speed faster than 2000 samples per second. The software stores the low value read
by the ADC and uses the low value to determine if an AC or DC fault occurred. The ADC must sample quickly
enough to consistently detect a low value during an AC waveform to differentiate AC versus DC fault.
The largest source of noise is the ADC reference voltage error. This design has a total reference voltage error of
1.5%. The fault detection signal needs to be amplified as much as possible to make this error less significant.

1 These fault threshold values can be increased by increasing the gain of the filter stage.

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2.3 Highlighted Products

2.3.1 UCC28742
The UCC28742 is a flyback power-supply controller which provides high-performance voltage regulation using
an optically coupled feedback signal from a secondary-side voltage regulator. The device provides accurate
constant-current regulation using primary-side feedback. The controller operates in discontinuous-conduction
mode (DCM) with valley-switching to minimize switching losses and allow for the use of low cost output rectifiers.
The control law scheme combines frequency with primary peak-current amplitude modulation to provide high
conversion efficiency across the load range. The control law provides a wide dynamic operating range of output
power which allows the power-supply designer to achieve low standby power dissipation. During low-power
operating conditions, the power-management features of the controller reduce the device operating current
at switching frequencies below 25 kHz. At and above this frequency, the UCC28742 includes features in the
modulator to reduce the EMI peak energy of the fundamental switching frequency and harmonics. A complete
low-cost and low component-count system is realized using a straight-forward design process.
2.3.2 TLV1805
The TLV1805 comparator features rail-to-rail inputs with a push-pull output stage that operates at supply
voltages as high as 40 V or ±20 V. The rail-to-rail input stage enables detection of signals close to the supply
and ground while the push-pull output stage creates fast transition edges to either supply rail. A low supply
current of 135 μA per channel with small, space-saving packages, makes these comparators versatile for use in
a wide range of applications, from portable to industrial.
2.3.3 DRV8220
DRV8220 is an integrated H-bridge driver with multiple control interface options: PWM (IN1, IN2) interface (DRL
and DSG packages), PH/EN (DSG only), or half-bridge interface (DSG only). To reduce area and external
components on a printed circuit board, the device integrates a charge pump regulator and its capacitors. Both
DSG and DRL packages support a timed auto-sleep mode which reduces microcontroller GPIO connections by
eliminating a disable/sleep pin and automatically putting the device into a low-power sleep mode when the inputs
remain inactive for 1-2 ms. When using autosleep for PWM or PH/EN mode, the nSLEEP pin can be tied high.
The nSLEEP pin allows the device to be put to sleep in half-bridge mode where autosleep is not available.
2.3.4 ISO1212
The ISO1211 and ISO1212 devices are fully-integrated, isolated digital-input receivers with IEC 61131-2 Type
1, 2, and 3 characteristics. The devices receive 24-V to 60-V digital-input signals and provide isolated digital
outputs. No field-side power supply is required. An external resistor, RSENSE, on the input-signal path precisely
sets the limit for the current drawn from the field input based on an internal feedback loop. The voltage transition
thresholds are compliant with Type 1, 2, and 3 and can be increased further using an external resistor, RTHR.
The ISO121x devices use an ON-OFF keying (OOK) modulation scheme to transmit the digital data across
a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage.
2.3.5 ADC122S051
The ADC122S051 and ADC122S051Q devices are low-power, two-channel CMOS 12-bit analog-to-digital
converters with high-speed serial interface. Unlike the conventional practice of specifying performance at a
single sample rate only, the ADC122S051 and ADC122S051Q is fully specified over a sample rate range of 200
ksps to 500 ksps. The converter is based on a successive-approximation register architecture with an internal
track-and-hold circuit. It can be configured to accept one or two input at inputs IN1 and IN2.
2.3.6 TPS7A39
The TPS7A39 device is a dual, monolithic, high PSRR, positive and negative low-dropout (LDO) voltage
regulator capable of sourcing (and sinking) up to 150 mA of current. The regulated outputs can be independently
and externally adjusted to symmetrical or asymmetrical voltages, making this device an ideal dual, bipolar power
supply for signal conditioning. Both positive and negative outputs of the TPS7A39 ratiometrically track each
other during start-up to mitigate floating conditions and other power-supply sequencing issues common in dual-
rail systems. The negative output can regulate up to 0 V, extending the common-mode range for single-supply

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amplifiers. The TPS7A39 also features high PSRR to eliminate power-supply noise, such as switching noise,
that can compromise signal integrity.
2.3.7 TPS7A20
The TPS7A20 is an ultra-small, low-dropout (LDO) linear regulator that can source 300 mA of output current.
The TPS7A20 is designed to provide low noise, high PSRR, and excellent load and line transient performance
that can meet the requirements of RF and other sensitive analog circuits. Using remarkable design techniques,
the TPS7A20 offers an ultra-low noise performance without the addition of a noise bypass capacitor. The
TPS7A20 also provides the advantage of low quiescent current, which can be good for battery-powered
applications. With an input voltage range of 1.6 V to 6.0 V and an output range of 0.8 V to 5.5 V, the TPS7A20
can be used for a wide variety of applications. The device uses a precision reference circuit to provide a
maximum accuracy of 1.5% over load, line, and temperature variations.
2.3.8 ATL431
The ATL431 and ATL432 are three-terminal adjustable shunt regulators, with specified thermal stability over
applicable automotive, commercial, and industrial temperature ranges. The output voltage can be set to any
value between Vref (approximately 2.5 V) and 36 V, with two external resistors. These devices have a typical
output impedance of 0.05 Ω. Active output circuitry provides a very sharp turn-on characteristic, making these
devices excellent replacements for Zener diodes in many applications, such as onboard regulation, adjustable
power supplies, and switching power supplies.
2.3.9 TL431
The TL431 and TL432 devices are three-terminal adjustable shunt regulators, with specified thermal stability
over applicable automotive, commercial, and military temperature ranges. The output voltage can be set to
any value between Vref (approximately 2.5 V) and 36 V, with two external resistors. These devices have a
typical output impedance of 0.2 Ω. Active output circuitry provides a very sharp turn-on characteristic, making
these devices excellent replacements for Zener diodes in many applications, such as onboard regulation,
adjustable power supplies, and switching power supplies. The TL432 device has exactly the same functionality
and electrical specifications as the TL431 device, but has different pinouts for the DBV, DBZ, and PK packages.
2.3.10 TPS563210A
The TPS562210A and TPS563210A are simple, easy-to-use, 2-A, 3-A synchronous step-down converters
in 8 pin SOT-23 package. The devices are optimized to operate with minimum external component counts
and optimized to achieve low standby current. These switch mode power supply (SMPS) devices employ
D-CAP2™ control mode providing a fast transient response and supporting both low equivalent series resistance
(ESR) output capacitors such as specialty polymer and ultra-low ESR ceramic capacitors with no external
compensation components.
2.3.11 TPS55330
The TPS55330 is a monolithic nonsynchronous switching regulator with integrated 5-A, 24-V power switch.
The device can be configured in several standard switching-regulator topologies, including boost, SEPIC, and
isolated flyback. The device has a wide input voltage range to support applications with input voltage from
multicell batteries or regulated 3.3- V, 5-V, and 12-V power rails. The TPS55330 regulates the output voltage
with current mode pulse width modulation (PWM) control, and has an internal oscillator. The switching frequency
of PWM is set by either an external resistor or by synchronizing to an external clock signal. The user can
program the switching frequency from 100 kHz to 1.2 MHz.
2.3.12 TPS259470
The TPS25947xx family of eFuses is a highly integrated circuit protection and power management design in a
small package. The devices provide multiple protection modes using very few external components and are a
robust defense against overloads, short-circuits, voltage surges, reverse polarity and excessive inrush current.
With integrated back-to-back FETs, reverse current flow from output to input is blocked at all times, making the
devices a good choice for power MUX and ORing applications as well as systems which need load side energy
hold up storage in case input power supply fails. The devices use linear ORing based scheme to make sure
almost zero DC reverse current and emulate the best diode behavior with minimum forward voltage drop and
power dissipation.

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2.3.13 TL7705A
The TL77xxA family of integrated-circuit supply voltage supervisors is designed specifically for use as reset
controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for
undervoltage conditions at the SENSE input.

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3 Hardware, Testing Requirements, and Test Results

3.1 Hardware Requirements
Figure 3-1 shows the top view of the board and different sections of the TIDA-010239 PCB.

Plug Lock
Driver
Relay Control

E-meter
Conn.
RCD

Communication
Board Conn.
ZC Detect Weld Detect

Pilot Wire

Power Supply

Figure 3-1. TIDA-010239 PCB Top View

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3.2 Test Requirements

3.2.1 Power Supply Test Setup
Figure 3-2 shows a block diagram of the external component arrangement and final connections in the test
setup.

J1772 Charge Electric

Coupler Vehicle Inlet
a
L1
b
GRID
Power c
N
d

L3 L2 e

12VLDO

–12VLDO

GND

3.3 V 1.8 V
5V
12 V power
Figure 3-2. External Component Connections With TIDA-010239 Hardware

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Figure 3-3 shows the test setup. The test setup for the linear regulator and converters consists of the
TIDA-010239 board, DC supply, digital multimeter, electronic load, voltage and current probe.

Oscilloscope
(DC or AC coupling)

CH1
CH1 CH2
CH2

Voltage probe

Isolation VOUT
Transformer
AC Source V
Power Meter Control IOUT
115VAC Mechanism
or and Power A
230VAC Stage
COUT

Load

DUT AC/DC Converter

Current Probe

Figure 3-3. Test Setup for Linear Regulator and Converters in TIDA-010239

Note
• DUT is Device Under Test.
• The oscilloscope analog signal bandwidth requires greater than 400 times the switching frequency.
• The oscilloscope requires higher memory depth and sampling rate to capture ripple waveform
accurately (at least 4 GSPS, memory depth > 1Mpts).
• Oscilloscope probe terminated to 50 Ω.

The tests conducted for this design are as follows:

• Device efficiency and system efficiency at various loads
• Ripple voltage, ripple frequency at full and light load conditions, output voltage accuracy
• Load transient response

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3.2.2 Weld Detect Test Setup

Overview:
• The system checks for the AC signal via ISO1212 when the relay is open. A normal (unwelded) condition
means there are not any output pulses.
• The system checks for the AC signal via ISO1212 when the relay is closed. A normal (AC present) condition
means there are no output pulses.
Complete the following work before powering the TIDA-010239 board.
Connect the AM62_R_ENABLE (pin 36, J2) to 3.3V (TP14_P) to enable the K1 relay at power up.
• Connect oscilloscope probe 1 to LINE1_IN (TP1_P). There is no need to connect the probe 1 reference clip.
• Connect oscilloscope probe 2 to RELAY_CHECK_L1 (J2). Connect the probe 2 reference clip to PGND
(TP7_P).
• Connect oscilloscope probe 3 to RELAY_CHECK_L2 (J2). There is no need to connect the probe 3 reference
clip.
• Connect oscilloscope probe 4 to RELAY_CHECK_L3 (J2). There is no need to connect the probe 4 reference
clip.

Note
1. The oscilloscope reference clip is tied to earth GND by default and for this test setup the
reference clip was connected to PGND. This technically removes the functional isolation of
the circuit but does make the functional testing easier. If isolated measurement is required, an
isolation transformer can be used to power the scope.
2. RELAY_CHECK_N (J2) can also be checked if there is more than 4 channels.

Powering the board for measurement:

• Apply an external 12-V (500 mA) power supply to J1_P so that the relay can be enabled before turning on
the AC line power. This prevents potential arcing when you enable the relay. Normally, AC zero crossing
detection is required before operating the relay. In this case, we are testing with manual relay control.
• With the relay already closed, turn on the AC line power supply (240 VRMS) and observe the waveforms on
the scope.
• When finished, turn off the AC line power first before removing the 12-V supply. The backup supercapacitor
can keep the relay closed for a while even when the AC line power is disconnected.
• The measurement can be repeated with the relay open by disconnecting the AM62_R_ENABLE from 3.3V.

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3.3 Test Results

3.3.1 Isolated AC/DC Power Supply Based on UCC28742
This section shows test data for efficiency over full scale load variation, output voltage regulation, output ripple,
cross regulation, and transient load response waveforms, as well as thermal performance. For all measurements
shown in the screenshots, VAC was set to 115 VRMS, 60 Hz with the oscilloscope set to 20-MHz bandwidth and
in AC coupling (for the voltage ripple measurements).

Note
• +12 V is the 12-V power output (TP4_P) here called also as “12-Vp, where p stands for power.
• +12 Va is the low noise +12-V out of U8_P.
• –12 Va is the low noise -12-V out of U8_P.
• 5 V and 3.3 V are the outputs of U9 and U13 buck converters.

3.3.1.1 Efficiency and Output Voltage Cross Regulation

Total zero-load current power consumption (all outputs active, ultra-capacitor charged):
• 115 VAC, 60 Hz: 485 mW
• 230 VAC, 50 Hz: 548 mW
88
86
84
82
Efficiency (%)

80
78
76
74 Voltage (VAC)
95
72 115
70 230
265
68
0 5 10 15 20 25 30
Total Output Power (W)
Figure 3-4. Output Power vs Efficiency at 95 V and 115 V AC, 60 Hz; 230 V and 265 V AC, 50 Hz

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12.035
VAC
265
12.03

12-VP Rail Output Voltage (V)

230
115
95
12.025

12.02

12.015

12.01

12.005
0 5 10 15 20 25 30
Total Output Power (W)
Figure 3-5. Output Power vs Voltage Regulation

-11.91

-11.92
–12-V Rail Output Voltage (V)

-11.93

-11.94

-11.95

-11.96 VAC
265
230
-11.97 115
95
-11.98
0 5 10 15 20 25 30
Total Output Power (W)
Figure 3-6. Output Power vs Voltage Regulation

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12.01
VAC
12 265

+12-V Rail Output Voltage (V)

230
11.99 115
95
11.98

11.97

11.96

11.95

11.94

11.93

11.92
0 5 10 15 20 25 30
Total Output Power (W)
Figure 3-7. Output Power vs Voltage Regulation

Table 3-1. Test Data at 95 VAC, 60 Hz AC Input

Efficiency
PIN (W) 12 Vp (V) +12 V (V) –12 V (V) I(12 Vp) (mA) I(+12 V) (mA) I(–12 V) (mA) POUT (W)
(%)
0.209 12.03 11.96 –11.93 0.00 0.00 0.00 0.00 0.00%

1.782 12.02 11.96 –11.93 104.7 4.98 –4.97 1.38 77.30%

3.225 12.02 11.96 –11.93 200.9 9.97 –9.94 2.65 82.24%

4.759 12.02 11.96 –11.93 302.8 14.95 –14.91 4.00 83.97%

7.821 12.02 11.97 –11.93 501.3 24.94 –24.85 6.62 84.65%

15.745 12.02 11.98 –11.93 1002.0 49.92 –49.71 13.24 84.06%

34.754 12.02 12.00 –11.93 2200.0 100.00 –99.42 28.83 82.95%

Table 3-2. Test Data at 115 VAC, 60 Hz AC Input

Efficiency
PIN (W) 12 Vp (V) +12 V (V) –12 V (V) I(12 Vp) (mA) I(+12 V) (mA) I(–12 V) (mA) POUT (W)
(%)

0.216 12.02 11.95 –11.93 0.00 0.00 0.00 0.00 0.00%

1.753 12.02 11.95 –11.93 102.1 4.98 –4.97 1.35 76.78%

3.219 12.02 11.95 –11.93 201.0 9.96 –9.94 2.65 82.45%

4.735 12.02 11.95 –11.93 302.8 14.94 –14.91 4.00 84.39%

7.752 12.02 11.95 –11.94 501.3 24.90 –24.88 6.62 85.40%

15.570 12.02 11.95 –11.95 1002.0 49.79 –49.79 13.23 85.00%

34.213 12.01 11.94 –11.97 2200.0 99.50 –99.75 28.80 84.19%

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Table 3-3. Test Data at 230VAC, 50 Hz AC Input

Efficiency
PIN (W) 12 Vp (V) +12 V (V) –12 V (V) I(12 Vp) (mA) I(+12 V) (mA) I(–12 V) (mA) POUT (W)
(%)

0.308 12.02 11.96 –11.93 0.00 0.00 0.00 0.00 0.00%

1.888 12.02 11.96 –11.93 102.1 4.98 –4.97 1.35 71.30%

3.337 12.02 11.96 –11.93 201.0 9.97 –9.94 2.65 79.53%

4.824 12.02 11.96 –11.93 302.8 14.95 –14.91 4.00 82.84%

7.748 12.02 11.97 –11.93 501.3 24.94 –24.85 6.62 85.45%

15.304 12.02 11.98 –11.93 1002.0 49.92 –49.71 13.24 86.48%

33.280 12.02 12.00 –11.92 2200.0 100.00 –99.33 28.83 86.62%

Table 3-4. Test Data at 260VAC, 50 Hz AC Input

Efficiency
PIN (W) 12 Vp (V) +12 V (V) –12 V (V) I(12 Vp) (mA) I(+12 V) (mA) I(–12 V) (mA) POUT (W)
(%)

0.334 12.02 11.96 –11.93 0.00 0.00 0.00 0.00 0.00%

1.932 12.02 11.96 –11.93 102.1 4.98 –4.97 1.35 69.69%

3.391 12.02 11.93 –11.95 200.9 9.94 –9.96 2.65 78.22%

4.878 12.02 11.93 –11.93 302.8 14.91 –14.91 4.00 81.91%

7.795 12.02 11.94 –11.95 501.3 24.88 –24.90 6.62 84.93%

15.312 12.02 11.95 –11.95 1001.9 49.79 –49.79 13.23 86.42%

33.212 12.01 11.97 –11.94 2200.0 99.75 –99.50 28.80 86.73%

Table 3-5. Output Voltage Cross Regulation at 115-V AC, 60-Hz AC Input
I(12 Vp) (mA) I(+12 V) (mA) I(–12 V) (mA) 12 Vp (V) +12 V (V) –12 V (V)

2000 100 100.00 12.09 11.95 –11.94

5 100 100.0 12.01 10.88 –10.88

2000 100 0.0 12.09 11.92 –11.93

2000 0 100.0 12.09 11.94 –11.95

50 100 100.0 12.10 11.95 –11.95

0 0 100.0 12.10 11.94 –10.76

0 0 0.0 12.10 11.94 –11.91

0 100 0.0 12.10 10.48 –11.88

2000 0 0.0 12.09 11.94 –11.91

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3.3.1.2 Efficiency and Output Voltage Regulation of TPS563210

94

93

92
Efficiency (%) 91

90

89

88

87

86

85
0 200 400 600 800 1000
Output Current (mA)
Figure 3-8. 5-V Output Current vs Efficiency

93

91

89

87
Efficiency (%)

85

83

81

79

77

75
0 200 400 600 800 1000 1200
Output Current (mA)
Figure 3-9. 3.3-V Output Current vs Efficiency

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4.99

4.98

4.97

Output Voltage (V)

4.96

4.95

4.94

4.93

4.92

4.91

4.9
0 200 400 600 800 1000
Output Current (mA)
Figure 3-10. 5-V Output Current vs Voltage Regulation

3.32

3.31
Output Voltage (V)

3.3

3.29

3.28

3.27

3.26
0 200 400 600 800 1000 1200
Output Current (mA)
Figure 3-11. 3.3-V Output Current vs Voltage Regulation

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3.3.1.3 Output Voltage Ripple Waveforms

In detail: C1 is –12-V output at 100 mA, C2 is +12-V output at 100 mA, C3 is +12 Vp at 2.2 A.

Figure 3-12. Voltage Ripple on –12 V, +12 V and +12 Vp at Full Load

In detail: C1 is –12-V output at 0 mA, C2 is +12-V output at 0 mA, C3 is +12 Vp at 0 A.

Figure 3-13. Voltage Ripple on –12 V, +12 V and +12 Vp at No Load

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Figure 3-14. Voltage Ripple on 3.3 VOUT at 1 A (1 ms/div)

Figure 3-15. Voltage Ripple on 3.3 VOUT at 1 A (10 μs/div)

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Figure 3-16. Voltage Ripple on 3.3 VOUT at 5-mA Load Current

Figure 3-17. Voltage Ripple on 3.3 VOUT at Zero Load Current

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Figure 3-18. Voltage Ripple on 5 VOUT at 1-A Load Current

Figure 3-19. Voltage Ripple on 5 VOUT at Zero Load Current

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3.3.1.4 Start, Shutdown, Backup Power, and Transient Response Waveforms

Figure 3-20 shows the behavior of the converter during start-up (AC source turned on) with –12 V, +12 V and
+12 Vp at full load. C1 is –12-V output at 100 mA, C2 is +12-V output at 100 mA, C3 is +12 Vp at 2.2 A.

Figure 3-20. Behavior of the Converter During Start-Up

Figure 3-21 shows the behavior of the converter during shutdown (AC source disconnected) with –12 V, +12 V
and +12 Vp at full load. C1 is –12-V output at 100 mA, C2 is +12-V output at 100 mA, C3 is +12 Vp at 2.2 A.

Figure 3-21. Behavior of the Converter During Shutdown

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Figure 3-22 shows the behavior of the converter, loaded according to the specifications with 12 Vp at 0.44 A, and
5-V rail at 275 mA. Here the trace C2 is 12-Vp output (TP4_P), C1 is 5-V output and C4 is input VAC.

Figure 3-22. Backup Supply Behavior After AC Source is Disconnected

Figure 3-23 shows the transient response of the 5 VOUT when switched between zero and 1 A load current.

Figure 3-23. Transient on 5 VOUT 0–1 A Load

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Figure 3-24 shows the transient response of the 3.3 VOUT when switched between zero and 1-A load current.

Figure 3-24. Transients on 3.3 VOUT 0 A to 1 A

Figure 3-25 shows the transient response of the converter with zero to 2-A transients on 12 VOUT, while 12 V
and –12 V are loaded both at 100 mA. C1 is –12-V output at 100 mA, C2 is +12-V output at 100 mA, C3 is +12
Vp with switched load and C4 is the 12 Vp output current.

Figure 3-25. Transient Response of the Converter With Zero to 2-A Transients on 12 VOUT

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Figure 3-26 shows the transient response of the converter with zero to 2-A transients on 12 VOUT, while 12 V
and –12 V are both loaded at zero current. C1 is –12-V output at 0 mA, C2 is +12-V output at 0 mA, C3 is +12
Vp with switched load and C4 is the 12-Vp output current.

Figure 3-26. Transient Response of the Converter With Zero to 2-A Transients on 12 VOUT

Figure 3-27 shows the transient response of –12-V output with 12 Vp fully loaded. C1 is –12-V output switched
from 100 mA to zero and C4 is the –12-V output current.

Figure 3-27. Transient Response of –12-V Output With 12 Vp Fully Loaded

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Figure 3-28 shows the transient response of –12-V output with 12 Vp fully loaded. C1 is –12-V output switched
from zero to 100 mA and C4 is the –12-V output current.

Figure 3-28. Transient Response of –12-V Output With 12 Vp Fully Loaded

Figure 3-29 shows the transient response of +12-V output with 12 Vp fully loaded. C2 is +12-V output switched
from zero to 100 mA and C4 is the +12-V output current.

Figure 3-29. Transient Response of +12-V Output With 12 Vp Fully Loaded

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Figure 3-30 shows the transient response of +12-V output with 12 Vp fully loaded. C2 is +12-V output switched
from 100 mA to zero and C4 is the +12-V output current.

Figure 3-30. Transient Response of +12-V Output With 12 Vp Fully Loaded

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3.3.1.5 Thermal Performance

Figure 3-31. Top View of AC/DC Stage at 120-V AC, 60-Hz AC Input

Table 3-6. Main Image Markers (Top Side)

NAME TEMPERATURE EMISSIVITY BACKGROUND

RT3_P 64.3°C 0.96 25.5°C

Q2_P 61.3°C 0.96 25.5°C

T1_P 62.1°C 0.96 25.5°C

U8_P 53.1°C 0.96 25.5°C

U13_P 47.9°C 0.96 25.5°C

U9_P 49.3°C 0.96 25.5°C

L17_P 44.7°C 0.96 25.5°C

L13_P 44.2°C 0.96 25.5°C

U3_P 54.0°C 0.96 25.5°C

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Figure 3-32. Bottom View of AC/DC Stage at 120-V AC, 60-Hz AC Input

Table 3-7. Main Image Markers (Bottom Side)

NAME TEMPERATURE EMISSIVITY BACKGROUND

D10_P 53.5°C 0.96 25.5°C

R15_P 51.5°C 0.96 25.5°C

D6_P 61.6°C 0.96 25.5°C

D9_P 60.1°C 0.96 25.5°C

Q2_P 63.7°C 0.96 25.5°C

R35_P 57.2°C 0.96 25.5°C

Q1_P 55.1°C 0.96 25.5°C

D7_P 52.9°C 0.96 25.5°C

D2_P 51.8°C 0.96 25.5°C

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3.3.2 TLV1805-Based Control Pilot Interface

This section shows test data for control pilot signal logic high and low voltage, pulse width, and frequency.
3.3.2.1 TLV1805 Output Rise and Fall Time
Figure 3-33 and Figure 3-34 show the rise and fall times of the TLV1805 control pilot signal generator.

Figure 3-33. TLV1805 Control Pilot Signal Figure 3-34. TLV1805 Control Pilot Signal
Generator Rise Time Generator Fall Time

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3.3.2.2 Control Pilot Signal Voltage Accuracy in Different States

Figure 3-35 through Figure 3-38 show the control pilot signal voltage accuracy in different states.

Figure 3-35. Control Pilot Signal Voltage Accuracy Figure 3-36. Control Pilot Signal Voltage Accuracy
in State A in State B

Figure 3-37. Control Pilot Signal Voltage Accuracy Figure 3-38. Control Pilot Signal Voltage Accuracy
in State C in State D

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3.3.3 DRV8220-Based Relay and Plug Lock Drive

Figure 3-39. Relay Drive Waveforms

Figure 3-40. Plug Lock Drive Waveforms

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3.3.4 ISO1212-Based Isolated Line Voltage Sensing

For this reference design, the high and low thresholds are set to 125 VRMS and 121 VRMS, respectively. The
measured high and low thresholds are 178 V (126 VRMS) and 170 V (120 VRMS) as shown in Figure 3-42.

Figure 3-41. ISO1212 Digital Outputs and Input Line Voltage When Relay is Closed with Labels

Figure 3-42. ISO1212 Digital Outputs and Input Line Voltage When Relay is Closed with Cursors

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4 Design and Documentation Support

4.1 Design Files
4.1.1 Schematics
To download the schematics, see the design files at TIDA-010239.
4.1.2 Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-010239.
4.2 Documentation Support

1. Texas Instruments, TIDA-00637: Level 1&2 Electric Vehicle Service Equipment Reference Design
2. Texas Instruments, TLV1805 40V, Rail-to-Rail Input, Push-Pull Output, High Voltage Comparator with
Shutdown data sheet
3. Texas Instruments, ISO121x Isolated 24-V Digital Input Receivers for Digital Input Modules data sheet
4.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
4.4 Trademarks
TI E2E™, MSP430™, TINA-TI™, D-CAP2™, and are trademarks of Texas Instruments.
Würth Elektronik™ is a trademark of Würth Elektronik GmbH & Co. KG.
All trademarks are the property of their respective owners.
5 About the Author
KELVIN LE is a systems engineer at Texas Instruments, where he is responsible for developing system
solutions for the grid sector with a focus on EV charging. Kelvin has been with TI since 2015. Kelvin earned
his Bachelor of Science in Biomedical Engineering from the University of Central Oklahoma and his Master of
Science in Electrical and Computer Engineering from the University of Texas at Austin.
ERROL LEON graduated with BSEE and MSEE from Cal Poly San Luis Obispo in 2015. Errol works with Texas
Instruments' grid infrastructure team with a focus on electric vehicle charging and smart meter. Has experience
with analog front end signal chains, PLC, and communication protocols.
ROBERTO SCIBILIA received his master's degree in Electronic Engineering in 1989 from university of Palermo
(Italy). Before joining Texas Instruments in 2007 in the European Power Reference Design team (PDS), he
worked from 1990 to 2007 in the telecom industry as a design engineer, developing telecom rectifiers, solar
inverters and UPS. In the PDS team he is designing custom power supplies for high-production volume
applications, supporting calculation, simulation, schematic entry, board layout, and prototype testing.

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