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CAO BS - Assignment # 03

This document provides instructions for Assignment #3 in Computer Architecture & Organization for the 4th semester of a BS in Computer Science. It notes that all questions must be answered individually without copying and submitted through the learning management system by the due date to receive grading. The assignment contains two questions - Question 1 involves calculating memory requirements, drawing a cache diagram and determining cache block assignments. Question 2 asks to explain tightly vs loosely coupled microprocessors, cache coherence, memory addressing lines, instruction execution flow, and differences between assembly and high-level languages.

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73 views1 page

CAO BS - Assignment # 03

This document provides instructions for Assignment #3 in Computer Architecture & Organization for the 4th semester of a BS in Computer Science. It notes that all questions must be answered individually without copying and submitted through the learning management system by the due date to receive grading. The assignment contains two questions - Question 1 involves calculating memory requirements, drawing a cache diagram and determining cache block assignments. Question 2 asks to explain tightly vs loosely coupled microprocessors, cache coherence, memory addressing lines, instruction execution flow, and differences between assembly and high-level languages.

Uploaded by

harisafridi09876
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Computer Architecture & Organization

Assignment # 3
BS (CS), 4th Semester

Note the following:


1. All questions should be attempted by each individual student and copy/paste is strictly
prohibited. Those who do not follow the instructions, will be marked zero in their
respective assignments.
2. As this is part of semester course assessment’s, it should be submitted through LMS only
and within due date. Assignment submitted after the deadline will not be accepted nor
graded.
3. Answer the questions in your own neat handwriting and scan & submit it through LMS.

Q1. a. How many 128 x 8 memory chips are needed to provide a memory capacity of 4096 x 16?
b. A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8 bytes
in each block. The physical address size is 32 bits, and the smallest addressable unit is 1 byte.
I. Draw a diagram showing the organization of the cache and indicating how physical
addresses are related to cache addresses.
II. To what block frames of the cache can the address 000010AF16 be assigned?
III. If the addresses 000010AF16 and FFFF7Axy16 can be simultaneously assigned to the
same cache set, what values can the address digits x and y have?

Q2. Briefly explain the followings:


a. Differentiate between tightly coupled and loosely coupled microprocessor from the
viewpoint of hardware organization and programming techniques?
b. What is cache coherence and why it is important in shared memory multiprocessors
system?
c. How many lines of the address bus must be used to access 2048 bytes of memory? How
many of these lines will be common to all the chips?
d. Explain with the help of flow diagram how an instruction is fetched, decoded and
executed?
e. What are the advantages of assembly language? How is it different from high- level
language?

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