Mark Bohr

Silicon
Trends
and Limits
for Advanced
Microprocessors
Beyond the Gordon Moore, one of the founders of Intel,
physical, chemical, first observed in the early 1970s that inte-
and intellectual grated circuit complexity, as measured by the
number of transistors per chip, was increasing
limits designers
at an exponential rate and that this rate had
have overcome for
been consistent over many years. He went fur-
the past 25 years
ther to predict that transistor count on lead-
may lie the
ing-edge circuits would double every 18
ultimate limit to months until fundamental physical limits
microprocessor were reached. His prediction was remarkably
design—money. accurate over the past 25 years, and we have
80 March 1998/Vol. 41, No. 3 COMMUNICATIONS OF THE ACM
 yet to reach the fundamental limits of silicon-based improvement in the industry for more than 20 years.
technology (see Figure 1). The continued increase New integrated circuit technology generations are
in transistor count has been achieved through a often referred to by the minimum feature size used in
combination of reduced transistor dimensions along units of micrometers (mm, equivalent to 1026m).
with an increase in chip size. Recent examples are the introduction by Intel of the
Reduced transistor dimensions have been possible 0.8mm generation in 1989, 0.5mm in 1992, and
due to continued improvements in 0.35mm in 1995. By reducing the wavelength of the
integrated circuit patterning exposing light, using better lenses, and improving
technology and to the the photosensitive films, optical lithog-
excellent scaling proper- raphy is now patterning
ties of metal-oxide-semi- 0.25mm minimum
conductor (MOS) transistors. feature sizes in high-
Robert Dennard of IBM’s volume production.
T.J. Watson Research This process is
Center was the first extendible to
researcher to propose the 0.18mm
an effective scaling generation, which
algorithm for MOS will be used to
transistors that make Intel’s Merced
simultaneously im- microprocessor in
proved density, 1999, and beyond
performance, and that to the 0.13mm-
power [6]. His generation.
scaling theory New-generation process
called for reduc- technologies generally
ing transistor dimen- come out every three
sions (such as years and provide roughly
channel length, chan- a 0.73 reduction in mini-
nel width, and gate oxide mum feature size. Using
thickness) and power supply, all by a 0.73 as the scale factor S,
given scale factor S, where S is a value less than 1. turning of the generations gives a
The result would be a transistor whose area is transistor area improvement of 0.493,
reduced by S2, whose gate delay (or switching speed) a gate delay improvement of 0.73, and an energy
is improved by S, and whose amount of energy used reduction of 0.343 for every new process generation.
each time a gate switches on or off is reduced by S3. Figure 2 shows how transistor parameters have scaled
The driving engine behind transistor scaling is over the last six generations of Intel microprocessor
the ability to pattern ever-smaller feature sizes. Pat- technology. Minimum feature size and gate oxide
terns are printed on integrated circuit wafers by thickness (TOX) have been scaled down by ~0.73
focusing light through masks and onto photosensi- with every generation, while supply voltage (VDD)
tive films on the wafer surface. This technique, called has been scaled down only for the last three genera-
optical lithography, has constantly been improved, tions. Until the 0.8mm generation, 5V was the
extending down to dimensions thought impossible industry standard supply voltage; power and relia-
by process technologists just a few years ago. To sup- bility were not yet significant enough concerns to
port the transistor density improvements in Figure justify deviating from the standard supply voltage.
1, minimum feature sizes have had to be reduced by But beginning with the 0.5mm generation, chip
~0.73 every three years. This has been the rate of power and gate oxide reliability concerns forced

Intel 233-Mhz mobile Pentium with MMX technology and 4.5 million transistors (courtesy Intel Corp.)

COMMUNICATIONS OF THE ACM March 1998/Vol. 41, No. 3 81

 transistors are turned off with a
1E+8 positive gate bias.) Technologies
providing these two opposite tran-
1E+7
®
Pentium Pro processor DEC21264 sistor types are referred to as com-
PPC620
Pentium ® processor PPC604 plementary MOS (CMOS)
PPC601 technologies. CMOS technologies
486  Sparc
1E+6 68040 MIPS4400 allow digital circuits to be
Transistors 386  DEC21064
designed with signals that have full
per Chip
1E+5
80286 voltage swing (from ground to
Note:
8086
power supply) and extremely low
Numbers=
Numbers
standby, or leakage, current.
of Zeros 1E+4 Trenches are etched into the silicon
substrate and filled with an insu-
4004
1E+3 lating silicon dioxide (SiO2) layer
1970 1975 1980 1985 1990 1995 2000 2005 to form the shallow trench isola-
Year tion between devices. Special
impurities are implanted into the
Figure 1. CPU transistor count 1970–2005 silicon to form P-type and
N-type well regions for the
N-channel and P-channel
1000 100
transistors. A thin silicon
dioxide insulating gate oxide
is next formed on the silicon
Inverter substrate surface. Such layers
Delay
(picosec.) are often measured in units of
TOX nanometers (nm, equivalent
Delay V ( )
V, to 1029 meter). On this
100 10 DD
TOX (nm) technology, the gate oxide is
4.5nm thick. A polysilicon
VDD gate layer is then deposited
and patterned over the gate
oxide. The length of this gate
(LG) is a key factor in transis-
1
tor performance, and consid-
10
0.25 0.35 0.5 0.8 1.0 1.5 erable effort goes into
Technology Generation (µm) learning ways to form
smaller gate lengths with
Figure 2. Transistor parameter trends tight dimensional control.
For Intel’s 0.25mm technology, the latest lithog-
adoption of scaled supply voltages with every new raphy tools using deep ultraviolet (DUV) light
generation. Throughout this period, transistor per- sources are used to pattern this gate layer. LG is tar-
formance, measured by inverter circuit delay, geted to be slightly less than 0.25mm to achieve
improved by ~0.73 per generation. So indeed, MOS maximum performance. Following the patterning of
transistor scaling has served us well by providing the gate layer, more N-type and P-type impurities
continued improvements in density, performance, are added next to the gates to form conductive
and power. source-drain regions and complete the MOS transis-
A cross-sectional diagram of the MOS transistors tor structure. A thin titanium silicide (TiSi2) con-
used on Intel’s latest 0.25mm microprocessor tech- ducting layer is added on top of the gate and
nology [5] is shown in Figure 3. Two types of MOS source-drain regions to further lower their sheet
transistors—N-channel and P-channel—are made resistance and improve transistor performance. Sili-
by this process using separate masking steps that con nitride (Si3N4) insulating spacers are formed on
introduce different dopant impurities into the MOS the sides of the polysilicon gates before the titanium
transistor structure. (N-channel transistors are silicide layer to prevent short circuits between the
turned on with a positive gate bias, while P-channel polysilicon gate and source-drain structures.

82 March 1998/Vol. 41, No. 3 COMMUNICATIONS OF THE ACM

 The transistors developed for Intel’s 0.25mm-gen-
eration technology use aggressive scaling techniques L G Shallow
Trench
Polysilicon Gate
Isolation Gate Oxide
to provide significant improvements in density, per- Si3N4
N+ TiSi2 P+
formance, and power over the 0.35mm generation
[4] of only three years ago. Transistor density is N+ N+ P+ P+
increased by almost a factor of 2, inverter delay is STI
improved by ~30%, and the reduced supply voltage P-well N-well
reduces circuit power consumption. These process
P-Silicon Substrate
technology improvements, coupled with circuit
design and microprocessor architecture improve-
ments, provide dramatic increases in microprocessor Figure 3. CMOS transistor cross-section
performance at reduced power
levels. The first product based 7 10
on this 0.25mm technology
was a high-performance, low- 6 + 0.75 Layer 0.77xper
power Pentium processor with per Generation Generation
MMX technology intended for 5
the laptop computer market, Average
indicating the increased 4 Metal
Number
importance of this market as Pitch
of Metal
well as the need to develop (µm)
Layers 3
technologies with low power
in mind. Other products based 2
on this technology introduced
last January include a 266- 1
MHz mobile Pentium with
MMX (Tillamook) and a 333- 0 1
MHz Pentium II (Deschutes) 0.25 0.35 0.5 0.8 1.0 1.5
Technology Generation (µm)
intended for desktop and
server applications.
Figure 4. Intel interconnect trends
Interconnect Scaling
uch attention has been paid to was not a concern in older technologies because the

M transistor improvement in the

course of integrated circuit devel-
opment, while the on-chip inter-
connects have been a relatively
minor factor in circuit performance. Unfortunately,
however, interconnects don’t have the same scaling
properties as transistors, and interconnects are
average RC delay was only a tiny fraction of the
clock cycle time. In newer technologies, RC delay
is increasing while clock cycle times are decreasing;
therefore, interconnect delay is now a significant
fraction of clock cycle time.
One way to meet the challenge of improving both
the density and the performance of interconnects is
quickly becoming as critical as transistors in deter- to add more layers of interconnects. Figure 4 shows
mining overall circuit performance [3, 5]. The how the average pitch (minimum line width plus
average width of interconnects is decreasing to pro- minimum space) and number of interconnect layers
vide the smaller dimensions needed to pack in more has evolved over the past six generations of Intel
transistors and more wires. As a result, average logic technology. The average pitch did not scale as
interconnect resistance is increasing. The speed at aggressively as the normal 70% target in order to
which a signal can propagate down a wire is pro- minimize the harmful effect of small pitch on RC
portional to the product of the wire resistance (R) delay. More metal layers were added to meet the
and the wire capacitance (C). This speed is known interconnect density requirements. Over these gen-
as the wire’s RC delay. Increased wire resistance, or erations, the average metal layer thickness was held
capacitance, results in increased RC delay and roughly constant, because thinning the metal would
slower signal propagation. Whereas MOS transis- have further degraded the RC delay problem. The
tors tend to get faster with each new generation, result is that on-chip interconnect cross-sections
interconnects tend to get slower. Interconnect delay have evolved from relatively wide and flat lines to

COMMUNICATIONS OF THE ACM March 1998/Vol. 41, No. 3 83

relatively narrow and tall lines. Integrated circuit
process technologists now spend as much effort
developing advanced interconnects as they do devel- M5
oping transistors, and the process steps involved in
forming the interconnects now represent about 50%
of Intel’s total wafer process cost. M4
Figure 5 shows a cross-sectional diagram of the Tungsten Via
interconnect structure used on Intel’s 0.25mm-gen-
M3
eration logic technology. Five layers of aluminum
wires are used to connect the transistors and route SiO2
signals and power. The lower three layers have finer M2
pitch and thinner metal. These layers are used for
M1
short-distance interconnects, in which density (small Transistors
pitch) is more critical than RC delay. The top two
layers have coarser pitch and thicker metal. These Silicon Substrate
layers are used for routing signals and power over Figure 5. Interconnect cross-section
longer distances on the circuit. Low resistance and
small RC delay are more important than tight pitch Beyond that, the industry road map calls for a new
on these interconnect layers. A silicon dioxide layer technology generation every 2-1/2 to three years,
is formed as the insulator between metal layers. The each providing roughly a 23 density improvement
silicon dioxide layer is deposited over each of the and a 30% gate delay reduction.
patterned metal layers and then planarized using a The first manufacturing issue to be addressed in
chemical-mechanical polishing (CMP) technique. future technologies is how to pattern ever-smaller
The planarized surface is needed to facilitate pat- feature sizes economically. The resolution capability
terning of the subsequent via, or etched vertical of optical lithography is proportional to the wave-
interconnect, and metal layers. With CMP, any length of light used. Today’s 0.25mm technologies
number of metal layers can be added to a wafer with- use DUV laser light with a wavelength of 248nm, or
out concerns about severe topography limiting the close to 0.25mm. There are special optical tech-
ability to pattern more layers. The only limit to the niques for improving resolution capability below the
number of metal layers is the additional process cost. wavelengths of light, such as phase-shifting masks
Tungsten-filled vias form the vertical interconnects [1], but these techniques provide only a half step in
between layers. These interconnects are made by first resolution improvement, and ultimately the need to
etching the via openings in the silicon dioxide insu- reduce wavelength cannot be avoided. The next laser
lator, then depositing a tungsten film that covers the light source available in the DUV range has a wave-
entire wafer surface and fills the via openings, and length of 193nm. Beyond that is the extreme ultra-
finally removing the tungsten from the wafer surface violet (EUV) regime, with wavelengths of ~13nm,
with another CMP step. As Figure 5 indicates, the and beyond that is the X-ray regime, with wave-
interconnect structure is large relative to the size of lengths of ~1nm. These wavelengths are obviously
the transistors, providing a further indication of the short enough to resolve the feature sizes needed, but
increased importance of interconnects in integrated many practical problems remain to be solved in the
circuit density and performance. design of lenses for EUV and the making of masks
for X-rays. Photosensitive films optimized for each
Limits of Silicon Device Scaling of these new wavelengths also need to be developed.
OS transistor scaling has worked Some lithography experts question whether these

M remarkably well for more than 30

years and is the main reason why
the integrated circuit industry has
been so successful. But can tran-
sistor scaling continue, or is there an end in sight?
Products using 0.25mm-generation technologies
are just now being introduced in high-volume
problems will be solved in time for the 0.13mm and
0.09mm technology generations, only 5–10 years
away. Some experts also question whether the solu-
tions will be cost-effective for high-volume manu-
facturing, in which typical integrated circuit process
flows have 20 or more patterning steps.
As shown in Figure 2, scaling of gate oxide thick-
manufacturing. Work on the next-generation tech- ness has been a key component in scaling of MOS
nology, 0.18mm, is well under way, and products transistors. Until the 0.8mm generation, supply
should be introduced around the end of the decade. voltage did not scale in order to be consistent with

84 March 1998/Vol. 41, No. 3 COMMUNICATIONS OF THE ACM

the industry standard. The result was continued age should be much higher than the transistor
increases in the strength of the electric field across threshold, or turn-on, voltage. Good transistor per-
the gate oxide as thickness decreased and supply formance can be maintained while reducing supply
voltage stayed constant. If the electric field becomes voltage by also reducing threshold voltage, but mak-
too strong, the gate oxide insulator breaks down and ing threshold voltage too low results in leaky tran-
begins leaking. Starting with the 0.5mm generation, sistors that cannot be fully turned off. The past four
supply voltage was reduced along with gate oxide generations of Intel logic technology have seen sup-
thickness to prevent the electric field from getting ply voltage decrease from 5V to 1.8V, while thresh-
too strong. The next barrier facing gate oxide scaling old voltage has decreased from 0.9V to 0.45V. Future
is direct electron tunneling through the insulator. technologies will require transistors with even lower
This barrier begins occurring at gate oxide thick- threshold voltages to keep pace with reduced power
nesses below 2nm and can cause both reliability and supplies, but increased transistor leakage will pose
circuit functionality concerns. New gate oxide mate- challenges for circuit designers.
rials need to be identified
to address the electric field ther technolo-
and electron tunneling
limits foreseen with silicon
dioxide.
Although gate oxide
reliability was the initial
motivation for reducing
supply voltage, chip power
The first
manufacturing
issue to be
O gies that have
been consid-
ered as replace-
ments
mainstream silicon transis-
tors include silicon-on-insu-
lator (SOI) and gallium
for

constraints have grown to addressed on arsenide (GaAs). The SOI

become as significant a
consideration. High-per- future technologies device differs from the tradi-
tional MOS transistor only
formance microprocessors
with millions of transistors
is how to pattern in that a thin silicon dioxide
layer is added under the
operating at high frequen-
cies can consume tens of
ever-smaller source-drain and channel
regions. The main advantage
watts of active power, not feature sizes is reduced junction capaci-
only putting them out of tance and, in some cases, the
range of mobile applica- economically. ability to scale threshold
tions but challenging the voltage lower without
heat-sinking capabilities of increasing transistor leakage
desktop applications. current. The extra cost and
Active power is propor- defects associated with the
tional to C 3 VDD2 3 f, added silicon dioxide layer
where C is total node have been barriers to wide
capacitance on the chip, VDD is supply voltage, and acceptance for SOI. The insulating silicon dioxide
f is operating frequency. Reducing supply voltage is layer also creates a “floating-body” effect in the tran-
clearly the most effective way to reduce active power. sistor, leading to unstable operation. Last, despite
Lowering supply voltage in the past several technol- the theoretical performance advantages of SOI, the
ogy generations has allowed new microprocessor rapid advances in performance on traditional MOS
designs to include more transistors and use higher transistors have made it difficult to conclusively
frequencies with only slight increases in power. At prove that SOI provides a realizable performance
the same time, it’s been possible to migrate older advantage to offset the related cost and defect
microprocessor designs with relatively fixed transis- concerns.
tor counts to the new process technology and provide GaAs has long been considered an attractive alter-
improved performance at lower power, often native to silicon as a material to make transistors
enabling the transition from desktop to mobile because the electrons in N-channel transistors move
applications. more quickly through GaAs than through silicon,
Although reducing supply voltage helps reduce resulting in higher performance. Unfortunately,
power consumption, it can also degrade transistor CMOS designs require both high-performance N-
performance. To maximize performance, supply volt- channel and P-channel devices, and P-channel tran-

COMMUNICATIONS OF THE ACM March 1998/Vol. 41, No. 3 85

sistors are slower on GaAs compared to those on sil- the industry. These alloys have a resistivity of
icon. It is also unclear whether N-channel transistor ~3mohm/cm. Gold, silver, and copper are the only
performance will continue to be better on GaAs as other naturally occurring elements with resistivities
device dimensions continue to scale. There is no lower than aluminum. The resistivity of gold
question that the current generation of GaAs circuits (2.3mohm-cm) is about 23% lower than that of alu-
is fast, but lack of CMOS capability forces circuit minum alloys, but gold has adhesion problems and
designs to use much higher power levels that cost concerns, so it is not generally considered an
are unacceptable in many integrated circuit option worth pursuing. Silver has the lowest resis-
applications. tivity of all (1.6mohm/cm) but corrodes easily. Cop-
Despite the many challenges in future MOS tran- per has a resistivity near that of silver (1.7mohm-cm)
sistor scaling, various and is getting a lot of atten-
industry research groups tion from the industry as a
continue to demonstrate possible successor to alu-
advanced devices with the
expected performance char-
Not clear is minum. Copper’s almost
23 reduction in resistivity
acteristics at dimensions whether optical relative to aluminum alloys
down to and below 0.1mm means an almost 23
[2, 5, 7]. Admittedly, these interconnects will improvement in intercon-
laboratory devices do not
yet meet all of the reliabil- be successful in nect RC delay. Copper has
one major problem, in that
ity and manufacturing
requirements of a high-vol-
transmitting data it tends to diffuse rapidly
through silicon and silicon
ume process, but with time
and effort, they will. Even-
over millimeter dioxide and can cause leak-
age problems, but thin bar-
tually, however, gate oxides to centimeter rier layers are being
will be one molecular layer
thick and transistor leakage distances in such investigated as a means of
preventing these problems.
will be higher than what
circuit design can toler-
applications as Recent announcements by
IBM, Motorola, and Semat-
ate—at which point silicon
device scaling will reach a
microprocessors. ech indicate the introduc-
tion of integrated circuit
physical limit. products using copper
interconnects is about to
Future Interconnect arrive. Intel will produce
Requirements copper processors when the
nterconnect dimen- market involves enough

I sions have been decreasing as the number of

interconnect layers has been increasing.
Although interconnect density requirements
are being met through this trend, intercon-
volume to sustain manufacturing on an industrial
scale.

nother way to improve interconnect

nect performance has been slowing down and will
soon be a major impediment to improving large-
scale circuit performance. Interconnect perfor-
mance could be improved by doing reverse scaling
of interconnect dimensions (increase line width and
thickness), but then, in order to meet density
requirements, the number of metal layers would
A performance is to reduce the capaci-
tance between wires. Some new insu-
lator materials being investigated
have lower capacitance than silicon
dioxide, providing approximately a 23 reduction in
capacitance, which would provide interconnects
twice as fast as previous generations. With intercon-
have to grow at a much faster rate. We would nect capacitance becoming a large portion of total
quickly reach a point where the financial cost of the chip capacitance, reduced interconnect capacitance
added layers would be excessive. New interconnect also reduces active chip power. Although the num-
materials are needed to improve performance with- ber of insulator material options is large, ranging
out increasing the number of metal layers. from adding special impurities to silicon dioxide to
Aluminum or, to be precise, aluminum-based using polymer materials and bubble-filled glass,
alloys are the standard interconnect material used in none has yet been identified that meets all of the

86 March 1998/Vol. 41, No. 3 COMMUNICATIONS OF THE ACM

stringent material properties required in modern increasingly important need for interconnect den-
integrated circuit processing. Introduction of these sity and performance. Many challenges remain in
low-capacitance insulators, especially in conjunction meeting future transistor and interconnect require-
with copper interconnects, will provide a significant ments, but the early indications coming out of
boost in interconnect performance within one or two research organizations—plus the confidence that
generations. comes from an industry that has so successfully sur-
Eventually, even low-capacitance insulators with mounted previous obstacles—suggest that inte-
copper conductors will not be able to meet the ever- grated circuit technology will continue to progress
increasing demands for interconnect performance. A at a healthy pace for at least three or four more gen-
more revolutionary change will be needed. Optical erations. Beyond that point, financial and business
interconnects (using light in waveguides instead of considerations are likely to be the main factors lim-
electrons in metal wires) are one possibility that has iting further advancements in silicon technology.
already shown success for high-bandwidth data The cost of patterning extremely small transistors
transmissions covering distances from meters to and forming multiple layers of interconnects with
thousands of kilometers. Not clear, however, is ever more exotic materials while still meeting tol-
whether optical interconnects will be successful in erance and defect density requirements will eventu-
transmitting data over millimeter to centimeter dis- ally be uneconomical, slowing the pace of
tances in such applications as microprocessors. Most integrated circuit evolution unless other feasible
internal microprocessor signals involve transmitting means emerge. c
an individual datum point to point, as opposed to
sending long series of data. The extra delay in con- References
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mann, L., Comfort, J., and Sunderland, D. Phase edge lithography for
back to electrical can be significant and thus negate sub-0.1mm electrical channel length in a 200mm full CMOS process.
the speed and bandwidth benefits of the optical In Tech. Dig. of the Symposium on VLSI Technology (Kyoto, June 6–8,
1995), IEEE Press, Piscataway, N.J., pp. 79–80.
interconnect. There are also physical issues involved 2. Asai, S., and Wada, Y. Technology challenges for integration near and
in making optical devices on silicon. Silicon is an below 0.1mm. Proc. IEEE 85, 4 (April 1997), 505–520.
inefficient material for making light sources; GaAs is 3. Bohr, M. Interconnect scaling—The real limiter to high-performance
ULSI. In Tech. Dig. of the International Electron Devices Meeting (Wash-
much better. Optical interconnect technology typi- ington, D.C., Dec. 10–13, 1995), IEEE Press, Piscataway, N.J., pp.
cally uses light in the infrared region (wavelength 241–244.
4. Bohr, M., Ahmed, S., Brigham, L., Chau, R., Gasser, R., Green, R.,
~1mm). This relatively long wavelength requires Hargrove, W., Lee, E., Natter, R., Thompson, S., Weldon, K., and
waveguides with a minimum pitch of 2mm, which is Yang, S. A high-performance 0.35mm logic technology for 3.3V and
larger than recent metal pitches, so designers of opti- 2.5V operation. In Tech. Dig. of the International Electron Devices Meeting
(San Francisco, Dec. 11–14, 1994), IEEE Press, Piscataway, N.J., pp.
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Hainsey, R., Jan, C., Packan, P., Sivakumar, S., Thompson, S., Tsai, J.,
data transmission can be used to reduce the number and Yang, S. A high-performance 0.25mm logic technology optimized
of interconnects. for 1.8V operation. In Tech. Dig. of the International Electron Devices Meet-
Another longer-range possibility for improving ing (San Francisco, Dec. 8–11, 1996), IEEE Press, Piscataway, N.J., pp.
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ature superconductors. Superconducting properties LeBlanc, A. Design of ion-implanted MOSFETs with very small phys-
would have to be maintained at normal chip opera- ical dimensions. IEEE J. Solid State Circuits SC-9, 5 (Oct. 1974),
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These are demanding requirements no superconduc-
tor material is yet close to meeting.
Mark Bohr (mark_bohr@[Link]) is a member of
Intel Corp.’s Portland Technology Development group where he
Conclusions is Director of Process Architecture and Integration and an
Silicon process evolution continues to progress at an Intel Fellow.
astounding pace, with 0.25mm-generation prod-
Permission to make digital/hard copy of part or all of this work for personal or class-
ucts being introduced in 1997, at least a year ear- room use is granted without fee provided that copies are not made or distributed for
lier than many in the industry thought possible just profit or commercial advantage, the copyright notice, the title of the publication and
its date appear, and notice is given that copying is by permission of ACM, Inc. To
a few years ago. Aggressive MOS transistor scaling copy otherwise, to republish, to post on servers, or to redistribute to lists requires
is offering benefits in density, speed, and power. prior specific permission and/or a fee.

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COMMUNICATIONS OF THE ACM March 1998/Vol. 41, No. 3 87