UNIVERSITY OF SOUTH AFRICA

SCHOOL OF ENGINEERING
CONTINUOUS ASSESSMENT

TEST NO: 527381

Semester Course

MCD2601

MICRO-CONTROLLER SYSTEMS

Examiner: Ms. N.P.F. Nqukwe Moderator: Ms K. Chetty

Marks: 50 Weight of Assessment: 35%
INSTRUCTIONS TO ALL STUDENTS:

YOUR SCRIPT MUST BE SAVED WITH STUDENT NO, SUBJECT CODE AND
UPLOADED ON ASSESSMENT 6 PLATFORM. EXAMPLE 72111985QAS401I
• Honesty Declaration must be completed
• The module is IRIS invigilated
Additional student instructions
1. Students must upload their answer scripts in a single PDF file (answer scripts must
not be password protected or uploaded as “read only” files)
2. NO emailed scripts will be accepted.
3. Students are advised to preview submissions (answer scripts) to ensure legibility
and that the correct answer script file has been uploaded.
4. Students are permitted to resubmit their answer scripts should their initial
submission be unsatisfactory.
5. Incorrect file format and uncollated answer scripts will not be considered.
6. Incorrect answer scripts and/or submissions made on unofficial examinations
platforms (including the invigilator cellphone application) will not be marked and no
opportunity will be granted for resubmission.
7. Mark awarded for incomplete submission will be the student’s final mark. No
opportunity for resubmission will be granted.
8. Mark awarded for illegible scanned submission will be the student’s final mark. No
opportunity for resubmission will be granted.
9. Submissions will only be accepted from registered student accounts.
10. Students who have not utilised invigilation or proctoring tools will be subjected to
disciplinary processes.
11. Students suspected of dishonest conduct during the examinations will be
subjected to disciplinary processes. UNISA has a zero tolerance for plagiarism and/or any
other forms of academic dishonesty.
12. Students are provided one hour to submit their answer scripts after the official
examination time. Submissions made after the official examination time will be rejected.
To proceed with the writing of the examination, click on the link below:
[Link]

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Instructions to Candidates
1. Answer all questions.
2. Diagrams and schematics will be marked as follows: Marks will be allocated for
the correct components or blocks added to the diagram or schematic and marks
will be deducted for each wrong connection of these components or blocks on the
diagram or schematic or for any additional components or blocks unnecessarily
added to the diagram or schematic.
3. No cheating is allowed.
4. By writing this paper, the student agrees to abide by all UNISA, subject and test
rules and regulations.

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 SECTION A

Section A contains Multiple Choice, True/False and other types of short questions.

For multiple choice questions, please put a cross on the correct answer. For
True/False question answer with either a T for true or a F for False [20]

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 Section A Online Question Bank

1. If the EA’-pin on the 8051 is strapped to Vcc, the following address ranges are on-
chip:
a) 0000h – 0FFFh X
b) 0000h – 1FFFh
c) 0000h – 2FFFh
d) 0000h – FFFFh

2. If you want to write data to Register Bank 2, you must use addresses:
a) 00h – 07h
b) 08h – 0Fh
cX) 10h – 17h X
d) 18h – 1Fh

3. If you want to write data to Register Bank 3, you must use addresses:
a) 00h – 07h
b) 08h – 0Fh
c) 10h – 17h
dX) 18h – 1Fh

4. If you want to use the bit-addressable RAM, the address range you must access
is:
a) 00h – 0Fh
b) 10h – 1Fh
cX) 20h – 2Fh
d) 30h – 3Fh

5. SFRs are only accessible by ____ mode of addressing.

aX) direct
b) indirect
c) both direct and indirect
d) neither direct or indirect

6 In the 8051, which register bank conflicts with the stack?

RB0
X) RB1
RB2
RB3

7. The registers of register banks (RBs) are accessed by _______ and _______
addressing, since the four RBs are mapped onto the lowest ____ bytes of the
internal data RAM.
a) Register, Index, 16
b) Direct, Indirect, 32 X
c) Immediate, Index, 32
d) None of the above
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8. What kind of PSW flags remain unaffected by the data transfer instructions?
a. Auxiliary Carry Flags
b. Overflow Flags
c. Parity Flags
d. All of the above X

9. . If 00h is decremented, it rolls back to ___h. Thus, to load 00h into a register,
would be the same as loading ______ value in decimal.
Answer: (FF)h, 256, respectively.
a) FFh, 255
b) FFh, 256 X
c) FFFFh, 255
d) FFFFh, 256

10. The mnemonic used to perform a subtraction of source with an 8-bit data, and
jumps to specified relative address if subtraction is non-zero, is given by:
a) CJE
b) CJNE X
c) CNE
d) JNE

SECTION B

Section B is a design question. Read the instructions carefully and complete the
question. You can make a drawing. Any drawing must be neat and tidy.

[20]

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1. Design a 4kByte external ROM memory by using 2kx4 ROM chips. Show the
design on the given diagram below.
2. Show how the ROMs should be connected to the 8051 by drawing the
connections on the same diagram.

Marks will be allocated as follows:

• Connections for VCC and GND on the 8051. (2)
• Data line labels. (2)
• Connections of the ROMs’ data lines to the data bus. (2)
• Connections of the data lines to the 8051 (via the bus). Use P1. (1)
• Correct number of address lines. (1)
• Address line labels. (1)
• Connections of the ROMS’ address lines to the address bus. (2)
• Connections of the address lines to the 8051 (via the bus). (2)
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• Connections for the Chip Select on both chips. (3)
• Crystal oscillator circuit (include all necessary components). (3)
• Connection for the EA’-pin (Vcc or GND). (1)

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 SECTION C

Section C is a programming question. [10]

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Test if a button was pressed. If it was, then an LED must switch on and stay on for
300ms. Use port 3 for the button and the LED.

Make R0 = 229 and R1 = 217. You have to calculate R2.

Complete the program by providing the answers in the Section C quiz.

Type the missing pieces of code to replace the letters (A-J) in the program given
below. Use CAPITAL letters.

ORG 0000H

;;;;;;;;;;;;;;; EQUATES ;;;;;;;;;;;;;;;

A ;Equate Port 3

;;;;;;;;;;;;;;; MAIN PROGRAM ;;;;;;;;;;;;;;;

MAIN: B ;Set P3.0 up as input

TEST: JNB C,MAIN ;Test pin 0 on Port 3

SETB P3.1 ;Set pin 1 on P1 to switch LED on

CALL D ;Jump to the label DELAY

CLR P3.0 ;Clear pin 1 on P1 to switch LED off

E ;Start again from the beginning

;;;;;;;;;;;;;;; 300ms DELAY SUBROUTINE ;;;;;;;;;;;;;;;

DELAY: F
G: MOV R1,#217
H: MOV R0,#229
I: DJNZ R0,LOOP1
DJNZ R1,LOOP2
DJNZ R2,LOOP3
J ;Return to instruction after CALL DELAY

END

END OF TEST

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TOTAL MARKS 50
©
UNISA
2022

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Appendix: MCS51 INSTRUCTION SET

2-loop: t = 1 + [(1+2.R0) + 2].R1 , 3-loop: t = 1 + (1 + [(1+2.R0) + 2].R1 + 2). R2

Mneumonic Byte Osc Mneumonic Byte Osc

Periods Periods
ADD A,Rn 1 12 MOV direct,A 2 12
ADD A,direct 2 12 MOV direct,Rn 2 24
ADD A,@Ri 1 12 MOV direct,direct 3 24
ADD A,#data 2 12 MOV direct,@Ri 2 24
ADDC A,Rn 1 12 MOV direct,#data 3 24
ADDC A,direct 2 12 MOV @Ri,A 1 12
ADDC A,@Ri 1 12 MOV @Ri,direct 2 24
ADDC A,#data 2 12 MOV @Ri,#data 2 12
SUBB A,Rn 1 12 MOV DPTR,#data16 3 24
SUBB A,direct 2 12 MOVC A,@A+DPTR 1 24
SUBB A,direct 1 12 MOVC A,@A+PC 1 24
SUBB A,#data 2 12 MOVX A,Ri 1 24
INC A 1 12 MOVX A,@DPTR 1 24
INC direct 2 12 MOVX @Ri,A 1 24
INC @Ri 1 12 MOVX @DPTR,A 1 24
DEC A 1 12 PUSH direct 2 24
DEC direct 2 12 POP direct 2 24
DEC @Ri 1 12 XCH A,Rn 1 12
INC DPTR 1 24 XCH A,direct 2 12
MUL AB 1 48 XCH A,@Ri 1 12
DIV AB 1 48 XCHD A,@Ri 1 12
DA A 1 12 CLR C 1 12
ANL A,Rn 1 12 CLR bit 2 12
ANL A,direct 2 12 SETB C 1 12
ANL A,@Ri 1 12 SETB bit 2 12
ANL A,#data 2 12 CPL C 1 12
ANL direct,A 2 12 CPL bit 2 12
ANL direct,#data 3 24 ANL C,bit 2 24
ORL A,Rn 1 12 ANL C,/bit 2 24
ORL A,direct 2 12 ORL C,bit 2 24
ORL A,@Ri 1 12 ORL C,/bit 2 24
ORL A,#data 2 12 MOV C,bit 2 12
ORL direct,A 2 12 MOV bit,C 2 12
ORL direct,#data 3 24 JC rel 2 24
XRL A,Rn 1 12 JNC rel 2 24
XRL A,direct 2 12 JB bit,rel 3 24
XRL A,@Ri 1 12 JNB bit,rel 3 24
XRL A,#data 2 12 JBC bit,rel 3 24
XRL direct,A 2 12 ACALL addr11 2 24
XRL direct,#data 3 24 LCALL addr16 3 24
CLR A 1 12 RET 1 24
CPL A 1 12 RETI 1 24
RL A 1 12 AJMP addr11 2 24
RLC A 1 12 LJMP addr16 3 24
RR A 1 12 SJMP rel 2 24
RRC A 1 12 JMP @A+DPTR 1 24
SWAP A 1 12 JZ rel 2 24
MOV A,Rn 1 12 JNZ rel 2 24
MOV A,direct 2 12 CJNE A,direct,rel 3 24
MOV A,@Ri 1 12 CJNE A,#data,rel 3 24
MOV A,#data 2 12 CJNE Rn,#data,rel 3 24
MOV Rn,A 1 12 CJNE @Ri,#data,rel 3 24
MOV Rn,direct 2 24 DJNZ Rn,rel 2 24
MOV Rn,#data 2 12 DJNZ direct,rel 3 24
MOV direct,A 2 12 NOP 1 12
A,#data,Rel (if A < #data then CY=1 else CY=0) CJNE A,direct,Rel (if A < direct) then CY=1 else CY=0)
CJNE Rn,#data,Rel (if A < #data) then CY=1 else CY=0

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