VII-SEM ECE: VLSI Design – 18EC72 (Module-5)

Module-5
Syllabus:
Semiconductor Memories: Introduction, Dynamic Random Access Memory
(DRAM) and Static Random Access Memory (SRAM)
(10.1 and 10.3 of TEXT1)
Testing and Verification: Introduction, Logic Verification Principals,
Manufacturing Test Principals, Design for Testability
(1 5 .1 , 1 5 . 3 , 1 5 . 5 , 1 5 .6 .1 t o 1 5 . 6 .3 o f T E X T 2 ) . L l, L 2

Introduction
 Semiconductor memory arrays capable of storing large quantities of digital
information are essential to all digital systems.
 The amount of memory required in a particular system depends on the type of
application.
 In general, the number of transistors utilized for the information (data) storage
function is much larger than the number of transistors used in logic operations
and for other purposes.
 Memory circuits are generally classified according to the type of data storage
and the type of data access.

 In ROMS, only the retrieval of previously stored data and it do not permit
modifications of the stored information contents during normal operation.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 ROMs are non-volatile memories, i.e., the data storage function is not lost even
when the power supply voltage is off.
 Read-write (R/W) memory circuits, permit the modification (writing) of data bits
stored in the memory array, as well as their retrieval (reading) on demand.
 Read-write (R/W) memory are volatile memories, i.e., the stored data are lost
when the power supply voltage is turned off.
 The read-write memory circuit is commonly called Random Access Memory
(RAM).

Typical random-access memory array organization

Figure 1: Typical random-access memory array organization

 A typical memory array organization is shown in figure 1.

 The data storage structure, consists of individual memory cells arranged in an
array of horizontal rows and vertical columns.
 Each cell is capable of storing one bit of binary information.
 Also, each memory cell shares a common connection with the other cells in the
same row, and another common connection with the other cells in the same
column.
 In this structure, there are 2 rows, also called word lines, and 2M columns, also
called bit lines. Thus, the total number of memory cells in this array is 2M x 2N.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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Design of Row and Column Decoders

 Consider circuit structures of row and column address decoders, which select a
particular memory location in the array, based on the binary row and column
addresses.
 A row decoder designed to drive a NOR ROM array must, by definition, select
one of the 2 word lines by raising its voltage to VOH. As an example, consider the
simple row address decoder shown in figure 2 which decodes a two-bit row
address and selects one out of four word lines by raising its level.

Figure 2: Row address decoder example for 2 address bits and 4 word lines

Read-Only Memory (ROM) Circuits

 The ROM produces a specified output value for each input combination, i.e., for
each address.
Example of a 4-bit x 4-bit NOR-based ROM array (Single address bits line)
 Consider 4-bit x 4-bit memory array shown in figure 2. Here, each column
consists of a pseudo-nMOS NOR gate driven by some of the row signals, i.e., the
word lines.

Figure 2: Example of a 4-bit x 4-bit NOR-based ROM array

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 Here only one word line is activated (selected) at a time by raising its voltage to
VDD, while all other rows are held at a low voltage level.
 If an active transistor exists at the cross point of a column and the selected row,
the column voltage is pulled down to the logic low level by that transistor.
 If no active transistor exists at the cross point, the column voltage is pulled
high by the pMOS load device. Thus, a logic "1"- bit is stored as the absence of
an active transistor, while a logic "0"- bit is stored as the presence of an active
transistor at the cross point.
 To reduce static power consumption, the pMOS load transistors in the ROM
array shown in figure 2 can also be driven by a periodic precharge signal,
resulting in a dynamic ROM.

Example of a 4-bit x 4-bit NAND-based ROM array (Single address bits line)

Figure 3: A 4-bit x 4-bit NAND-based ROM array.

 Here, each bit line consists of a depletion-load NAND gate, driven by some of
the row signals, i.e., the word lines.
 In normal operation, all word lines are held at the logic-high voltage level except
for the selected line, which is pulled down to logic-low level. If a transistor exists
at the cross point of a column and the selected row, that transistor is turned off
and the column voltage is pulled high by the load device.
 On the other hand, if no transistor exists (shorted) at that particular cross
point, the column voltage is pulled low by the other nMOS transistors in the
multi-input NAND structure.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 Thus, a logic "1" - bit is stored by the presence of a transistor that can be
deactivated, while a logic "0"-bit is stored by a shorted or normally on transistor
at the cross point.

Example of a 4-bit x 4-bit NOR-based ROM array (Double address bits line)
 A most straight forward implementation of this decoder is another NOR array,
consisting of 4 rows (outputs) and 4 columns (two address bits and their
complements).
 Note that this NOR-based decoder array can be built just like the NOR ROM
array, using the same selective programming approach (figure 5).
 The ROM array and its row decoder can thus be fabricated as two adjacent NOR
arrays, as shown in figure 6.

Figure 5: NOR-based row decoder circuit for 2 address bits and 4 word lines

Figure 6: Implementation of the row decoder circuit and the ROM array as two adjacent NOR
planes.

Static Read-Write Memory (SRAM) Circuits

 Read-write (R/W) memory circuits are designed to permit the modification
(writing) of data bits to be stored in the memory array, as well as their retrieval
(reading) on demand.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 The memory circuit is said to be static if the stored data can be retained
indefinitely (as long as a sufficient power supply voltage is provided), without
any need for a periodic refresh operation.
 The 1-bit memory cell in static RAM arrays, invariably consists of a simple latch
with two stable operating points (states).
 Depending on the preserved state of the two-inverter latch circuit, the data
being held in the memory cell will be interpreted either as a logic "0" or as a
logic "1."
 To access (read and write) the data contained in the memory cell via the bit line,
we need at least one switch, which is controlled by the corresponding word line,
i.e., the row address selection signal (figure 7(a)).
 Usually, two complementary access switches consisting of nMOS pass
transistors are implemented to connect the 1-bit SRAM cell to the
complementary bit lines (columns). This can be likened to turning the car
steering wheel with both left and right hands in complementary directions.

Figure 7: Various configurations of the static RAM cell. (a) Symbolic representation of the two-inverter
latch circuit with access switches. (b) Generic circuit topology of the MOS static RAM cell. (c) Resistive-
load SRAM cell. (d) Depletion-load nMOS SRAM cell. (e) Full CMOS SRAM cell.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 Figure 7(b) shows the generic structure of the MOS static RAM cell, consisting
of two cross-coupled inverters and two access transistors. The load devices may
be polysilicon resistors, depletion-type nMOS transistors, or pMOS transistors,
depending on the type of the memory cell. The pass gates acting as data access
switches are enhancement-type nMOS transistors.
 The use of resistive-load inverter with undoped polysilicon resistors in the latch
structure typically results in a significantly more compact cell size, compared
with the other alternatives (figure 7(c)).

The six-transistor depletion-load nMOS SRAM cell shown in figure 7(d) can be
easily implemented with one polysilicon and one metal layer, and the cell size
tends to be relatively small.
The full CMOS SRAM cell shown in figure 7(e) achieves the lowest static power
dissipation among the various circuit configurations presented here. In addition,
the CMOS cell offers superior noise margins and switching speed as well.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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Testing and Verification (Chapter-2)

CMOS IC test can be categorized into three main categories

1. Functionality tests or Logic verification:
 It verifies that the chip performs its intended function. These tests run before
tape-out to verify the functionality of the circuit.

2. Silicon debug:
 Silicon debug tests are run on the first batch of chips that return from
fabrication.
 These tests confirm that the chip operates as it was intended and help debug
any discrepancies.
 They can be much more extensive than the logic verification tests because the
chip can be tested at full speed in a system.
 For example, a new microprocessor can be placed in a prototype motherboard
to try to boot the operating system.
 This silicon debug requires creative detective work to locate the cause of failures
because the designer has much less visibility into the fabricated chip compared
to during design verification.

3. Manufacturing tests
 It verifies that every transistor, gate and storage element in the chip functions
correctly.
 These tests are conducted on each manufactured chip before shipping to the
customer to verify that the silicon is completely intact.

Testing a die (chip) can occur at the following levels:

 Wafer level
 Packaged chip level
 Board level
 System level
 Field level
Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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Logic Verification:
 Verification tests are usually the designer first choice that is constructed as
part of the design process.
 Verification tests is necessary to prove that a synthesized gate description was
functionally equivalent to the source RTL. This proves that RTL is equivalent to
the design specification at a higher behavioral or specification level of
abstraction.
 The behavioral specification might be a verbal description, a plain language
textual specification, a description in some high level computer language such
as C, a program in a system-modeling language such as System C, or a
hardware description language such as VHDL or Verilog, or simply a table of
inputs and required outputs.
 Often, designers will have a golden model in one of the previously mentioned
formats and this becomes the reference against which all other representations
are checked.
 Figure 8 shows functional equivalence at various levels of abstraction.

Figure 8: Functional equivalence at various levels of abstraction

Debugging
Many times, when a chip returns from fabrication, the first set of tests are run in a
lab environment, so you need to prepare for this event. You can begin by
constructing a circuit board that provides the following attributes:
Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 Power for the IC with ability to vary VDD and measure power dissipation.
 Real-world signal connections (i.e., analog and digital inputs and outputs as
required)
 Clock inputs as required (it is helpful to have a stable variable-frequency clock
generator)
 A digital interface to a PC (either serial or parallel ports for slow data or PCI bus
for fast data interchanges)

Manufacturing Tests
Whereas verification or functionality tests seek to confirm the function of a chip as
a whole, manufacturing tests are used to verify that every gate operates as
expected. Typical defects include the following:
o Layer-to-layer shorts (e.g., metal-to-metal)
o Discontinuous wires (e.g., metal thins when crossing vertical topology jumps)
o Missing or damaged vias
o Shorts through the thin gate oxide to the substrate or well
These in turn lead to particular circuit maladies, including the following:
o Nodes shorted to power or ground
o Nodes shorted to each other
o Inputs floating/outputs disconnected

Logic verification principles

Test vectors: Test vectors are a set of patterns applied to inputs and a set of
expected outputs. Both logic verification and manufacturing test require a good set
of test vectors. These must be large enough to catch all the logic errors and
manufacturing defects, yet small enough to keep test time (and cost) reasonable.

Test bench and Harnesses: A test bench or harness is a piece of HDL code that is
placed as a wrapper around a core piece of HDL (stimuli) to apply and check test
vectors. In the simplest test bench, input vectors are applied to the module under
test and at each cycle, the outputs are examined to determine whether they are

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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same as predefined expected data set. The expected outputs can be derived from
the golden model and saved as a file or the value.

Regression Test: High-level language scripts are frequently used when running
large test benches, especially for regression testing. Regression testing involves
performing a suite of simulations to automatically verify that no functionality has
inadvertently changed in a module or set of modules. During a design, it is
common practice to run a regression script every night after design activities have
concluded to check that bug fixes or feature enhancements have not broken
completed modules

Bug Tracking: Another important tool to use during verification is a bug-tracking

system. Bug-tracking systems such as the Unix/Linux based GNATS (is a set of
tools for tracking tools) allow the management of a wide variety of bugs. In these
systems, each bug is entered and the location, nature, and severity of the bug is
noted.

Manufacturing Test Principles:

A critical factor in VLSI design is the necessity to incorporate methods of testing
circuits. This task should proceed concurrently with architectural considerations
and not be left until fabricated parts are available.

Figure 9: The combinational explosion in test vectors

 The Above figure 9(a) shows a combinational circuit with N inputs. To test this
circuit exhaustively, a sequence of 2N inputs (or test vectors) must be applied
and observed to fully exercise the circuit.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 This combinational circuit is converted to a sequential circuit with addition of M

registers, as shown in figure 9(b).
 The state of the circuit is determined by the inputs and the previous state. A
minimum of 2(N+M) test vectors must be applied to exhaustively test the circuit.

Fault Models
A model for how faults occur and their impact on circuits is called a fault module.
A fault model for every circuit is proposed before actual testing.
Two popular fault models are:
1. Stuck-At model
2. Short Circuit/Open Circuit model
1. Stuck-At faults:
 In the Stuck-At model, a faulty
gate input is modeled as a stuck at
zero (Stuck-At-0, S-A-0) or stuck
at one (Stuck-At-l, S-A-l).
 This model dates from board-level
designs, where it was determined
to be adequate for modelling
faults.
 Figure illustrates how an S-A-0 or S-A-1 fault might occur. These faults most
frequently occur due to gate oxide shorts (the nMOS gate to GND or the pMOS
gate to VDD) or metal-to-metal shorts.

2. Short-Circuit and Open-Circuit Faults

Short-Circuit fault:
From the above figure it can be seen that, the short
S1 results in an S-A-0 fault at input A, while short S2
results in a output node shorted with drain terminal
of C and D, irrespective of input combination the
output results in error due to these shorts.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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Open-Circuit Faults

Figure shows 2-input NOR gate implementation in CMOS logic. If nMOS transistor
A is stuck open, then the function displayed by the gate will be Z  A  B  BZ' ,
where Z’ is the previous state of the gate.

Observability
 Observability is a degree to which it can be observed that node at outputs
operates correctly.
 Observability is useful, when a test engineer has to measure the output of a
gate/chip within a larger circuit to check its correct operation.
 Higher Observability indicates less number of cycles required to measure
output node value.

Controllability
 Controllability is the ability of an internal circuit within a chip the ease of
setting the node to logic ‘1’ or logic ‘0’ state.
 Controllability is important while accessing the degree of difficulty of testing a
particular signal in a circuit.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 A node with little controllability may take hundreds of cycles to get it to the
right state.

Fault Coverage
 Ideally testing involves detecting all possible faults in a Device Under Test
(DUT). The extent of testing decides the percentage of faults that can be
detected. Detection of all possible faults in a DUT corresponds to 100 % test
coverage.
 Fault coverage is defined as the percentage of fault that can be detected by the
applied test vectors. Fault coverage gives a measure of goodness of a test
program. High fault coverage is desirable during manufacture test. Design For
Testability (DFT) is used to improve the fault coverage.

Steps to find Fault Coverage

 Each circuit node is held to logic ‘0’ (S-A-0) one by one.
 The output of chip is compared with “good machine”
 If the output is deviated, then the machine is marked as “fault machine”
 Repeat the above step by setting the circuit node to logic ‘1’ (S-A-1).
 Fault coverage in percentage is given as:

Number of faults det ected

% Fault Coverage =
Total nodes in the circuit

Automatic Test Pattern Generation (ATPG)

 Historically, in the IC industry, logic and circuit designers implemented the
functions at the RTL or schematic level, mask designers completed the layout,
and test engineers wrote the tests.
 For the longest time, test engineers requested to circuit designers to include
extra circuitry to reduce the burden of test generation.
 As density of the chips increased in complexity, the inclusion of test circuitry
finds difficulty for the designer.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 To deal with this burden, Automatic Test Pattern Generation (ATPG) methods
have been invented.
 The use of some form of ATPG is standard for most digital designs.
 This ATPG tools can achieve excellent fault coverage.
 Some ATPG tools use statistical algorithms to predict the fault coverage of a set
of vectors without performing as much simulation.
 Scan based and Built-In Self-Test (BIST) are the popular ATPG, which reduce
the number of test vectors required to achieve a desired fault coverage.

Delay Fault Testing

 Failures that occur in CMOS could leave the functionality of the circuit
untouched, but affect the timing.
 For instance, consider the layout shown in Figure for an inverter gate composed
of paralleled nMOS and pMOS transistors.
 If an open circuit occurs in one of the nMOS transistor source connections to
GND, then the gate would still function but with increased delay fault timing
(tpdf).
 Delay faults may be caused by crosstalk.
 Delay faults can also occur more often in SOI logic through the history effect.

Design for Testability

Design for testability may be categorized as follows:
1. Ad hoc testing
2. Scan-based approaches
3. Built-in self-test (BIST)
Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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1. Ad hoc testing
 Ad hoc test techniques, as their name suggests, are collections of ideas aimed at
reducing the combinational explosion of testing.
 They are only useful for small designs where scan, ATPG, and BIST are not
available.
 A complete scan-based testing methodology is recommended for all digital
circuits.
 The following are common techniques for ad hoc testing:
 Partitioning large sequential circuits
 Adding test points
 Adding multiplexers
 Providing for easy state reset

2. Scan Design
The scan technique is a structured approach to designing sequential circuit for
testability. The storage cells in registers are used as observation points, control
points or both.
The scan path technique consists in connecting together all the storage
elements to form a long serial shift register. These storage elements can be D, JK
or SR flip flops.
The selection of the input source is achieved using a multiplexer on the data
input controlled by an external mode signal. The sequential circuit has two modes
of operation. There are Test Mode and Normal Mode.
In Test Mode: The scan-in signal is clocked into scan path and output of last
storage is scanned out.
In Normal Mode: The scan in path is disabled and circuit functions as a sequential
circuit.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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The method of testing a circuit with the scan path is as follows:

1. Set test mode signal, flip-flops accept data from scan-in input.
2. Verify the scan path by shifting in and out test data.
3. Set the shift register to an initial state.
4. Apply a test pattern to the primary inputs of the circuit.
5. Set normal mode, the circuit settles and can monitor the primary outputs of the
circuit.
6. Activate the circuit clock for one cycle.
7. Return to test mode; Scan out the contents of the registers, simultaneously scan
in the next pattern.
8. Repeat testing steps 3 to 7 until all test patterns are applied.

Built–In Self-Test (BIST):

 Built-in test techniques, as their names suggest, rely on augmenting
(additional) circuits to allow them to perform operations upon themselves that
prove correct operation. These techniques add area to the chip for the test logic,
but reduce the test time required and thus can lower the overall system cost.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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 The structure of BIST is shown below.

 One method of testing a module is to use ‘signature analysis’ or ‘cyclic

redundancy checking’. This involves using a pseudo-random sequence
generator to produce the input signals for a section of combinational
circuitry and a signature analyzer to observe the output signals.
 A PRSG of length n is constructed from a linear feedback shift register
(LFSR), which in turn is made of n flip-flops connected in a serial fashion.
 The XOR of particular outputs are fed back to the input of the LFSR. An n-
bit LFSR will cycle through 2n–1 states before repeating the sequence. One
problem seen is that it is not possible to generate pattern with all 0’s.

Figure 10: Pseudo-random sequence generator

 A complete feedback shift register (CFSR), shown in Fig, includes the zero state
that may be required in some test situations. An n-bit LFSR is converted to an
n-bit CFSR by adding an n – 1 input NOR gate connected to all but the last bit.
When in state 0…01, the next state is 0…00.
 A signature analyzer receives successive outputs of a combinational logic block
and produces a syndrome that is a function of these outputs. The syndrome is
reset to 0, and then XORed with the output on each cycle.
 The syndrome is present in each cycle so that a fault in one bit is unlikely to
cancel itself out. At the end of a test sequence, the LFSR contains the syndrome
that is a function of all previous outputs. This can be compared with the correct

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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syndrome (derived by running a test program on the good logic) to determine

whether the circuit is good or bad.

BILBO–Built-In Logic Block Observation:

 The combination of signature analysis and the scan technique is the formation
of BILBO.
 The 3-bit BIST register shown in Fig is a scannable, resettable register that also
can serve as a pattern generator and signature analyzer.
 This structure can operate in different mode as shown in table below.

 In the reset mode (10), all the flip-flops are synchronously initialized to 0. In
normal mode (11), the flip-flops behave normally with their D input and Q
output. In scan mode (00), the flip-flops are configured as a 3-bit shift register
between SI and SO. In test mode (01), the register behaves as a pseudo-random
sequence generator or signature analyzer.

Figure 11: 3-bit register BIST

 In summary, BIST is performed by first resetting the syndrome in the output
register. Then both registers are placed in the test mode to produce the pseudo-
random inputs and calculate the syndrome. Finally, the syndrome is shifted out
through the scan chain.

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Memory BIST:
On many chips, memories involves with majority of the transistors. A robust
testing methodology must be applied to provide reliable parts. In a typical
MBIST scheme, multiplexers are placed on the address, data, and control
inputs for the memory to allow direct access during test. During testing, a state
machine uses these multiplexers to directly write a checkerboard pattern of
alternating 1s and 0s. The data is read back, checked, then the inverse pattern
is also applied and checked. ROM testing is even simpler: The contents are read
out to a signature analyzer to produce a syndrome.

Dr. Praveen J, IQAC Director, Professor & Head, Dept. of ECE, GMIT, Davangere
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