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B.Tech IT Exam: Computer Architecture

This document is an exam for a Computer Organization and Architecture course. It contains 6 questions testing various topics: 1) Machine instructions and addressing modes 2) Integer and floating point number representations 3) Memory access and control unit design 4) Memory and cache design 5) I/O and interrupt handling 6) Pipeline processor design and hazards The questions require explaining concepts, providing examples, completing calculations, and designing components like memory systems.

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118 views3 pages

B.Tech IT Exam: Computer Architecture

This document is an exam for a Computer Organization and Architecture course. It contains 6 questions testing various topics: 1) Machine instructions and addressing modes 2) Integer and floating point number representations 3) Memory access and control unit design 4) Memory and cache design 5) I/O and interrupt handling 6) Pipeline processor design and hazards The questions require explaining concepts, providing examples, completing calculations, and designing components like memory systems.

Uploaded by

coolshubupaunikar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Course Code : ITT 256 QVRU/RS – 22 / 1201

Fourth Semester B. Tech. ( Information Technology ) Examination

COMPUTER ORGANIZATION AND ARCHITECTURE

Time : 3 Hours ] [ Max. Marks : 60

Instructions to Candidates :—
(1) All questions carry marks as indicated against them.
(2) Assume suitable data and illustrate answers with neat sketches wherever necessary.

1. (a) Write zero address, one address, two address and three address machine
instruction for following expression :—
Z = (A + B) y (C – D + E) / (A + D). 3 (CO 1)

(b) Explain Big Endian and Little Endian assignments. Show memory contents
after storing "HELLO" by both these methods. 3 (CO 1)

(c) State and Explain the necessity of the different addressing modes with the
help of example. 4 (CO 1)

2. (a) Write the non-restoring integer division algorithm. Also draw the necessary
circuit arrangement for the same and solve 11/3. 4 (CO 2)

(b) Solve by using Booth's multiplication algorithm multiplicand = –1110,


multiplier = 1010. 3 (CO 2)

(c) Explain IEEE 754 Double precision floating point number representation.
3 (CO 2)

3. (a) Why the wait for memory function is completed step needed when reading
from or writing to the memory ? In which clock cycle this signal is initiated
for read and write ? 2 (CO 3)

QVRU/RS-22 / 1201 Contd.


(b) What are the advantages and disadvantages of Hardwired and Micro programmed
control ? 4 (CO 3)

(c) Write the sequence of control steps required for single bus architecture for
each instruction given below :

(i) Add the contents of the memory location whose address is


at memory location N to register R1.

(ii) Move the contents of memory location N1 to R4. 4 (CO 3)

4. (a) Design a 64K x 16 memory, using 16K x 8 Static RAM chip. 4 (CO 4)

(b) Distinguish between write - through and write - back approaches in the context
of cache memory and compare their pros and cons. 2 (CO 4)

(c) Cache has 64 KB capacity 128 byte lines and is 4 way set associative.
The system containing the cache uses 32 bit addresses :—

(i) How many lines and sets does the cache have ?

(ii) How many entries are required in tag array ?

(iii) How many bits of tag are required in each entry in the tag
array ?

(iv) How is 32 bit address divided into different fields ?


4 (CO 4)

5. (a) Explain direct memory access, state the interactions between the CPU,
the DMA controller and the IO device with the help of diagram.
4 (CO 5)

(b) Describe I/O mapped I/O and Memory mapped I/O. 3 (CO 5)

(c) Write short note on interrupt handling of multiple devices. 3 (CO 5)

QVRU/RS-22 / 1201 2 Contd.


6. (a) Consider a 4 stage pipeline processor. The number of cycles needed by
the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown
below :
S1 S2 S3 S4
I1 2 1 1 1
I2 1 3 2 2
I3 2 1 1 3
I4 1 2 2 2
What is the number of cycles needed to execute the following loop and
also draw the timing diagram ?
For (i = 2 to 2) {I1 ; I2 ; I3 ; I4 ;} 3 (CO 6)
(b) What are important goals in designing a pipelined processor ? What are
Hazards in the context of pipelining ? Explain any one of them with an
example. 4 (CO 6)
(c) How cache memory and interstage buffer affects the performance of pipeline
processor ? 3 (CO 6)

QVRU/RS-22 / 1201 3 75

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