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VHDL Testbench for Logic Circuit

The document describes a testbench for testing a component with 4 inputs and 1 output using 12 test cases. It connects the component, assigns values to the inputs, waits for 10ns, and checks if the output is the expected value for each case. It counts any errors and reports the test result at the end.

Uploaded by

Chúc Văn Kiên
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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31 views3 pages

VHDL Testbench for Logic Circuit

The document describes a testbench for testing a component with 4 inputs and 1 output using 12 test cases. It connects the component, assigns values to the inputs, waits for 10ns, and checks if the output is the expected value for each case. It counts any errors and reports the test result at the end.

Uploaded by

Chúc Văn Kiên
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

Library IEEE;

Use IEEE.STD_logic_1164.All;
Entity test12_tb is

End test12_tb;

Architecture ktra of test12_tb is


Component test12
Port (
x3,x2,x1,x0: IN std_logic;
F : OUT std_logic
);
End Component;
Signal X3,X2,X1,X0,F : std_logic ;
Begin
DUT: test12 Port Map ( X3,X2,X1,X0,F );
Process
Variable err_cnt: integer := 0;
Begin
-- Test case 0
X3 <= '0';
X2 <= '0';
X1 <= '0';
X0 <= '0';
Wait for 10 ns;
assert (F='0')
report "Failed Case1!" severity error;
if (F='1') then
err_cnt := err_cnt +1;
end if;
-- Test case 1
X3 <= '0';
X2 <= '0';
X1 <= '0';
X0 <= '1';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 2
X3 <= '0';
X2 <= '0';
X1 <= '1';
X0 <= '0';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 3
X3 <= '0';
X2 <= '0';
X1 <= '1';
X0 <= '1';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 4
X3 <= '0';
X2 <= '1';
X1 <= '0';
X0 <= '0';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 6
X3 <= '0';
X2 <= '1';
X1 <= '1';
X0 <= '0';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 7
X3 <= '0';
X2 <= '1';
X1 <= '1';
X0 <= '1';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 9
X3 <= '1';
X2 <= '0';
X1 <= '0';
X0 <= '1';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 10
X3 <= '1';
X2 <= '0';
X1 <= '1';
X0 <= '0';
wait for 10 ns;
assert (F='1')
report "Failed Case1!" severity error;
if (F='0') then
err_cnt := err_cnt +1;
end if;
-- Test case 11
X3 <= '1';
X2 <= '0';
X1 <= '1';
X0 <= '1';
wait for 10 ns;
assert (F='0')
report "Failed Case1!" severity error;
if (F='1') then
err_cnt := err_cnt +1;
end if;
-- Test case 12
X3 <= '1';
X2 <= '1';
X1 <= '0';
X0 <= '0';
wait for 10 ns;
assert (F='0')
report "Failed Case1!" severity error;
if (F='1') then
err_cnt := err_cnt +1;
end if;
-- summary of all the tests to see if any errors
if (err_cnt=0) then
assert false report "Testbench completed successfully!"
severity note;
else
assert true
report "Something wrong, try again pls!"
severity error;
end if;
wait; -- stop running
end process;
End Ktra;

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