Operating
Systems:
Internals Chapter 1
and Design
Principles Computer System
Overview
BALOYI VR
Operating System
Exploits
the hardware resources of one or more
processors
Provides a set of services to system users
Manages secondary memory and I/O devices
Basic Elements
I/O
Processor Modules
Main System
Memory Bus
Processor
Controls the Performs the
operation of the data processing
computer functions
Referred to as
the Central
Processing Unit
(CPU)
Main Memory
Volatile
Contents of the memory is
lost when the computer is
shut down
Referred to as real memory
or primary memory
I/O Modules
storage (e.g. hard
drive)
Moves data
between the
computer and communications
external equipment
environments
such as:
terminals
System Bus
Provides for
communication among
processors, main memory,
and I/O modules
Top-Level
View
Graphical Processing
Units (GPU’s)
Provide efficient computation on arrays
of data using Single-Instruction Multiple
Data (SIMD) techniques
Used for general numerical processing
Physics simulations for games
Computations on large spreadsheets
Digital Signal Processors
(DSPs)
Deal with streaming signals such as
audio or video
Used to be embedded in devices like
modems
Encoding/decoding speech and video
(codecs)
Support for encryption and security
Instruction Execution
A program consists of a set of instructions
stored in memory
Two steps:
• processor reads (fetches)
instructions from memory
• processor executes each
instruction
Basic Instruction Cycle
The processor fetches
the instruction from
memory
Program counter
(PC) holds address of
the instruction to be
fetched next
PC is
incremented after
each fetch
Instruction Register (IR)
Fetched instruction is Processor interprets the
loaded into Instruction instruction and performs
Register (IR) required action:
Processor-memory
Processor-I/O
Data processing
Control
Characteristics of a
Hypothetical Machine
Example of
Program
Execution
Interrupts
Interrupt the normal sequencing of the
processor
Provided to improve processor utilization
most I/O devices are slower than the processor
processor must pause to wait for device
wasteful use of the processor
Common Classes
of Interrupts
Flow of Control
Without
Interrupts
Interrupts:
Short I/O Wait
Instruction Cycle With Interrupts
Multiple Interrupts
An interrupt occurs
while another interrupt Two approaches:
is being processed
• e.g. receiving data • disable interrupts
from a while an interrupt is
communications line being processed
and printing results at • use a priority scheme
the same time
Transfer of Control With
Multiple Interrupts:
Transfer of Control With
Multiple Interrupts:
Memory Hierarchy
Major constraints in memory
amount
speed
expense
Memory must be able to keep up with the processor
Cost of memory must be reasonable in relationship
to the other components
Memory Relationships
Greater capacity
= smaller cost per
bit
Faster Greater
access time capacity =
= greater slower access
cost per bit speed
The Memory Hierarchy
Going down the
hierarchy:
decreasing cost per bit
increasing capacity
increasing access time
decreasing frequency of
access to the memory by
the processor
Secondary
Memory
Also referred to
as auxiliary
memory
• External
• Nonvolatile
• Used to store
program and data
files
Invisible to the OS
Interacts with other memory management hardware
Processor must access memory at least once per instruction
cycle
Processor execution is limited by memory cycle time
Exploit the principle of locality with a small, fast memory
Contains a copy of a portion of main memory
Processor first checks cache
If not found, a block of memory is read into cache
Because of locality of reference, it is likely that many of the
future memory references will be to other bytes in the block
Cache and
Main
Memory
Cache Read
Operation
cache size
number of
cache block size
levels
Main
categories
are:
write mapping
policy function
replacement
algorithm
Cache and Block Size
Cache Size
Block
Size
The unit of data
Small caches have
exchanged
significant impact
between cache and
on performance
main memory
Mapping Function
∗ Determines which cache
location the block will occupy
When one block is read
in, another may have to be
replaced
Two constraints affect
design:
The more flexible the
mapping function, the
more complex is the
circuitry required to
search the cache
Replacement Algorithm
Least Recently Used (LRU) Algorithm
effective strategy is to replace a block that has been
in the cache the longest with no references to it
hardware mechanisms are needed to identify the
least recently used block
chooses which block to replace when a new block is
to be loaded into the cache
I/O Techniques
Three techniques are possible for I/O
operations:
Programmed Interrupt- Direct Memory
I/O Driven I/O Access (DMA)
Programmed I/O
The I/O module performs the requested action
then sets the appropriate bits in the I/O status
register
Theprocessor periodically checks the status of the
I/O module until it determines the instruction is
complete
With programmed I/O the performance level of
the entire system is severely degraded
Interrupt-Driven I/O
Processor
issues an I/O The processor
command to a executes the
module and data transfer
then goes on and then
to do some resumes its
other useful former
work processing
The I/O module will More efficient than
then interrupt the Programmed I/O but
processor to request still requires active
service when it is intervention of the
ready to exchange processor to transfer
data with the data between memory
processor and an I/O module
Interrupt-Driven I/O
Drawbacks
Transfer
rate is limited by the speed with
which the processor can test and service a
device
The processor is tied up in managing an I/O
transfer
a number of instructions must be
executed for each I/O transfer
Direct Memory Access
(DMA)
∗ Performed by a separate module on the system bus or
incorporated into an I/O module
When the processor wishes to read or write data it
issues a command to the DMA module containing:
• whether a read or write is requested
• the address of the I/O device involved
• the starting location in memory to read/write
• the number of words to be read/written
Transfersthe entire block of data directly to
and from memory without going through the
processor
processor is involved only at the beginning and end of the
transfer
processor executes more slowly during a transfer when
processor access to the bus is required
More efficient than interrupt-driven or
programmed I/O
Symmetric Multiprocessors
(SMP)
A stand-alone computer system with the
following characteristics:
two or more similar processors of comparable capability
processors share the same main memory and are
interconnected by a bus or other internal connection scheme
processors share access to I/O devices
all processors can perform the same functions
the system is controlled by an integrated operating system
that provides interaction between processors and their
programs at the job, task, file, and data element levels
Performance Scaling
• a system with multiple • vendors can offer a range of
processors will yield greater products with different price
performance if work can be and performance
done in parallel characteristics
Availability Incremental Growth
• the failure of a single • an additional processor can
processor does not halt the be added to enhance
machine performance
SMP Organization
Figure 1.19 Symmetric Multiprocessor Organization
Multicore Computer
Also known as a chip multiprocessor
Combines two or more processors (cores) on a
single piece of silicon (die)
each core consists of all of the components of an
independent processor
Inaddition, multicore chips also include L2
cache and in some cases L3 cache
Summary
Basic Elements
processor, main memory, I/O modules, system
bus
GPUs, SIMD, DSPs, SoC
Instruction execution
processor-memory, processor-I/O, data processing,
control
Interrupt/Interrupt Processing
Memory Hierarchy
Cache/cache principles and designs
Multiprocessor/multicore
