ECE4680 Computer Organization and Architecture Memory Hierarchy
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The Big Picture: Where are We Now?
The Five Classic Components of a Computer
Processor Input Control Memory Datapath
Output
Todays Topic: Memory System
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Who Cares About the Memory Hierarchy?
Processor-DRAM Memory Gap (latency)
1000
Proc 60%/yr. (2X/1.5yr)
CPU
Moores Law Performance
100
Processor-Memory Performance Gap: (grows 50% / year) DRAM 9%/yr. (2X/10 yrs)
10
DRAM
1
1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002
Time
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An Expanded View of the Memory System
Processor Control Memory Memory Memory Memory Datapath Memory
Speed: Fastest Size: Smallest Cost: Highest
Slowest Biggest Lowest
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Memory Hierarchy: Principles of Operation
At any given time, data is copied between only 2 adjacent levels: Upper Level: the one closer to the processor - Smaller, faster, and uses more expensive technology Lower Level: the one further away from the processor Bigger, slower, and uses less expensive technology
Block: The minimum unit of information that can either be present or not present in the two level hierarchy
To Processor
Upper Level Memory
Blk X
Lower Level Memory
From Processor
Blk Y
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Memory Hierarchy: Terminology
Hit: data appears in some block in the upper level (example: Block X) Hit Rate: the fraction of memory access found in the upper level Hit Time: Time to access the upper level which consists of RAM access time + Time to determine hit/miss Miss: data needs to be retrieve from a block in the lower level (Block Y) Miss Rate = 1 - (Hit Rate) Miss Penalty: Time to replace a block in the upper level + Time to deliver the block to the processor Hit Time << Miss Penalty
Lower Level Memory
To Processor
Upper Level Memory
Block X
From Processor
Block Y
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Memory Hierarchy: How Does it Work?
Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon. Keep more recently accessed data items closer to the processor Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon. Move blocks consists of contiguous words to the upper levels
To Processor
Upper Level Memory
Blk X
Lower Level Memory
From Processor
Blk Y
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Memory Hierarchy of a Modern Computer System
By taking advantage of the principle of locality: Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology.
Processor Control Second Level Cache (SRAM) Main Memory (DRAM) Secondary Storage (Disk)
On-Chip Cache
Registers
Datapath
Speed (ns): 1s Size (bytes): 100s
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10s Ks
100s Ms
10,000,000s (10s ms) Gs
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Memory Hierarchy Technology
Random Access: Random is good: access time is the same for all locations DRAM: Dynamic Random Access Memory - High density, low power, cheap, slow - Dynamic: need to be refreshed regularly SRAM: Static Random Access Memory Low density, high power, expensive, fast Static: content will last forever
Non-so-random Access Technology: Access time varies from location to location and from time to time Examples: Disk, tape drive, CDROM The next two lectures will concentrate on random access technology The Main Memory: DRAMs Caches: SRAMs
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Technology Trends
Capacity Logic: 2x in 3 years DRAM: 4x in 3 years Disk: 4x in 3 years Speed (latency) 2x in 3 years 2x in 10 years 2x in 10 years DRAM Year 1980 1983 1986 1989 1992 1995
1000:1!
Size 64 Kb 256 Kb 1 Mb 4 Mb 16 Mb 64 Mb
2:1!
Cycle Time 250 ns 220 ns 190 ns 165 ns 145 ns 120 ns
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SPARCstation 20s Memory System Overview
Memory Controller
Memory Bus (SIMM Bus) 128-bit wide datapath Memory Module 5 Memory Module 7 Memory Module 4 Memory Module 3 Memory Module 6 Memory Module 2 Memory Module 1 Memory Module 0
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Processor Bus (Mbus) 64-bit wide
Processor Module (Mbus Module) SuperSPARC Processor External Cache Instruction Cache Data Cache
Register File
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SPARCstation 20s Memory Module
Supports a wide range of sizes: Smallest: 4 MB = 16 2Mb DRAM chips, 8 KB of Page Mode SRAM Biggest: 64 MB = 32 16Mb chips, 16 KB of Page Mode SRAM
DRAM Chip 15 512 cols 256K x 8 = 2 MB
DRAM Chip 0 512 rows 256K x 8 = 2 Mb
One page
512 8 SRAM 8 bits bits<127:0>
512 8 SRAM bits<7:0> Memory Bus<127:0>
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Summary:
Two Different Types of Locality: Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon. Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon. By taking advantage of the principle of locality: Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology. DRAM is slow but cheap and dense: Good choice for presenting the user with a BIG memory system SRAM is fast but expensive and not very dense: Good choice for providing the user FAST access time.
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