Proceedings of the 50th European Microwave Conference

A High Efficiency Compact Class F GaN MMIC

Power Amplifier for 5G Applications
Rachit Joshi1, Min-Hsin Liu, Shawn S. H. Hsu2
Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan
1
rachitjoshi23@[Link], 2shhsu@[Link]

Abstract — A high performance compact MMIC class F Semiconductor, aiming for 5G small cell applications. A high
power amplifier is demonstrated for 5G small cell applications by efficiency, high output power, and wide BW MMIC is
a 0.25-μm Gallium Nitride (GaN) High Electron Mobility demonstrated.
Transistor (HEMT) technology. Both the 2nd and 3rd harmonic
VDD
terminations are considered in the output matching network, and
optimized utilizing the backside via parasitic inductance. Also, RF short Even harmonic
the device drain-source parasitic capacitance is considered short (λ/4)
together into the matching circuit for improving the bandwidth
and high frequency operation. The measured peak output power Input Series LC at RFout
Pout of the amplifier is 36.6 dBm at 6 GHz. Also, the measured matching fundamental Z= 50Ω
peak power-added-efficiency (PAE) at a 1.5 dB gain compression RFin
is 65.8 %. Also, the measured 3-dB bandwidth is 1800 MHz. The Z= 50Ω
design has a chip size of only 2.56 mm2.
Keywords — Gallium Nitride (GaN), MMIC, class F, power
amplifier, PAE, 5G communications. Fig. 1. A typical class F PA topology.

I. INTRODUCTION II. CIRCUIT DESIGN AND ANALYSIS

Efficiency of a power amplifier (PA) is a critical parameter Fig. 2 shows the proposed class F power amplifier,
for 5G transmitter operation, which is the most power hungry including input/output matching network (IMN/OMN) for
block in the system front end. Also, the need for a compact PA both fundamental tone and harmonics, stability network, and
design becomes a significant factor for the small cells in 5G also the intrinsic device is highlighted. Note that CDS is mainly
applications. Another important design consideration is the contributed from the capacitance coupling between drain and
bandwidth (BW). With an increased BW of the PA, more source through the substrate, and LD is introduced by the drain
different wireless communication standards could be fingers and interconnect in the layout. The TL with different
accommodated, which allows simplifying the transmitter characteristic impedances together with the metal-insulator-
design [1], [2]. With the superior material properties of GaN metal (MIM) capacitors and the inductance of backside via
such as wide bandgap and high saturation velocity under a LBvia are employed for the fundamental and harmonic
large electrical field, the GaN-based MMIC is an excellent matching/termination networks, and no spiral inductors are
candidate for the 5G applications [3], [4]. used. To achieve a proper class F operation, the device is
The class F power amplifier is a widely used topology for biased at deep class AB. Also, the amplifier is optimized to
various such applications. Fig. 1 shows the basic concept of achieve high output power and PAE simultaneously.
class F PA design [5], which can achieve a theoretical 100% The IMN consists of two cascaded L-Type networks
efficiency by using a quarter-wave transmission line (TL) to including a series transmission line TL1 and a shunt short
short circuit the even harmonics and provide high impedance circuit stub TL2, and also the MIM capacitors C1 and C2 form
to the odd harmonics, and with the series LC network the other L network, which allows a wideband operation. The
resonating at the fundamental tone for the output power. stability network in the proposed design consists of two sets of
Different approaches have been proposed to realize high RC networks, namely, the RSP-CSP connected in parallel to the
performance class F PAs [6]-[8]. However, challenges still signal path and the RSS-CSS connected in series to the gate of
transistor. We employ both types of stability networks to
remain such as the efficiency and chip size owning to the
ensure the circuit stability.
relatively complicated output network with high order
It is critical to select the size of power cell for the targeted
harmonic terminations. In addition, the device parasitics could
output power level of the proposed class F PA, which is about
seriously degrade the PA performance if not considered 4-5 W (36-37 dBm) in this design for 5G small cell
properly, especially the large output capacitance of the power applications. The adopted 0.25 μm GaN technology (WIN
transistor. In this paper, a class F MMIC power amplifier is
Semiconductors) is fabricated on a 4 mil (100 μm) thick SiC
presented with both second and third harmonic terminations substrate with the nominal maximum drain current density
using a 0.25 μm GaN HEMT technology provided by WIN and transconductance of 1040 mA/mm and 390 mS/mm,

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 VDD
CB

VG C0
CB
Intrinsic Extrinsic
plane plane TL4
ZIN C0
RFout
TL2 Z= 50Ω
LD TL3
RFin RSS
Z= 50Ω C1 TL1 TL6 C3
TL5
CDS CSH
TL7
RSP Intrinsic
C2 CSS Backside Via
GaN LBvia
Inductance
CSP device

Fig. 2. Circuit topology of the proposed class F PA.

respectively. The suggested drain bias voltage is 28 V. The high characteristic impedance (~ 70 Ω) and two small shunt
power cell selected in the amplifiers is 4×200 μm (4 fingers) capacitors C0 (~ 0.2 pF). The circuit size can be effectively
with the corresponding fT/fmax of ~ 30/70 GHz. The load-pull reduced.
simulation under ~ 2.5 dB gain compression is The second harmonic short is realized by the shunt branch
performed to find the impedance point for simultaneously TL5, CSH, and LBvia, where LBvia is obtained from the inductance
achieving high PAE and output power. Fig. 3(a) shows the of the backside via directly. Fig. 4 (a) shows the 3D plot of the
simulated matching trajectories from 3 to 20 GHz based on the standard backside via available in the adopted 0.25-μm GaN
selected transistor size under the designed bias point at the technology, which is surrounded by the SiC substrate with an
device intrinsic and extrinsic planes respectively, as illustrated oval shape (60 μm × 30 μm) and a height of 100 μm. The via
in Fig. 2. Note that the extrinsic plane is the output terminals is a hollow cylinder with a sidewall of ~ 4 μm gold. The full-
of the transistor, where it interfaces with the output matching wave EM simulation as shown in Fig. 4 (b) indicates that the
network. On the other hand, the intrinsic plane is a backside via can provide a relatively small but stable
nonphysical plane separating the voltage-controlled current inductance with a high quality factor over a broad frequency
source in the equivalent circuit model from the device range, almost acting as a pure 3-dimensional inductor, which
parasitics such as CDS and LD, as explained in [5]. As can be cannot be obtained by a typical microstrip line or spiral
seen, the simulated optimal impedance points for the 2nd and inductor. A wideband inductance LBvia of ~ 32 pH from 3 to 30
3rd harmonics are very close to short and open respectively GHz can be obtained with the Q factor up to ~ 60 at 18 GHz.
when referred back at the device intrinsic plane, which is The LBvia is co-designed with TL5 and CSH for improved
consistent with the theory prediction for achieving the optimal harmonic termination of the class F PA.
performance of class F PA. Fig. 3(b) shows the simulated The third harmonic impedance optimization is achieved by
waveforms of the amplifier using the harmonic terminations the combination of LC shunt filter (TL5, CSH, and LBvia) and
shown in Fig. 3(a) at the device intrinsic plane, where the equivalent quarter wave line. We consider the output parasitic
overlap between voltage and current is minimized with capacitance of power transistor CDS, TL3, and one of the C0 as
harmonic terminations to achieve a high efficiency. It should a π network. Combining with the equivalent quarter-wave line
be mentioned that we are allowed to access the device intrinsic TL4 and C0, the two cascaded π network can achieve a wide
plane of the transistor model to observe the waveform by bandwidth. It should be emphasized that the overall
collaboration with the foundry. impedance ZIN (see Fig. 2) looking towards the output port
The output matching network can be roughly divided to two from the intrinsic plane should satisfy the boundary conditions
parts. The design of TL6 to TL7 with C3 mainly considers the as ZIN (ω0) = Ropt, ZIN (2ω0) = 0 and ZIN (3ω0) = ∞ for the class
matching of the fundamental frequency. The rest elements are F PA. In practical design, the main parameters for harmonic
for the 2nd and 3rd harmonic terminations. Compared with the termination design of ZIN are CDS, LD, CSH, LBvia, C0, and the
conventional class F topology as shown in Fig. 1, the quarter- effective inductances of TL4, TL5, and the series TL3.
wave transmission line is replaced by TL4 with a relatively

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 Table 1. Comparison of Previous Published 0.25-μm GaN/GaAs MMIC PAs

Ref. Freq. Small-signal Peak P1dB PAE at 3-dB BW Chip-Size

Topology Technology
(GHz) gain (dB) Pout (dBm) (dBm) Peak Pout (%) (MHz) (mm×mm)
[3] Doherty GaN 0.25 μm 5.9 15 38.7 32.1 47.3 NA 2.49 × 1.56
[4] Doherty GaN 0.25 μm 14.6 7 36.0 30 40.0 NA 3.1 × 1.6
[6] Class F GaN 0.25 μm 4 11.4 30.4 NA 69 400 3.3 × 2.5
[7] Class F GaAs 0.25 μm 13.95 10.5 26.5 NA 57.6 1800 NA
[8] Class F GaAs 0.25 μm 5.5 13.7 27.5 NA 70 NA 1.24 × 1.25
This work Class F GaN 0.25 μm 6.0 10.8 36.6 35.5 65.8 1800*/2300+ 1.6 × 1.6
*
Measured small-signal 3-dB bandwidth; +Simulated large-signal 3-dB bandwidth at PIN of 26.5 dBm (around peak PAE).

Third_ext
Third_int
Fund_ext

100 μm
Fund_int

Second_int
Second_ext SiC

Ground
Solid Blue - Intrinsic
Dotted Red - Extrinsic

(a) (a)
70 0.8 40 80

0.7 70
60 38
0.6 60
50
IDS_int (A)
VDS_int (V)

0.5 36 50
L (pH)

40

Q
0.4 40
30 34
L
30
0.3 Q
20 20
0.2 32
10 10
0.1
30 0
0 0.0 3 6 9 12 15 18 21 24 27 30
0 50 100 150 200 250 300 350
time (psec) Frequency (GHz)

(b) (b)
Fig. 3. (a) Simulated matching trajectories from 3 to 20 GHz for the proposed Fig. 4. (a) 3D plot of the standard back via in the adopted 0.25-μm GaN
class F PA at the device intrinsic and extrinsic planes. (b) Time domain HEMT technology. (b) full-wave (HFSS) simulated results of inductance and
waveform at device intrinsic plane. quality factor.

10
0
S21 5
S11 and S22 (dB)

S21 and S12 (dB)

-4 0
S22 S11 -5
-8 -10
1.6 mm

-15
-12 Sim. (Open) -20
Meas. (Fill)
-16 -25
-30
-20 S12 -35
-40
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
1.6 mm Frequency (GHz)

(a) (b)
Fig. 5. (a) Chip micrograph of the fabricated class F amplifier. (b) Comparison of simulated and measured small-signal S-parameters.

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 36 80 [4] R. Quaglia et al., ‘‘A 4-W Doherty power amplifier in GaN MMIC
Gain_M technology for 15-GHz applications,’’ IEEE Microw. Wireless Compon.
32 Gain_S 70
Pout (dBm) and Gain (dB)
Lett., vol. 27, no. 4, pp. 365---367, Apr. 2017.
Pout_M
28 Pout_S 60 [5] S. C. Cripps, RF Power Amplifiers for Wireless Communications - 2nd
PAE_M ed. 685 Canton Street Norwood, MA 02062: ARTECH HOUSE, INC,
24 50
PAE_S May 2006, p. 158.

PAE (%)
20 [6] V. Zomorrodian, U. K. Mishra, and R. York, “A High efficiency class
40
16 F MMIC power amplifier at 4.0 GHz using AlGaN/GaN HEMT
30 technology,” IEEE CSIC Symp. Oct. 2012.
12
[7] M. Ozalas, “High efficiency class-F MMIC power amplifiers at Ku
20
8 band,” IEEE Wireless and Microwave Techn. conf., April 2005.
4 10 [8] G. Nikandish, E. Babakrpur, and A. Medi, “A harmonic termination
technique for single- and multi-band high-efficiency class-F MMIC
0 0 power amplifiers,” IEEE Trans. Microwave Theory Techn., vol. 62, no.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
5, pp. 1212–1220, May 2014.
Pin (dBm)

Fig. 6. Pout, gain, and PAE versus input power at 6.0 GHz of the class F PA.

III. RESULTS AND DISCUSSION

Fig. 5(a) shows the chip micrograph of the fabricated class
F PA by 0.25 μm GaN technology with a chip size of 1.6 mm
× 1.6 mm (2.56 mm2). The amplifier was biased from a 28 V
dc supply and measured on-wafer. A pre-amplifier was used to
enhance the maximum input power to 28 dBm. Fig. 5(b)
compares the measured and simulated small-signal S-
parameters of the circuit from 4 to 8 GHz at an input power of
-20 dBm. The input and output return loss larger than 10 dB is
obtained in a range of 5.3 to 6.8 GHz and 5.4 to 5.8 GHz,
respectively. The small-signal gain S21 around 10 dB is
achieved from 5.2 to 6.1 GHz, and the 3-dB BW is about 1800
MHz. Note that the simulated results indicate that the large-
signal BW is extended to 2300 MHz under PIN of 26.5 dBm.
The measured results shown in Fig. 6 at 6.0 GHz demonstrate
that a peak output power of 36.6 dBm with a PAE of 65.8 %
can be achieved. In addition, the amplifier shows a P1dB of
35.5 dBm with an associated PAE of 60 %. Table I shows the
comparison with previous PAs in 0.25-μm GaN or GaAs
HEMT technology.

IV. CONCLUSION
A high performance compact MMIC class F power
amplifier aiming for 5G small cell applications was
demonstrated in 0.25 μm GaN HEMT technology. The 2nd
and 3rd harmonics were terminated by the output matching
network, and optimized with the high quality factor backside
via parasitic inductance. The device drain-source parasitic
capacitance was also absorbed into the output matching circuit
for improving the bandwidth and high frequency operation.
The circuit achieved a high PAE of 65.8 % at 1.5 dB gain
compression, with 36.6 dBm output power at 6 GHz.
REFERENCES
[1] T. Qi and S. He, “Power up potential power amplifier technologies for
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2019.
[2] Z. Popovic, ‘‘Amping up the PA for 5G,’’ IEEE Microw. Mag., vol. 18,
no. 3, pp. 137–149, May 2017.
[3] S. Li, S. Hsu, J. Zhang, and K. Huang, “Design of a compact GaN
MMIC Doherty power amplifier and system level analysis with X-
parameters for 5 G communications,” IEEE Trans. Microwave Theory
Techn, vol. 66, no. 12, pp. 5676−5684, Dec. 2018.

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