2011 International Conference on Electronic & Mechanical Engineering and Information Technology

Design of three-lift controller based on FPGA

Xiaoyan Jiang Yujun Bao

School of Electronic Information & Electric Engineering School of Electronic Information & Electric Engineering
Changzhou Institute of Technology, CZU Changzhou Institute of Technology, CZU
Chanzhou, China Chanzhou, China
yanzi_fei@ 163. com

Abstract—This paper describes the design of elevator • You use a computer to describe a "logic function"
controller based on FPGA, the FPGA chip EP1C6Q240C8 is that you want. You might draw a schematic, or
used as the core of controller, and its functions are described create a text file describing the function.
in hardware description language VHDL, and its programs use
Max+plus II to compile and simulate, then downloaded to the • You compile the "logic function" on your computer.
test box to verify. The results show that the elevator is in line That creates a binary file that can be downloaded
with actual demand. Thus, it is highly practical. into the FPGA.

Keywords- FPGA; VHDL; Controller; Max+plus II • You connect a cable from your computer to the
FPGA, and download the binary file to the FPGA.
I. INTRODUCTION
Electronic Design Automation (EDA) combines III. ELEVATOR CONTROLLER REQUIREMENTS
electronic technology, computer technology, information FPGA design and implementation require a three-lift
processing, intelligent technology and so on; it is control system. System requirements are as follows:
indispensable technology with modern electronic system
design and manufacturing. With the rapid development of • Elevator rule: When the elevator is at the rising
EDA technology, the emergence of large-scale FPGA mode, only the response of the upstairs request,
programmable logic devices brought a lot of convenience to executive from the bottom to up one by one until the
the designers [1]. VHDL has abstract description of ability to last upstairs request is finished. If the top level has
support hardware design, verification, synthesis and testing. down request, directly to rise to the top floor of
It is often top-down structured design method for high-level downstairs request, and then into downward mode.
circuit modeling [2], with better efficiency and effectiveness. When elevator is at downward mode, work mode is
This article describes the FPGA-based elevator controller the opposite to up.
design method and simulation.
• The initial state of the elevator is at the first floor, in
open state.
II. FPGA FEATURES
• There are provided up and down request switch at
FPGAs are programmable digital logic chips[3]. What the e each layer entrance (the first layer is no
that means is that you can program them to do almost any downstairs request, the third layer is no upstairs
digital function. request), inside the elevator has stops request and the
Here are the general features with FPGAs: display switches.

• You can download FPGAs as many time as you • Set the location of the elevator instruction, and up or
want. If you make a mistake in your design, just fix down direction instructions.
your "logic function", re-compile and re-download it. • When the elevator stops to the request floor, the
• The designs can run much faster than if you were to elevator doors opened, open the door indicator lights.
design a board with discrete components, since Open the door 4 seconds, the elevator door closed,
everything runs within the FPGA, on its silicon die. door lights off, the elevator continues to run until the
last request signal executed, and then stop at the
• FPGAs lose their functionality when the power goes current layer.
away. You have to re-download them when power
goes back up to restore the functionality. • The elevator control system can storage inside and
outside request signals and elevator can operate in
Here's the general workflow when working with FPGAs: accordance with the rules, and can remove each
request signal[4].

978-l-61284-088-8/ll/$26. 00 ©2011 IEEE 531 12-14 August, 2011

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 IV. LEVATOR CONTROLLER the elevator occurs downstairs request at the external 3rd
layer D0WN3, DOWNLIGHT (3) <= ' 1 ' , so the value of the
A. Entity definitions waveform diagram DOWNLIGHT is 4, elevator POSTIONG
According to the design requirements of the elevator to 3rd layer, open the door to wait, and then closed; When
control system, it needs a system clock signal CLK, also the elevator has internal stop request at the first floor STOPl,
should define the input signals and output signals. STOPLIGHT (1) <= '1 ', the value of STOPLIGHT is 1,
elevator POSTIONG to the first layer, open the door to wait,
1) The input signas are defined as follows: then closed; when the elevator occurs upstairs request at the
a) System reset signal: RESET, active-high; external 2nd layer UP2, UPLIGHT(2) <= V , so the value of
the UPLIGHT is 2 , elevator POSTIONG to 2nd layer, open
b) The elevator upstairs request switch: UP1, UP2; the door to wait, and then closed; When the elevator has
c) The elevator downstairs request switch: DOWN2, internal stop request at the third floor ST0P3, STOPLIGHT
DOWN3; (3) <= ?1 ', the value of STOPLIGHT is 4, elevator
POSTIONG to the third layer, open the door to wait, then
d) The elevator stops within reach floor request closed; In addition, when the elevator from the third floor to
switch: STOPl, STOP2, STOP3. the first floor, UDSIG = '1 ', said the elevator is down, when
All of the input signals are defined as: the input signal is the elevator from the first floor to the second floor then to the
equal to 1, indicating a request; the signal is equal to 0, no third floor, UDSIG = '0 ', said the elevator is up. The location
requests. change of the elevator and its operation is consistent with
2) The output signals are defined as follows: initial design requirements.
a) Up and down request indicator outside the elevator:
UPTIGHT and DOWNLIGHT, these signals are respective
to UPl, UP2, DOWN2 andDOWN3 signal;
b) Stop request light inside the elevator: STOPLIGHT,
the signal is corresponding to STOPl, STOP2 and STOP3
signal;
c) Elevator operation mode indicator: UDSIG, 1
representative of drop mode, 0 for up mode;
d) Elevator floor indicate: POSITION, said the
elevator in the corresponding floor;
e) Elevator door status indication: DOORLIGHT, 1 Figure 1. Simulated waveform 1 of the elevator control system
said open, 0 closed.
3) Elevator controller entity procedures are as follows: Figure 2 is also the elevator control system simulation
LIBRARY IEEE; waveforms, which can be seen from the figure: when the
USE IEEE.STDLOGIC1164.ALL; elevator occurs downstairs request at the external 2nd layer
DOWN2, when the elevator has internal stop request at the
USE IEEE.STD_LOGIC_ARITH.ALL; first floor STOPl, the elevator is from the 2nd floor to 1st
USE IEEE.STD_LOGIC_UNSIGNED.ALL; floor, when the elevator occurs downstairs request at the
external 3rd layer DOWN3, the elevator from 1st layer to
ENTITY dianti_3 IS 3rd layer, during which will go through 2nd layer.
PORT(CLK,RESET,UPl,UP2,DOWN2,DOWN3,STOP
l,STOP2,STOP3:IN STDLOGIC; C. Hardware verification
Experimental box used GW48 Series , select the test
UPLIGHT,DOWNLIGHT,STOPLIGHT:BUFFER
mode 5, CLK links to clockO, keys 1-3 correspond to the
STD_LOGIC_VECTOR(3 DOWNTO 1);
layer buttons inside elevator, key 4 and key 5 correspond to
UDSIG: BUFFER STDLOGIC; the up button UPl and UP2; key 6 and key 7 correspond to
the down button DOWN2 and DOWN3; key 8 corresponds
POSITION : BUFFER INTEGER RANGE 1 TO 3; to the system reset button; light-emitting diode 1-3 indicate
DOORLIGHT : OUT STDLOGIC); each layer button inside elevator is pressed; light-emitting
diode 4 and 5 indicates up button of the lth and 2nd layer
ENDdianti_3; outside the elevator is pressed; light-emitting diode 6 and 7
indicates down button of the 2nd and 3rd layer outside the
B. System simulation elevator is pressed; light 8 indicates the door open.
Elevator control system simulation waveforms shown in
Fig. 1, it can be seen from the simulation waveform: when

532

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 REFERENCES

[1] SHEN Yanchun, ZHANG Yinpu, and WU Zheng, "Design of the

elevator controller based on FPGA," Science and Tdchnology
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[4] CHEN Huiping, WANG Zhangrui, MA Qiqiang, and HUANG
Xuekun, "Implemention of three-lift controller based on FPGA,"
Figure 2. Simulated waveform 2 of the elevator control system
INSTRUMENTION CUSTION, Vol;.14, pp. 72-73, 2007.
[5] SU Xinhong, and ZHANG Haiyan, "Design of smart elevator system
V. CONCLUSION based on FPGA," SCIENCE & TECHNOLOGY INFORMATION,
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This article describes the elevator controller using VHDL [6] GAO Yinghui, HOU Zhongxia, and YANG Chenlin, "Sesign of
language design, and use Max+plusII to simulate, and FPGA-based automatic elevator controller," Journal of Liaoning
through hardware verification. The slightest change in Technical University, Vol. 25, pp. 242-243, April 2007.
procedure can achieve a higher level of elevator control,
flexibility [5], and has broad application prospects [6].

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