A4919

Three-Phase MOSFET Driver with Integrated Regulator

FEATURES AND BENEFITS DESCRIPTION

• High-current 3-phase gate drive for N-channel MOSFETs The A4919 is a three-phase controller for use with N-channel
• 5.5 to 50 V supply voltage range external power MOSFETs.
• Regulated logic supply voltage output option
A unique charge pump regulator provides full (>10 V) gate drive
• Low-current Sleep mode option
at power supply voltages down to 7 V and allows the A4919
• Motor phase short-to-supply and short-to-ground detection
to operate with reduced gate drive at power supply voltages
• Cross-conduction protection
down to 5.5 V. A bootstrap capacitor is used to provide the
• Undervoltage, overtemperature monitors
above power supply voltage required for N-channel MOSFETs.
APPLICATIONS One logic-level input is provided for each of the six power
• Lawn and garden equipment MOSFETs in the 3-phase bridge, allowing motors to be driven
• Battery-operated power tools with any commutation scheme defined by an external controller.
• Industrial grinders The power MOSFETs are protected from cross-conduction by
• Continuous positive airway pressure (CPAP) machines integrated crossover control.
• Vacuum cleaners Motor phase short-to-supply and short-to-ground detection
is provided by independent drain-source voltage monitors on
PACKAGE: each MOSFET. Short faults, supply undervoltage, and chip
28-pin TSSOP
overtemperature conditions are indicated by a single open-
with exposed thermal pad drain fault output.
(suffix LP) Product variants incorporating a low dropout (LDO) regulator to
source either 5.0 V or 3.3 V to external circuitry are available.
28-terminal The A4919 is supplied in a 28-pin TSSOP power package with
5 mm × 5 mm QFN exposed thermal pad (package type LP) and a 28-terminal
with exposed thermal pad 5 mm × 5 mm × 0.90 mm QFN package with exposed thermal
(suffix ET) pad. Both packages are lead (Pb) free, with 100% matte-tin
leadframe plating (suffix T).
Not to scale

Typical Application Diagram

V+

VDD

3-Phase
BLDC
A4919 Motor
Micro-
controller

A4919-DS, Rev. 8 November 7, 2022

MCO-0000329
A4919 Three-Phase MOSFET Driver with Integrated Regulator

SELECTION GUIDE
Part Number Sleep Mode Regulator Packing Package
A4919GLPTR-T Yes –
9.7 mm × 4.4 mm, 1.2 mm nominal height
A4919GLPTR-3-T – 3.3 V 4000 pieces per 13-in. reel
28-pin TSSOP with exposed thermal pad
A4919GLPTR-5-T – 5V
A4919GETTR-T Yes –
5 mm × 5 mm, 0.9 mm nominal height
A4919GETTR-3-T – 3.3 V 1500 pieces per 7-in. reel
28-terminal QFN with exposed thermal pad
A4919GETTR-5-T – 5V

ABSOLUTE MAXIMUM RATINGS with respect to GND

Characteristic Symbol Notes Rating Unit
Load Supply Voltage VBB –0.3 to 50 V
VDDM if no internal LDO regulator, V3 or V5 if LDO regulator
Logic Monitor or Supply VDDM, V3, V5 –0.3 to 7 V
present
Terminal VREG –0.3 to 16 V
Terminals CP1, CP2 –0.3 to 16 V
Logic Inputs AHI, ALO, BHI, BLO, CHI,
–0.3 to 6.5 V
CLO
Terminal VBRG –5 to 55 V
Terminal LSS –4 to 6.5 V
Terminals SA, SB, SC –5 to 55 V
Terminals GHA, GHB, GHC Sx to Sx+15 V
Terminals GLA, GLB, GLC –5 to 16 V
Terminals CA, CB, CC –0.3 to Sx + 15 V
Terminal FAULT –0.3 to 6.5 V
Terminal VDSTH –0.3 to 6.5 V
Ambient Operating Temperature
TA Limited by power dissipation –40 to 105 °C
Range
Maximum Continuous Junction
TJ(max) 165 °C
Temperature
Overtemperature event not exceeding 10 seconds, lifetime
Transient Junction Temperature TtJ duration not exceeding 10 hours, determined by design 175 °C
characterisation.
Storage Temperature Range Tstg –55 to 150 °C

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Unit
LP package, on 4-layer PCB based on JEDEC standard 28 °C/W
Package Thermal Resistance
RθJA LP package, on 2-layer PCB with 3.8 in2 copper each side 32 °C/W
(Junction to Ambient)
ET package, on 4-layer PCB based on JEDEC standard 32 °C/W
Package Thermal Resistance LP package 2 °C/W
RθJP
(Junction to Pad) ET package 2 °C/W
*Additional thermal information available on the Allegro website.

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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
[Link]
A4919 Three-Phase MOSFET Driver with Integrated Regulator

Table of Contents
Specifications 2
Absolute Maximum Ratings 2
Thermal Characteristics 2
Pinout Diagram and Terminal Lists 4
Functional Block Diagram 6
Electrical Characteristics 7
Functional Description 10
Input and Output Terminal Functions 10
Power Supplies 11
CP1, CP2, VREG 11
Sleep Mode 11
Gate Drives 11
High-Side Gate Drives (GHA, GHB, GHC) 11
Bootstrap Charge Management 11
Low-side Gate Drive (GLA, GLB, GLC) 12
Drain Source Voltage Monitor 12
Logic Control Inputs 13
Diagnostics 13
Fault States 13
Low Dropout (LDO) Regulator 15
Applications Information 16
Power Bridge Management Using PWM Control 16
Bootstrap Capacitor Selection 16
Bootstrap Charging 17
VREG Capacitor Selection 17
LDO Regulator Capacitor Selection 17
Supply Decoupling 17
Input/Output Structures 18
Layout Recommendations 19
Package Outline Drawings 20

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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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A4919 Three-Phase MOSFET Driver with Integrated Regulator

PINOUT DIAGRAMS AND TERMINAL LIST TABLES

LP Pinout Diagrams

LSS 1 28 CLO LSS 1 28 CLO LSS 1 28 CLO

GLC 2 27 CHI GLC 2 27 CHI GLC 2 27 CHI
GHC 3 26 BLO GHC 3 26 BLO GHC 3 26 BLO
SC 4 25 BHI SC 4 25 BHI SC 4 25 BHI
CC 5 24 ALO CC 5 24 ALO CC 5 24 ALO
GLB 6 23 AHI GLB 6 23 AHI GLB 6 23 AHI
PAD PAD PAD
GHB 7 22 FAULT GHB 7 22 FAULT GHB 7 22 FAULT
SB 8 21 VDSTH SB 8 21 VDSTH SB 8 21 VDSTH
CB 9 20 V3 CB 9 20 V5 CB 9 20 VDDM
GLA 10 19 GND GLA 10 19 GND GLA 10 19 GND
GHA 11 18 VBRG GHA 11 18 VBRG GHA 11 18 VBRG
SA 12 17 VBB SA 12 17 VBB SA 12 17 VBB
CA 13 16 CP1 CA 13 16 CP1 CA 13 16 CP1
VREG 14 15 CP2 VREG 14 15 CP2 VREG 14 15 CP2

A4919GLPx-3 variant A4919GLPx-5 variant A4919GLPx (No LDO) variant

Terminal List Table

Name Number Function Name Number Function
LSS 1 Low-Side Source CP1 16 Pump Capacitor
GLC 2 Low-Side Gate Drive Phase C VBB 17 Main Power Supply
GHC 3 High-Side Gate Drive Phase C VBRG 18 High-Side Bridge Voltage Sense
SC 4 Motor Connection Phase C GND 19 Ground
CC 5 Bootstrap Capacitor Phase C V3 Voltage Supply (Output) – A4919GLPx-3
V5 20 Voltage Supply (Output) – A4919GLPx-5
GLB 6 Low-Side Gate Drive Phase B
VDDM Monitor Input – A4919GLPx (No LDO)
GHB 7 High-Side Gate Drive Phase B
VDSTH 21 VDS Monitor Threshold Voltage
SB 8 Motor Connection Phase B
FAULT 22 Programmable Diagnostic Output
CB 9 Bootstrap Capacitor Phase B
AHI 23 Phase A High-Side Control Input
GLA 10 Low-Side Gate Drive Phase A
ALO 24 Phase A Low-Side Control Input
GHA 11 High-Side Gate Drive Phase A
BHI 25 Phase B High-Side Control Input
SA 12 Motor Connection Phase A
BLO 26 Phase B Low-Side Control Input
CA 13 Bootstrap Capacitor Phase A
CHI 27 Phase C High-Side Control Input
VREG 14 Gate Drive Supply Output
CLO 28 Phase C Low-Side Control Input
CP2 15 Pump Capacitor Pad – Exposed Thermal Pad On Underside

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Allegro MicroSystems
955 Perimeter Road
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A4919 Three-Phase MOSFET Driver with Integrated Regulator

ET Pinout Diagrams
25 VREG

25 VREG

25 VREG
22 GHA

22 GHA

22 GHA
28 VBB

28 VBB

28 VBB
27 CP1
26 CP2

27 CP1
26 CP2

27 CP1
26 CP2
24 CA

24 CA

24 CA
23 SA

23 SA

23 SA
VBRG 1 21 GLA VBRG 1 21 GLA VBRG 1 21 GLA
GND 2 20 CB GND 2 20 CB GND 2 20 CB
V3 3 19 SB V5 3 19 SB VDDM 3 19 SB
VDSTH 4 PAD 18 GHB VDSTH 4 PAD 18 GHB VDSTH 4 PAD 18 GHB
FAULT 5 17 GLB FAULT 5 17 GLB FAULT 5 17 GLB
AHI 6 16 CC AHI 6 16 CC AHI 6 16 CC
ALO 7 15 SC ALO 7 15 SC ALO 7 15 SC
CHI 10

LSS 12
GLC 13
GHC 14

CHI 10

LSS 12
GLC 13
GHC 14

CHI 10

LSS 12
GLC 13
GHC 14
CLO 11

CLO 11

CLO 11
8
9

8
9

8
9
BHI
BLO

BHI
BLO

BHI
BLO
A4919GETx-3 variant A4919GETx-5 variant A4919GETx (No LDO) variant

Terminal List Table

Name Number Function Name Number Function
VBRG 1 High-Side Bridge Voltage Sense SC 15 Motor Connection Phase C
GND 2 Ground CC 16 Bootstrap Capacitor Phase C
V3 Voltage Supply (Output) – A4919GETx-3 GLB 17 Low-Side Gate Drive Phase B
V5 3 Voltage Supply (Output) – A4919GETx-5
VDDM Monitor Input – A4919GETx (No LDO) GHB 18 High-Side Gate Drive Phase B
VDSTH 4 VDS Monitor Threshold Voltage SB 19 Motor Connection Phase B
FAULT 5 Programmable Diagnostic Output CB 20 Bootstrap Capacitor Phase B
AHI 6 Phase A High-Side Control Input GLA 21 Low-Side Gate Drive Phase A
ALO 7 Phase A Low-Side Control Input GHA 22 High-Side Gate Drive Phase A
BHI 8 Phase B High-Side Control Input SA 23 Motor Connection Phase A
BLO 9 Phase B Low-Side Control Input CA 24 Bootstrap Capacitor Phase A
CHI 10 Phase C High-Side Control Input VREG 25 Gate Drive Supply Output
CLO 11 Phase C Low-Side Control Input CP2 26 Pump Capacitor
LSS 12 Low-Side Source CP1 27 Pump Capacitor
GLC 13 Low-Side Gate Drive Phase C VBB 28 Main Power Supply
GHC 14 High-Side Gate Drive Phase C Pad – Exposed Thermal Pad On Underside

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Allegro MicroSystems
955 Perimeter Road
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A4919 Three-Phase MOSFET Driver with Integrated Regulator

Power Supply +
V3 (A4919x-3) CP
A V5 (A4919x-5)
VDDM (A4919x)
VBB CP1 CP2

Charge VREG VBAT

LDO Pump
Regulator Regulator CREG
(A4919x-3)
(A4919x-5)
VBRG

Phase A
Logic Supply
Regulator CA

CBOOTA

AHI High Side GHA One of three phases shown

Drive RGATE
ALO VDS
Control Monitor
Logic SA
BHI
VDS
Monitor
BLO
VREG

CHI GLA
Low Side
Drive Phase C
RGATE
CLO
Phase B

FAULT LSS
Diagnostics
and
VDSTH Protection

GND

A External pin acts as a monitor input (VDDM) on

variants without LDO regulator, and a supply voltage
output on variants with LDO regulator (designated V3
or V5 for 3.3 V and 5.0 V variants respectively)

Functional Block Diagram

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

ELECTRICAL CHARACTERISTICS [1]: Valid at TJ = 25°C, VBB = 7 to 50 V, unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Unit
SUPPLY AND REFERENCE
VBB Functional Operating Range [2] VBB Correct function, parameters not guaranteed 5.5 – 50 V
IBBQ Operational mode, outputs low, VBB = 12 V – 10 14 mA
VBB Quiescent Current [3] Sleep mode, VBB = 12 V
IBBS – – 15 µA
(A4919x, No LDO, variant)
VBB > 9 V, IREG = 0 to 15 mA 12.5 13 13.75 V
7.5 V < VBB ≤ 9 V, IREG = 0 to 10 mA 12 13 13.75 V
VREG Output Voltage VREG 2×VBB
6 V < VBB ≤ 7.5 V, IREG = 0 to 9 mA – – V
– 3.0
5.5 V < VBB ≤ 6 V, IREG < 8 mA 8.5 9.5 – V
ID = 10 mA 0.4 0.7 1.0 V
Bootstrap Diode Forward Voltage VfBOOT
ID = 100 mA 1.5 2.2 3.1 V
rD(100mA) = (VfBOOT(150mA) – VfBOOT(50mA)) /
Bootstrap Diode Resistance rD 6 13 28 Ω
100 (mA)
Bootstrap Diode Current Limit IDBOOT 250 500 750 mA
GATE OUTPUT DRIVE
Turn-On Time tr CLOAD = 1 nF, 20% to 80% – 35 – ns
Turn-Off Time tf CLOAD = 1 nF, 80% to 20% – 20 – ns
TJ = 25°C, IGHx = –150 mA 5 8 13 Ω
Pull-Up On Resistance RDS(on)UP
TJ = 105°C, IGHx = –150 mA – 13 – Ω
TJ = 25°C, IGLx = 150 mA 1.5 2.4 4.6 Ω
Pull-Down On Resistance RDS(on)DN
TJ = 105°C, IGLx = 150 mA – 3 – Ω
GHx Output Voltage – High VGHH Bootstrap capacitor fully charged VCx – 0.2 – – V
GHx Output Voltage – Low VGHL – – VSX + 0.3 V
GLx Output Voltage – High VGLH VREG – 0.2 – – V
GLx Output Voltage – Low VGLL – – VLSS + 0.3 V
GHx Passive Pull-Down Resistance RGHPD VGHx – VSx < 0.3 V – 400 – kΩ
GLx Passive Pull-Down Resistance RGLPD VGLx – VLSS < 0.3 V – 400 – kΩ
Turn-Off Propagation Delay [4] tP(off) Input change to unloaded gate output change 60 90 180 ns
Turn-On Propagation Delay [4] tP(on) Input change to unloaded gate output change 60 90 180 ns
Propagation Delay Matching – Phase
∆tPP Same phase change – 10 – ns
to Phase
Propagation Delay Matching – On
∆tOO Single phase – 30 – ns
to Off

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Allegro MicroSystems
955 Perimeter Road
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A4919 Three-Phase MOSFET Driver with Integrated Regulator

ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TJ = 25°C, VBB = 7 to 50 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
LOGIC INPUTS AND OUTPUTS
Input Low Voltage VIL – – 0.8 V
Input High Voltage VIH 2.0 – – V
Input Hysteresis VIhys 100 300 – mV
Input Pull-Down Resistor (xHI, xLO) RPD – 50 – kΩ
Input Pulse Filter Time (xHI, xLO) tPIN – 35 – ns
VDS Disable Voltage VDSD – – 100 mV
Fault Disable Voltage VFLTD – – 0.5 V
Output Low Voltage (FAULT) VOL IOL = 1 mA, no fault indicated – 0.2 0.4 V
Output Leakage (FAULT) [5] IO 0 V < VO < 5.5 V, fault indicated –1 – 1 µA
PROTECTION
VREGON VREG rising 7.5 8 8.5 V
VREG Undervoltage Lockout
VREGOFF VREG falling 6.75 7.25 7.75 V
Bootstrap Undervoltage Threshold VBOOTUV VBOOT falling, VCx – VSx 62 – 75 %VREG
Bootstrap Undervoltage Hysteresis VBOOTHys – 9 – %VREG
VDDM / V3 / V5 Undervoltage
VDDUV Voltage falling 2.45 2.7 2.85 V
Threshold [6]
VDDM / V3 / V5 Undervoltage
VDDUVHys 40 100 160 mV
Hysteresis [6]
VDS Threshold – Internal VDSTHI VDSTH > 2.7 V 1.0 1.2 1.4 V
VDS Threshold Range VDSTH 0.2 – 2 V
VDS Threshold Input Leakage VDSTHL 0 V < VDSTH < 5.5 V –3 – 3 µA
VBRG Input Voltage VBRG VBB – 1 VBB VBB + 1 V
VBRG Input Current IVBRG VDSTH = 2 V, VBB = 12 V, 0 V < VBRG < VBB – – 250 µA
VDSTH ≥ 1 V – ±100 – mV
Short-to-Ground Threshold Offset VSTGO
VDSTH < 1 V –150 ±50 +150 mV
Short-to-Power Supply Threshold VDSTH ≥ 1 V – ±100 – mV
VSTPO
Offset VDSTH < 1 V –150 ±50 +150 mV
VDS Fault Blank Time tBL 1.5 2.3 4.5 µs
Overtemperature Warning TJF Temperature increasing 170 – 180 °C
Overtemperature Hysteresis TJHyst Recovery = TJF – TJHyst – 15 – °C
VARIANT WITHOUT LDO REGULATOR ONLY (A4919x)
Input Low Voltage For Sleep Mode VILS xHI, xLO – – 0.5 V
Sleep Mode Activation Timeout
tSLT From all xHI, xLO < VIL 7.5 10 12.5 ms
(xHI, xLO) [3]
Wake-up from Sleep Delay [3] tWK Any xHI, xLO > VIH , CREG < 1 µF – – 1 ms
Gate Drive Disable Threshold VGDD – 1.5 – V
VDDM Pull-Down Resistor RVDDM – 60 – kΩ

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Allegro MicroSystems
955 Perimeter Road
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A4919 Three-Phase MOSFET Driver with Integrated Regulator

ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TJ = 25°C, VBB = 7 to 50 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
5 V LDO REGULATOR VARIANT ONLY (A4919x-5 ) [7]
IV5 < 70 mA, VBB > 6 V 4.85 – 5.25 V
V5 Output Voltage V5
5 mA < IV5 < 25 mA 4.9 5.0 5.2 V
V5 Output Overcurrent Limit ILDOOC(V5) 130 – 260 mA
V5 Shutdown Voltage Threshold VLDOSD(V5) Voltage falling 450 – 850 mV
V5 Shutdown Voltage Hysteresis VLDOHys(V5) 80 – 200 mV
V5 Pilot Current [8] ILDOP(V5) LDO regulator shut down – 2 – mA
V5 Shutdown Lockout Period tLDOL(V5) From V5 < VLDOSD(V5) – 2 – ms
3 V LDO REGULATOR VARIANT ONLY (A4919x-3 ) [7]
IV3 < 70 mA, VBB > 6 V 3.15 – 3.53 V
V3 Output Voltage V3
5 mA < IV3 < 25 mA 3.2 3.3 3.5 V
V3 Output Overcurrent Limit ILDOOC(V3) 130 – 260 mA
V3 Shutdown Voltage Threshold VLDOSD(V3) Voltage falling 450 – 850 mV
V3 Shutdown Voltage Hysteresis VLDOHys(V3) 80 – 200 mV
V3 Pilot Current [8] ILDOP(V3) LDO regulator shut down – 2 – mA
V3 Shutdown Lockout Period tLDOL(V3) From V3 < VLDOSD(V3) – 2 – ms

[1] Specifications presented apply to all product variants except where variant-specific limitations are explicitly defined.
[2] Function is correct but parameters are not guaranteed below the general limits (7 V).
[3] Sleep mode entered after logic low (less than V ) simultaneously detected on all xLO and xHI inputs for a period of t
IL SLT . Operating mode resumed
within tWK of logic high (greater than VIL ) being detected on any of the xLO or xHI pins.
[4] See Figure 1 for gate drive output timing.
[5] For input and output current specifications, negative current is defined as coming out of (sourced by) the specified device terminal.
[6] On product variants with LDO regulator (A4919x-3 and A4919x-5), an undervoltage trip sets all gate drive outputs low and an unlatched fault
state on the FAULT pin. On product variants without LDO regulator (A4919x), an undervoltage trip has no effect on device operation but sets an
unlatched fault state on the FAULT pin.
[7] A capacitance of at least 1 µF with an ESR of no more than 250 mΩ should be fitted between the LDO V3 / V5 output and GND to ensure stability.
[8] Pilot current is disabled while the overtemperature warning is active.

xH

xL

tP(off) tP(on) tP(off) tP(on)

GHx

GLx

Figure 1: Gate Drive Timing

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Allegro MicroSystems
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A4919 Three-Phase MOSFET Driver with Integrated Regulator

FUNCTIONAL DESCRIPTION
The A4919 provides six high-current gate drives capable of driv- V3. Unique to A4919x-3 variant (has a 3.3 V LDO regulator).
ing a wide range of N-channel power MOSFETs. The gate drives Sources 3.3 V to power external circuitry but does not power any
are configured as three high-side drives and three low-side. The on-chip functions. Must be loaded with appropriate capacitance
six gate drives are controlled by individual TTL-threshold logic as detailed in the Electrical Characteristics table.
inputs which may be driven from 3.3 V or 5 V logic outputs.
V5. Unique to A4919x-5 variant (has a 5 V LDO regulator).
The A4919 provides all necessary circuitry to ensure that the Sources 5 V to power external circuitry but does not power any
gate-source turn-on voltages of both high-side and low-side on-chip functions. Must be loaded with appropriate capacitance
external MOSFETs are driven above 10 V at supply voltages as detailed in the Electrical Characteristics table.
down to 7 V. For extreme low-power supply voltage conditions,
correct functional operation is maintained down to 5.5 V but with CP1, CP2. Pump capacitor connection for charge pump. Connect
a reduced gate drive. a minimum 220 nF capacitor, typically 470 nF, between CP1 and
CP2.
The control inputs to the A4919 provide a simple solution for
many motor drive applications controlled by an external micro- VREG. Regulated voltage, nominally 13 V, used to supply the
controller or DSP. Phase commutation and PWM control must be low-side gate drivers and to charge the bootstrap capacitors. A
managed by the external system controller. sufficiently large storage capacitor must be connected to this
terminal to provide the transient charging current.
Specific device functions are described more fully in the follow-
ing sections. GND. Analog reference, digital, and power ground. Connect to
supply ground (see Layout Recommendations section).

Input and Output Terminal Functions CA, CB, CC. High-side connections for the bootstrap capacitors
and positive supply for high-side gate drivers.
VBB. Power supply for all device functions including internal
logic and charge pump. Also used to power the LDO regulator GHA, GHB, GHC. High-side, gate-drive outputs for external
where present. N-channel MOSFETs.

System power should be connected to VBB through a reverse SA, SB, SC. Motor phase connections. Used to sense the voltages
voltage protection circuit. The VBB pin should be decoupled to switched across the load. Also connected to the negative side of
ground with ceramic capacitors mounted physically close to the the bootstrap capacitors and constitute the negative supply con-
device pins. nections for the floating high-side drivers.

VDDM. Unique to parts without an LDO regulator. It does not GLA, GLB, GLC. Low-side gate-drive outputs for external
provide power to support external circuitry and must be con- N-channel MOSFETs.
nected to the system logic supply voltage or similar. LSS. Low-side return path for discharge of the capacitance on the
If the voltage applied on VDDM drops below the VDDUV under- MOSFET gates, connected to the common sources of the low-
voltage threshold (2.7 V typ), an unlatched fault condition is side external MOSFETs through a low-impedance PCB trace.
set on the FAULT pin. If it rises above VDDUV +VDDUVHys the VBRG. Sense input to the top of the external MOSFET bridge.
fault condition is cleared. Additionally, if the voltage on VDDM
Allows accurate measurement of the voltage at the drains of the
drops below the VGDD gate drive disable threshold (1.5 V typ),
high side MOSFETs.
the charge pump is turned off and all gate drive outputs are
disabled. If it rises above VGDD, the charge pump restarts and all AHI, BHI, CHI. Input to control the high-side gate drives. A logic
gate drives are enabled. A pull-down resistance (60 kΩ typical) is high on the pin commands the relevant high-side gate drive to be
connected from VDDM to ground within the device. activated.

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955 Perimeter Road
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A4919 Three-Phase MOSFET Driver with Integrated Regulator

ALO, BLO, CLO. Input to control the low-side gate drives. A with the Input Logic Low Voltage For Sleep (VILS) are detected
logic high on the pin commands the relevant low-side gate drive simultaneously on all xLO and xHI inputs for a period equal to
to be activated. the Sleep Mode Activation Timeout (tSLT). In Sleep mode, all
FAULT. Open-drain active-high fault output. If a fault is present,
outputs are switched to a high-impedance state.
the open-drain pull-down is off and the FAULT output may be Operating mode is activated within a period equal to the Wake-
pulled high by an external pull-up resistor connected to any volt- up from Sleep Delay (tWK) from when a logic high is detected
age up to a maximum of 5.5 V. on any of the xLO or xHI pins. In operating mode, logic low
VDSTH. Drain source fault threshold programming pin. The control states applied on the xHI, xLO inputs need only comply
VDS fault threshold may be set by applying an externally gener- with the Input Low Voltage (VIL) and not the lower Input Logic
ated analog voltage. VDS fault reporting is disabled if VDSTH Low Voltage For Sleep (VILS). It is recommended that all xLO
is driven to less than VDSD (for example, shorted to ground). inputs are simultaneously driven to logic high (GLx turned on)
The VDS fault threshold is set to an internally hardwired value, when waking from Sleep mode, in order to recharge the bootstrap
VDSTHI, if VDSTH is driven to a voltage above its specified capacitors and enable subsequent high-side turn on.
analog input range (for example, pulled-up to the system logic Sleep mode is not available on A4919x-3 and A4919x-5 (LDO
supply voltage).
regulator) variants. If all logic inputs are taken low, power
consumption remains unchanged and all functions remain opera­
Power Supplies tional.

A single supply voltage applied to the VBB pin powers all device
functions including on-chip logic, analog circuitry, output drivers Gate Drives
and the LDO regulator (where present). The supply should be
The A4919 is designed to drive external, low on-resistance,
connected to VBB through a reverse voltage protection circuit
power N-channel MOSFETs. It will supply the large transient
and decoupled by way of a ceramic capacitor mounted close
to the VBB and GND terminals. All variants of the A4919 will currents necessary to quickly charge and discharge the exter-
operate within specified performance limits with VBB between nal MOSFET gate capacitances in order to reduce dissipation
7 and 50 V, and will function correctly with VBB as low as 5.5 V. in the external MOSFET during switching. Charge current for
the low‑side drives is provided directly by the capacitor on
CP1, CP2, VREG the VREG terminal. Charge current for the high-side drives is
The gate drivers are powered by an internal regulator which delivered via the bootstrap capacitors connected, one per phase,
limits the supply to the drivers and therefore the maximum gate across the Cx – Sx terminal pairs. Charge and discharge rate can
voltage. For VBB supply greater than approximately 16 V, the be controlled by incorporating an external resistor in series with
regulator is a simple buck regulator. Below 16 V, the regulated each MOSFET gate drive (GHx, GLx).
supply is maintained by a charge pump boost converter which
requires a pump capacitor, typically 470 nF, connected between High-Side Gate Drives (GHA, GHB, GHC)
the CP1 and CP2 terminals. The regulated voltage, nominally These are the high-side gate drive outputs for external N-channel
13 V, is available on the VREG terminal. A sufficiently large MOSFETs. An external resistor between the GHx gate drive
storage capacitor (see the Applications Information section) must output and the MOSFET gate terminal (mounted as close to the
be connected to this terminal to provide the transient charging latter as possible) may be used to control the slew rate at the gate,
current to the low‑side drivers and the bootstrap capacitors. thereby controlling the di/dt and dv/dt at the Sx terminals. Setting
GHx high turns-on the upper half of the driver, sourcing current
to the gate of the high-side MOSFET in the external motor-driv-
Sleep Mode ing bridge, turning it on. Setting GHx low turns-on the lower half
A low-power Sleep mode is available on the A4919x (no LDO of the driver, sinking current from the external MOSFET gate
regulator) variant. It is activated after logic low states compatible circuit to the respective Sx terminal, turning it off.

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

Bootstrap Charge Management

Bootstrap capacitors are charged to approximately VREG when
the associated Sx terminal is driven low. When the Sx terminal
subsequently goes high, the capacitor provides the necessary volt-
age for high-side N-channel power MOSFET turn-on. At system
startup, it is necessary to turn on each low-side drive (GLx) prior 5.5 V
to attempting to turn on the complementary high-side (GHx), in
order to charge the bootstrap capacitors. Internal[1]
(Threshold set to internal value, VDSTHI,
with accuracy specified in Electrical
Low-side Gate Drive (GLA, GLB, GLC) Characteristics table)
The low-side, gate-drive outputs on GLA, GLB, and GLC are
referenced to the LSS terminal. These outputs are designed to
drive external N-channel power MOSFETs. An external resistor
between the GLx gate drive output and the MOSFET gate ter-
minal (mounted as close to the latter as possible) may be used to 2.7 V
control the slew rate at the gate, thereby providing some control
of the di/dt and dv/dt at the Sx terminals. Setting GLx high turns-
on the upper half of the driver, sourcing current to the gate of the Indeterminate[2][3]
low-side MOSFET in the external motor-driving bridge, turning
it on. Setting GLx low turns-on the lower half of the driver, sink-
ing current from the external MOSFET gate circuit to the to the 2.3 V
External
LSS terminal, turning it off.
(Threshold set to voltage
approximately equal to that applied on
VDSTH pin. Accuracy not specified.)
Drain Source Voltage Monitor
2.0 V VDSTH (max)
The VDS fault threshold is set by applying a control voltage on External

the VDSTH pin, as detailed in Figure 2. If a voltage between (Threshold set to voltage applied on
VDSTH pin with accuracy specified in
0.2 and 2.0 V is applied, the threshold follows this level, subject Electrical Characteristics table)
to the Short to Ground Threshold (VSTGO) and Short to Power
Supply Threshold (VSTPO) offsets detailed in the Electrical Char-
acteristics table.
0.2 V VDSTH (min)
Indeterminate[2]
If a voltage between 2.0 and 2.3 V is applied, the threshold
0.1 V VDSD
approximates the applied level, but accuracy is not specified. Disabled
0V
If the VDSTH pin is driven below the VDS Disable Voltage
[1]
(VDSD), 0.1 V (such as when shorted to ground), VDS fault VDSTH pin typically tied to system logic supply voltage
(for example, V3 or V5)
reporting is disabled.
[2]
Behaviour indeterminate due to threshold detection uncertainty
If the VDSTH pin is taken above 2.7 V (such as when pulled [3]
Threshold range confirmed by design
up to the system logic supply voltage) the threshold is set to the
VDS Threshold Internal voltage (VDSTH), detailed in the Electri-
cal Characteristics table (typically 1.2 V). Figure 2: VDSTH Pin Voltage versus VDS Monitor
Function
The VDSTH pin presents a high impedance at all voltages across
its permissible input range (per the VDS Threshold Input Leak-
age limits, VDSTHL , detailed in the Electrical Characteristics

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

table), allowing a wide range of programming circuits to be used Diagnostics

including simple resistive dividers.
Several diagnostic features are integrated into the A4919 to
The VDSTH input has an internal passive first-order filter with a indicate fault conditions. In addition to system-wide faults such
time constant of approximately 0.01 ms. Additional filter capaci- as undervoltage and overtemperature, the A4919 integrates
tance may be added externally if required. individual monitors for each bootstrap capacitor voltage and each
external MOSFET drain-source voltage.
Logic Control Inputs The presence of a fault condition is indicated on the FAULT pin.
This is an open drain output that should be pulled to any voltage,
A set of discrete digital inputs (xHI and xLO) provides direct
up to 5.5 V, by an external resistor, typically 10 to 47 kΩ. The
control of the six gate drive outputs (GHx and GLx). TTL input
definition of the individual fault states and the effects on the gate
threshold levels ensure these can be driven from 3.3 V or 5 V
drive outputs (GHx and GLx) are shown in Table 2 and described
logic systems. Setting a logic input high causes the corresponding
below.
gate drive output to go high, thereby commanding the associated
external MOSFET to turn on. Conversely, setting a logic input
low causes the corresponding gate drive to go low, commanding Fault States
the MOSFET to turn off.
It is recommended that any external control circuitry remaining
Internal lock-out logic, detailed in Table 1, ensures that the active in the event of a fault state being flagged be configured
high-side output drive and low-side output drive cannot be active to take appropriate action to prevent damage to the A4919 and
simultaneously. associated motor drive components.

Table 1: Phase Control Truth Table Overtemperature. If the junction temperature exceeds the
Input Output Phase
overtemperature warning threshold (TJF), the A4919 enters the
overtemperature warning state and FAULT goes high. When
xHI xLO GHx GLx Sx Comment
the junction temperature drops below the recovery level ( TJF
0 0 L L Z Phase disabled – TJF hys ), the overtemperature warning state is cleared and the
0 1 L H LO Low-side active FAULT output returned to logic low.
1 0 H L HI High-side active
While an overtemperature warning state is being asserted, no on-
1 1 L L Z Phase disabled chip circuitry or functions are disabled, with the exception of the
HI = high-side MOSFET active LDO regulator on the A4919x-3 and A4919x-5 variants, which is
LO = low-side MOSFET active
shut down immediately and remains off until the overtemperature
Z = high impedance, both MOSFETs off
warning state is cleared.

Table 2: Fault Definitions

FAULT Pin Fault
Fault Description Outputs Disabled
State Latched
Low No fault No –
High Overtemperature No No
VDDM undervoltage All gate drives enabled for VDDM > VGDD. All gate drives
(A4919x variant, without LDO) low (external MOSFETs off) for VDDM ≤ VGDD
High No
V3 or V5 undervoltage
All gate drives low (external MOSFETs off)
(A4919x-3 and A4919x-5 variants, with LDO)
High VREG undervoltage All gate drives low (external MOSFETs off) No
High VDS overvoltage No No
High-side drive of the output phase that is generating the
High Bootstrap undervoltage fault condition is set low (external MOSFET off). Other Yes
outputs unaffected.

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

VREG Undervoltage. The charge pump generates VREG to Bootstrap Capacitor Undervoltage. Each bootstrap capacitor
provide low-side gate driver and bootstrap charge current. It is monitored to ensure sufficient high-side gate drive voltage is
is necessary to ensure that this voltage is high enough prior to available to initiate and maintain external MOSFET turn-on.
enabling any of the gate drive outputs. If the voltage at the VREG
High-side gate drive outputs turn on only if the relevant bootstrap
pin drops below the VREG Undervoltage Lockout Threshold
capacitor voltage is higher than the bootstrap turn-on voltage
(falling), VREGOFF , the A4919 enters the VREG undervoltage
threshold, VBOOTUV + VBOOTHys . If the bootstrap voltage is
fault state, FAULT is set high, and all gate drive outputs (GHx
below this threshold when turn-on is commanded (on the xHI
and GLx) are disabled. The VREG undervoltage fault state is
pin), the corresponding gate drive, GHx, is not switched on and
cleared and FAULT goes low when VREG rises above the VREG
FAULT is set high. The output remains off and FAULT remains
Undervoltage Lockout Threshold (rising), VREGON .
high until either the affected gate drive is commanded to turn
During power-up, the VREG undervoltage monitor circuit is off, or the FAULT pin is pulled low by external means (see the
active and the A4919 remains in the VREG undervoltage fault FAULT Disable description, below).
state until VREG is greater than the rising VREG Undervoltage
After a high-side gate drive has been successfully turned on, the
Lockout Threshold (VREGON, rising).
appropriate bootstrap capacitor voltage must remain above the
VDDM / V3 / V5 Undervoltage. The voltage on the VDDM / V3 Bootstrap Undervoltage Threshold, VBOOTUV . If the bootstrap
/ V5 pin is monitored on all part variants. If it drops below the capacitor voltage drops below VBOOTUV, the high-side driver in
VDDM / V3 / V5 undervoltage threshold, VDDUV, the A4919 question is switched off and FAULT goes high. The driver will
enters the VDDM/V3/V5 undervoltage state and FAULT is set remain off and FAULT will remain high until either the affected
high. On part variants with LDO regulator functionality, all high-side gate drive turn-on command is removed from xHI or
gate drive outputs (GHx, GLx) are disabled. On the part variant the FAULT pin is pulled low by external means (see the FAULT
without LDO functionality, all gate drive outputs remain active Disable description below).
unless the applied voltage also drops below the gate drive disable
If a bootstrap capacitor fault condition is detected, only the driver
threshold, VGDD. The VDDM/V3/V5 undervoltage fault state is
in question is disabled. All other gate drives continue to respond
cleared and FAULT goes low when the voltage on VDDM / V3 /
to control inputs on xHI and xLO.
V5 pin rises above VDDUV+VDDUVhys.
FAULT Disable. If the FAULT pin is held low (below the Fault
During power-up, the VDDM/V3/V5 undervoltage monitor cir-
Disable Voltage, VFLTD ) by external means, the bootstrap under-
cuit is active and all variants of the A4919 remain in the VDDM/
voltage monitor feature is disabled. In this condition, if the boot-
V3/V5 undervoltage fault state until the voltage on the VDDM/
strap capacitor voltage fails to reach VBOOTUV + VBOOTHys for
V3/V5 pin is greater than the VDDM/V3/V5 undervoltage thresh-
turn-on, or if it drops below VBOOTUV after turn-on, the driver in
old plus hysteresis, VDDUV+VDDUVhys.
question is not forced into the off state. A fault state is not flagged
VDS Overvoltage. When a gate drive output is commanded to because the FAULT pin is held low.
turn on (GHx or GLx high), the drain-source voltage of the cor-
While the FAULT pin is held low (to disable the bootstrap under-
responding external MOSFET is monitored between VBRG and
voltage monitor), any other fault conditions that might arise are
Sx, or between Sx and LSS, as appropriate. If the measured volt-
undetectable outside the A4919. However, internal fault actions
age exceeds the threshold value programmed on the VDSTH pin,
are unaffected and gate drive outputs are still disabled in response
the FAULT output is set high but none of the gate drive outputs is
to other faults in accordance with Table 2.
disabled.
Propagation of any fault states to the FAULT output is disabled Low Dropout (LDO) Regulator
for the VDS Fault Blank Time (tBL) commencing at every exter- The A4919x-3 and A4919x-5 variants have a linear regulator that
nal MOSFET turn-on event to avoid reporting spurious faults provides a low-voltage DC supply to power external circuitry.
in response to switching transients. If a fault is reported on the It is derived from VBB and incorporates a number of protection
FAULT pin it will be cleared as soon as the measured drain- features.
source voltage drops below the programmed VDSTH level.

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

An overcurrent circuit limits the output of the regulator in the At device power-up, full output current is delivered for a period
event of an excessively high load demand being made (load cur- equal to the Shutdown Lockout Period regardless of output volt-
rent > ILDOOC ). age to facilitate reliable regulator startup.
If the output voltage falls below the regulator undervoltage If the device internal temperature rises high enough to generate
threshold (VDDUV ), a fault state is flagged on the FAULT output an Overtemperature Warning (T > TJF), the regulator is immedi-
to provide an external warning, but device operation remains ately shut down and the FAULT flag is set. All device functions
otherwise unchanged. other than the regulator remain active. When the Overtemperature
Warning is cleared ( T < TJF – TJHyst ), the pilot current is turned
If the output voltage falls below the regulator shutdown thresh-
on and the regulator attempts to restart.
old (VLDOSD , which is lower than the regulator undervoltage
threshold) for a period exceeding the Shutdown Lockout Period If an undervoltage shutdown (< VLDOSD ) and an Overtemperature
(tLDOL ), the regulator is turned off but all other device func- Warning (T > TJF ) occur simultaneously, both must be cleared to
tions remain active. In this state a small pilot current (ILDOP), is allow the regulator to restart.
driven through the regulator output to detect load resistance. If
Internal device circuitry is not powered from the LDO regula-
the resultant voltage rises above the regulator shutdown threshold
tor and remains fully operational regardless of whether the LDO
plus hysteresis (VLDOSD + VLDOHys), the regulator immediately
regulator is running normally or is shut down.
attempts to restart.
As detailed in the Electrical Characteristics table, a minimum
capacitance must be connected between the LDO regulator output
and ground to ensure stability. Running the device with signifi-
cantly less than the stated minimum capacitance may result in
oscillation and voltage excursions exceeding the specified V3 or
V5 output voltage range. In some applications the use of redun-
dant output capacitors may be advisable to avoid such a condition
in the event of a single-point, capacitor-high-impedance failure.

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

APPLICATIONS INFORMATION

Power Bridge Management Using PWM on the bootstrap capacitor, QBOOT , should be much larger than
Control QGATE, the charge required by the gate:
The A4919 provides individual high-side and low-side controls QBOOT >> QGATE (1)
for each phase through the six digital control inputs. The only A factor of 20 is a reasonable value. CBOOT can then be calcu-
restriction imposed by the A4919 is to prevent both the high- lated as:
side and low-side gate drives of the same phase from being
QBOOT = CBOOT × VBOOT = QGATE × 20, or (2)
on at the same time, in order to avoid cross-conduction. This
CBOOT = (QGATE × 20) / VBOOT
design approach allows almost all 3-phase BLDC bridge control
schemes to be implemented. This includes fast and slow decay, where VBOOT is the voltage across the bootstrap capacitor.
synchronous rectification and diode rectification, and edge-
aligned and center-aligned PWM.
Figure 3A shows an example of the path of the bridge and load
current. In this example, the high-side MOSFETs are switched off
during the current decay time (PWM off-time) and load current
recirculates through the low-side MOSFETs. This is commonly
referred to as high-side chopping or high-side PWM. During
the PWM off-time, the complementary MOSFETs are turned A B C
on to short the body diode and provide synchronous rectifica-
tion. Figure 3A only shows one combination of phase states, but
the same principal applies to any of the possible phase states. Drive Recirculate
The same principal also applies when the low-side MOSFETs
Phase A B C Phase A B C
are turned off during the PWM off-time and the load current xH 1 1 0 xH 0 0 0
recirculates through the high-side MOSFETs as in Figure 3B. In xL
GHx
0
H
0
H
1
L
xL
GHx
1
L
1
L
1
L
this control scheme, the microcontroller has full control over the GLx L L H GLx H H H

current decay method, load current recirculation paths, braking,

and coasting. (A) High-side PWM with slow decay and synchronous rectification

The A4919 provides exceptional propagation delay matching

from logic input to gate drive output for high performance motor
control applications. These advanced applications usually require
high-resolution PWM control on each phase. This must be
provided by an external controller, which must also provide the A B C
necessary dead time to avoid shoot through in the power bridge.

Bootstrap Capacitor Selection Drive Recirculate

CBOOT must be correctly selected to ensure proper operation of Phase

xH
A
1
B
1
C
0
Phase
xH
A
1
B
1
C
1
the device. If it is too large, time will be wasted charging the xL 0 0 1 xL 0 0 0
GHx H H L GHx H H H
capacitor, resulting in a limit on the maximum duty cycle and GLx L L H GLx L L L
PWM frequency. If it is too small, there can be a large voltage
drop at the time the charge is transferred from CBOOT to the (B) Low-side PWM with slow decay and synchronous rectification
MOSFET gate.
To keep the voltage drop due to charge sharing small, the charge Figure 3: Power Bridge Control

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

The voltage drop, ∆V, across the bootstrap capacitor as the MOS- which can be several hundred milliamperes, cannot be provided
FET is being turned on can be approximated by: directly by the limited output of the VREG regulator but instead
∆V = QGATE / CBOOT (3) must be supplied by an external capacitor connected to VREG.
so for a factor of 20, ∆V will be 5% of VBOOT. The turn-on current for the high-side MOSFET is similar in
The maximum voltage across the bootstrap capacitor under value, but is mainly supplied by the bootstrap capacitor. How-
normal operating conditions is VREG (max). However, in some ever, the bootstrap capacitor must then be recharged from the
circumstances the voltage may transiently reach 18 V, which is VREG regulator output.
the clamp voltage of the Zener diode between the Cx terminal
and the Sx terminal. In most applications, with a good ceramic Unfortunately, the bootstrap recharge can occur a very short
capacitor the working voltage can be limited to 16 V. time after the low-side turn-on occurs. This means that the value
of the capacitor connected between VREG and GND should be
Bootstrap Charging high enough to minimize the transient voltage drop on VREG for
the combination of a low-side MOSFET turn-on and a bootstrap
It is good practice to ensure the high-side bootstrap capacitor is
capacitor recharge. For block commutation motor control, where
completely charged before a high-side PWM cycle is requested.
The time required to charge the capacitor, tCHARGE, in µs, is the number of MOSFETs switching at any one time is limited,
approximated by: a value of 20 × CBOOT is a reasonable value. For sinusoidal or
vector motor control (SVM), where several MOSFETs may be
tCHARGE = (CBOOT × ∆V ) / 500 (4)
switching at the same time, a value of 40 × CBOOT is recom-
Where CBOOT is the value of the bootstrap capacitor in nF and
mended. The maximum working voltage will never exceed VREG
∆V is the required voltage of the bootstrap capacitor.
so the capacitor can be rated as low as the terminal. This capaci-
At power‑up and when the drivers have been disabled for a long tor should be placed as close as possible to the VREG terminal.
time, the bootstrap capacitor can become completely discharged.
In this case, ∆V can be considered to be the full high-side drive
voltage, 12 V. Otherwise, ∆V is the amount of voltage dropped LDO Regulator Capacitor Selection
during the charge transfer, which should be 400 mV or less. The
capacitor is charged whenever the Sx terminal is pulled low and A capacitor of at least 1 µF, ESR < 250 mΩ should be connected
current flows from VREG through the internal bootstrap diode between the V3 / V5 pin and GND on A4919x-3 and A4919x-5
circuit to CBOOT . variants to ensure LDO stability.

VREG Capacitor Selection Supply Decoupling

The internal reference, VREG , supplies current for the low-side
The switching action associated with device operation will result
gate-drive circuits and the charging current for the bootstrap
capacitors. When a low-side MOSFET is turned on, the gate- in current spikes on VBB at each transition. Consequently, VBB
drive circuit will provide the high, transient current to the gate should be decoupled to GND with a ceramic capacitor, typically
that is necessary to turn the MOSFET on quickly. This current, 220 nF, mounted as close to the A4919 pins as possible.

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

Cx

18V VBRG VBB

20V
GHx
20V

14V CP1 CP2 VDDM / V3 / V5 VREG

Sx 7.5V

VREG
20V 20V
8V 60kΩ
18V 20V 20V 18V
18V 6V
18V GLx
18V 14V

LSS

Figure 4a: Gate Drive Outputs Figure 4b: Supplies

4.5V(max)

xHI 2kΩ 4kΩ 25Ω

xLO VDSTH FAULT

50kΩ
6V 6V 6V 6V 6V

F i gure 4c: xHI,xLO Inputs F i gure 4d: VDSTH Input F i gure 4e: FAULT Outpu t

Figure 4: Input / Output Structures

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

LAYOUT RECOMMENDATIONS

Optional reverse
power supply protection

VBB VBRG
+ Supply
VREG GHC
GHB
GHA
VDDM/
V3/
V5 SA
SB Motor
SC
A4919
GLA
VDSTH GLB
GLC

LSS
GND TAB
RS
Optional components to
limit LSS transients Supply
Power Ground
Common
Controller Supply

Figure 5: Supply Routing Suggestions

Careful consideration must be given to PCB layout when design- located as close to the device pins as possible. All connections
ing high frequency, fast-switching, high-current circuits: should take the form of short, dedicated traces. If VDSTH is
directly strapped to a logic supply or GND, this should similarly
• The A4919 ground, GND, and the high-current return of the
be by way of a short, dedicated trace.
external MOSFETs should return separately to the negative side
of the motor supply filtering (DC-link) capacitor. This will mini- • Check the peak voltage excursion of the transients on the LSS
mize the effect of bridge switching noise on the A4919. terminal with reference to the GND terminal using a close-
grounded (tip and barrel) probe. If the voltage at LSS exceeds the
• The exposed thermal pad should be connected to GND.
absolute maximum in the datasheet, add additional clamping and/
• Minimize stray inductance by using short, wide copper PCB or capacitance between the LSS terminal and the GND terminal
traces at the drain and source terminals of all power MOSFETs. as shown.
This includes motor lead connections, the input power bus, and
• Gate charge drive paths and gate discharge return paths may
the common source of the low-side power MOSFETs. This will
carry a large transient current pulse. Therefore the traces from
minimize voltages induced by fast switching of large load cur-
GHx, GLx, Sx (x = A, B or C) and LSS should be a short as pos-
rents.
sible to minimize trace inductance.
• Consider the use of small (100 nF) ceramic decoupling capaci-
• Provide an independent connection from LSS to the common
tors across the source and drain of the power MOSFETs to limit
point of the power bridge. It is not recommended to connect LSS
fast transient voltage spikes caused by circuit trace inductance.
directly to the GND terminal as this may inject noise into sensi-
• Keep the gate discharge return connections Sx and LSS as short tive functions such as the various voltage monitors.
as possible. Any inductance on these traces will cause negative
• A low cost diode can be placed in the connection to VBB to
transitions on the corresponding A4919 terminals, which may
provide reverse power supply protection. In reverse power sup-
exceed the absolute maximum ratings. If this is likely, consider
ply conditions it is possible to use the body diodes of the power
the use of clamping diodes to limit the negative excursion on
MOSFETs to clamp the reverse voltage to approximately 4 V. In
these terminals with respect to GND.
this case the additional diode in the VBB connection will prevent
• The threshold programming network associated with the damage to the A4919 and the VBRG terminal will survive the
VDSTH input, including suitable supply decoupling, should be reverse voltage.

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

PACKAGE OUTLINE DRAWINGS

For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000379, Rev. 3 and JEDEC MO-153AET)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

9.70 ±0.10

5.40 MAX
4.98 MIN 8º
0º
28
0.20
0.09

B
3.20 MAX 4.40±0.10 6.40±0.20
2.80 MIN

0.60 ±0.15 1.00 REF

1 2
Branded Face
0.25 BSC
28× C
1.20 MAX
0.10 C SEATING SEATING PLANE
PLANE GAUGE PLANE
0.30 0.65 BSC 0.15
0.19 0.025
0.45 0.65
28 XXXXXXX
Date Code
1.65
Lot Number

D Standard Branding Reference View

3.20 6.10 Lines 1, 2, 3 = 10 characters

Line 1: Part Number

Line 2: Logo A, 4-digit Date Code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number

A Terminal #1 mark area

B Exposed thermal pad (bottom surface)
1 2
C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
5.40 All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
C PCB Layout Reference View mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Branding scale and appearance at supplier discretion.

Figure 6: Package LP, 28-Pin TSSOP with Exposed Thermal Pad

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A4919 Three-Phase MOSFET Driver with Integrated Regulator

0.30
5.00 BSC
1.15 28 0.50
28

1
2 A 1
0.15 C 2×

5.00 BSC 3.15 4.80

0.15 C 2×
3.15
29× D C
4.80
0.08 C SEATING
PLANE C PCB Layout Reference View
+0.05
0.25 –0.07 0.90 ±0.10
0.50

0.55
B
3.15
XXXX
2 Date Code
1 Lot Number

28
E Standard Branding Reference View 1
3.15
Line 1: Part Number
Line 2: Logo A, 4-Digit Date Code
Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number
For Reference Only; not for tooling use
(reference DWG-0000378, Rev. 3)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals

E Branding scale and appearance at supplier discretion

Figure 7: Package ET, 28-Terminal QFN with Exposed Thermal Pad

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Manchester, NH 03103-3353 U.S.A.
[Link]
A4919 Three-Phase MOSFET Driver with Integrated Regulator

Revision History
Revision Description of Revision Pages Responsible Revision Date
– Initial Release All A. Wood April 14, 2014
Added VGDD spec and new Input Low Voltage for Sleep Mode; 7, 9, 10,
1 (was 0.1) A. Wood November 11, 2014
ammended VDDM description 12, 13
2 Updated Electrical Characteristics test conditions in table headers 6-8 A. Wood January 4, 2017
3 Editorial update All R. Couture October 24, 2017
Updated VDSTHI min/max values; corrected typos in Sleep Mode 1, 2, 8,
4 S. Ehara January 16, 2018
section; added ET package option 11, 21
5 Minor editorial updates All R. Couture January 25, 2019
6 Minor editorial updates All R. Couture January 31, 2020
7 Updated LP package drawing 20 A. Wang November 9, 2021
8 Updated package drawings 20-21 R. Couture November 7, 2022

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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
[Link]