TPS5450

SLVS757E – MARCH 2007 – REVISED JULY 2022

TPS5450 5-A, Wide Input Range, Step-Down Converter

1 Features 3 Description
• Wide input voltage range: 5.5 V to 36 V The TPS5450 is a high-output-current PWM converter
• Up to 5-A continuous (6-A peak) output current that integrates a low-resistance, high-side N-channel
• High efficiency greater than 90% enabled by 110- MOSFET. Included on the substrate with the
mΩ integrated MOSFET switch listed features are a high-performance voltage
• Wide output voltage range: adjustable down to error amplifier that provides tight voltage regulation
1.22 V with 1.5% initial accuracy accuracy under transient conditions; an undervoltage-
• Internal compensation minimizes external part lockout circuit to prevent start-up until the input
count voltage reaches 5.5 V; an internally set slow-start
• Fixed 500-kHz switching frequency for small filter circuit to limit inrush currents; and a voltage feed-
size forward circuit to improve the transient response.
• 18-μA shutdown supply current Using the ENA pin, shutdown supply current is
• Improved line regulation and transient response by reduced to 18 μA typically. Other features include an
input voltage feedforward active-high enable, overcurrent limiting, overvoltage
• System protected by overcurrent limiting, protection and thermal shutdown. To reduce design
overvoltage protection, and thermal shutdown complexity and external component count, the
• –40°C to 125°C operating junction temperature TPS5450 feedback loop is internally compensated.
range
The TPS5450 device is available in a thermally-
• Available in small thermally enhanced 8-pin SOIC
enhanced, 8-pin SOIC PowerPAD package. TI
PowerPAD™ package
provides evaluation modules and software tool to aid
2 Applications in achieving high-performance power supply designs
to meet aggressive equipment development cycles.
• High density point-of-load regulators
• LCD displays, plasma displays Device Information(1)
• Battery chargers PART NUMBER PACKAGE BODY SIZE (NOM)
• 12-V and 24-V distributed power systems TPS5450 HSOP (8) 4.89 mm × 3.90 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.
Simplified Schematic Efficiency vs Output Current

100
VIN VOUT
VIN PH 95

90
85
BOOT
Efficiency - %

NC
80
NC 75

70
ENA VSENSE
65 VI = 12 V,
GND VO = 5 V,
60
fs = 500 kHz,
55 TA = 25°C
50
0 1 2 3 4 5 6
IO - Output Current - A

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS5450
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................11
2 Applications..................................................................... 1 8 Application and Implementation.................................. 12
3 Description.......................................................................1 8.1 Application Information............................................. 12
4 Revision History.............................................................. 2 8.2 Typical Application.................................................... 12
5 Pin Configuration and Functions...................................3 9 Power Supply Recommendations................................19
Pin Functions.................................................................... 3 10 Layout...........................................................................19
6 Specifications.................................................................. 4 10.1 Layout Guidelines................................................... 19
6.1 Absolute Maximum Ratings........................................ 4 10.2 Layout Example...................................................... 20
6.2 ESD Ratings............................................................... 4 10.3 Thermal Calculations.............................................. 21
6.3 Recommended Operating Conditions.........................4 11 Device and Documentation Support..........................22
6.4 Thermal Information....................................................4 11.1 Device Support........................................................22
6.5 Electrical Characteristics.............................................6 11.2 Trademarks............................................................. 22
6.6 Typical Characteristics................................................ 7 11.3 Electrostatic Discharge Caution.............................. 22
7 Detailed Description........................................................9 11.4 Glossary.................................................................. 22
7.1 Overview..................................................................... 9 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram........................................... 9 Information.................................................................... 22
7.3 Feature Description...................................................10

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2014) to Revision E (July 2022) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Changes from Revision C (October 2013) to Revision D (September 2014) Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1

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5 Pin Configuration and Functions

DDA PACKAGE
(TOP VIEW)

BOOT 1 8 PH

NC 2 PowerPAD 7 VIN
(Pin 9)
NC 3 6 GND

VSENSE 4 5 ENA

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Boost capacitor for the high-side FET gate driver. Connect 0.01-μF, low-ESR capacitor from BOOT pin to PH
BOOT 1 O
pin.
NC 2, 3 – Not connected internally.
VSENSE 4 I Feedback voltage for the regulator. Connect to output voltage divider.
ENA 5 I On and off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND 6 – Ground. Connect to PowerPAD.
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality, low-ESR
VIN 7 I
ceramic capacitor.
PH 8 O Source of the high-side power MOSFET. Connected to external inductor and diode.
PowerPAD 9 – GND pin must be connected to the exposed pad for proper operation.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
V Voltage VIN –0.3 40(2) V
PH (steady-state) –0.6 40(2)
PH (transient < 10 ns) –1.2
ENA –0.3 7
BOOT-PH –0.3 10
VSENSE –0.3 3
IO Source current PH Internally Limited
Ilkg Leakage current PH 10 μA
TJ Operating virtual junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Section 6.1 may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum
rating.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±1500 V
C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VI Input voltage range 5.5 36 V
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

TPS5450
THERMAL METRIC(1) (2) (3) DDA UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance (custom board) (4) 30
RθJA Junction-to-ambient thermal resistance (standard board) 42.3
ψJT Junction-to-top characterization parameter 4.9
ψJB Junction-to-board characterization parameter 20.7 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 46.4
RθJC(bot) Junction-to-case(bottom) thermal resistance 0.8
RθJB Junction-to-board thermal resistance 20.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Maximum power dissipation may be limited by overcurrent protection
(3) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Section 10.3 for more information.

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(4) Test boards conditions:

a. 2 in x 1.85 in, 4 layers, thickness: 0.062 inch (1.57 mm).
b. 2 oz. copper traces located on the top of the PCB
c. 2 oz. copper ground planes on the 2 internal layers and bottom layer
d. 4 thermal vias (10mil) located under the device package

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6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 5.5 V - 36 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VSENSE = 2 V, Not switching,
3 4.4 mA
IQ Quiescent current PH pin open
Shutdown, ENA = 0 V 18 50 μA
UNDERVOLTAGE LOCK OUT (UVLO)
Start threshold voltage, UVLO 5.3 5.5 V
Hysteresis voltage, UVLO 330 mV
VOLTAGE REFERENCE
TJ = 25°C 1.202 1.221 1.239
Voltage reference accuracy V
IO = 0 A – 5 A 1.196 1.221 1.245
OSCILLATOR
Internally set free-running frequency 400 500 600 kHz
Minimum controllable on time 150 200 ns
Maximum duty cycle 87% 89%
ENABLE (ENA PIN)
Start threshold voltage, ENA 1.3 V
Stop threshold voltage, ENA 0.5 V
Hysteresis voltage, ENA 450 mV
Internal slow-start time (0~100%) 6.6 8 10 ms
CURRENT LIMIT
Current limit 6.0 7.5 9.0 A
Current limit hiccup time 13 16 20 ms
THERMAL SHUTDOWN
Thermal shutdown trip point 135 162 °C
Thermal shutdown hysteresis 14 °C
OUTPUT MOSFET
VIN = 5.5 V 150
rDS(on) High-side power MOSFET switch mΩ
110 230

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6.6 Typical Characteristics

530 3.5
VI = 12 V

520
f − Oscillator Frequency − kHz

I Q−Quiescent Current −mA

3.25
510

500
3
490

480
2.75

470

460 2.5
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
T − Junction Temperature − °C T J −Junction T emperature − °C

Figure 6-1. Oscillator Frequency vs Junction Figure 6-2. Non-Switching Quiescent Current vs
Temperature Junction Temperature
25 1.230
ENA = 0 V
−µ A

VREF - Voltage Reference - V

20 T J = 125°C 1.225
I SD −Shutdown Current

15 T J = 27°C 1.220

T J = –40°C
10 1.215

5 1.210
0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125
V I −Input V oltage −V TJ - Junction Temperature - °C

Figure 6-3. Shutdown Quiescent Current vs Input Figure 6-4. Voltage Reference vs Junction
Voltage Temperature
180 9
V I = 12 V
170
TSS − Internal Slow Start Time − ms
DS(on) −On Resistance −mΩ

160
8.5
150

140

130 8

120

110
7.5
r

100

90

80 7
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
T J −Junction Temperature − °C TJ − Junction Temperature − °C

Figure 6-5. On Resistance vs Junction Figure 6-6. Internal Slow Start Time vs Junction
Temperature Temperature

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180 8

Minimum Controllable On Time − ns

170

7.75

Minimum Duty Ratio - %

160

150 7.50

140

7.25
130

120 7
−50 −25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
TJ − Junction Temperature − °C TJ - Junction Temperature - °C

Figure 6-7. Minimum Controllable On Time vs Figure 6-8. Minimum Controllable Duty Ratio vs
Junction Temperature Junction Temperature

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7 Detailed Description
7.1 Overview
The TPS5450 device is a 36-V, 5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET.
The device implements constant-frequency voltage-mode control with voltage feed forward for improved
line regulation and line transient response. Internal compensation reduces design complexity and external
component count.
The integrated 110-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
5-A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied
by a bootstrap capacitor connected from the BOOT to PH pins. The TPS5450 device reduces the external
component count by integrating the bootstrap recharge diode.
The TPS5450 device has a default input start-up voltage of 5.3 V typical. The ENA pin can be used to disable
the TPS5450 reducing the supply current to 18 µA. An internal pullup current source enables operation when
the EN pin is floating. The TPS5450 includes an internal slow-start circuit that slows the output rise time during
start-up to reduce in rush current and output voltage overshoot.
The minimum output voltage is the internal 1.221-V feedback reference. Output overvoltage transients are
minimized by an Overvoltage Protection (OVP) comparator. When the OVP comparator is activated, the high-
side MOSFET is turned off and remains off until the output voltage is less than 112.5% of the desired output
voltage.
Internal cycle-by-cycle overcurrent protection limits the peak current in the integrated high-side MOSFET. For
continuous overcurrent fault conditions the TPS5450 will enter hiccup mode overcurrent limiting. Thermal
protection protects the device from overheating.
7.2 Functional Block Diagram
VIN

VIN

1.221 V Bandgap VREF SHDN Boot

UVLO Slow Start Regulator BOOT
Reference
HICCUP
5 µA
ENA ENABLE SHDN SHDN
VSENSE
Z1

Thermal
SHDN Error
Protection SHDN Z2
Amplifier

Ramp
NC VIN
Generator Feed Forward
Gain = 25

NC PWM HICCUP
SHDN
Comparator

GND Overcurrent
SHDN Oscillator Protection

SHDN
Gate Drive
VSENSE OVP Control
POWERPAD 112.5% VREF Gate
Driver
SHDN

BOOT PH

VOUT

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7.3 Feature Description

7.3.1 Oscillator Frequency
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.
7.3.2 Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable band-gap circuit. The band-gap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.
7.3.3 Enable (ENA) and Internal Slow-Start
The ENA pin provides electrical on and off control of the regulator. Once the ENA pin voltage exceeds the
threshold voltage, the regulator starts operation and the internal slow-start begins to ramp. If the ENA pin voltage
is pulled below the threshold voltage, the regulator stops switching and the internal slow-start resets. Connecting
the pin-to-ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode.
The quiescent current of the TPS5450 in shutdown mode is typically 18 μA.
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open-drain or open-collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its
final value, linearly. The internal slow-start time is 8 ms typically.
7.3.4 Undervoltage Lockout (UVLO)
The TPS5450 incorporates an UVLO circuit to keep the device disabled when VIN (the input voltage) is below
the UVLO start voltage threshold. During power-up, internal circuits are held inactive and the internal slow-start
is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is
reached, the internal slow-start is released and device start-up begins. The device operates until VIN falls below
the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
7.3.5 Boost Capacitor (BOOT)
Connect a 0.01-μF, low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate-drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
7.3.6 Output Feedback (VSENSE) and Internal Compensation
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
The TPS5450 implements internal compensation to simplify the regulator design. Since the TPS5450 uses
voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See the Section [Link].2 for more details.
7.3.7 Voltage Feed-Forward
The internal voltage feed-forward provides a constant DC power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed-forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed-forward gain, that is.

Feed Forward Gain = VIN

Ramp
pk – pk (1)

The typical feed-forward gain of TPS5450 is 25.

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7.3.8 Pulse-Width-Modulation (PWM) Control

The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high-gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by
the PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty
cycle. Finally, the PWM output is fed into the gate-drive circuit to control the on-time of the high-side MOSFET.
7.3.9 Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid
any turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen
when using cycle-by-cycle current limiting. A second mode of current limiting is used, that is, hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-
side MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts
under control of the slow-start circuit.
7.3.10 Overvoltage Protection
The TPS5450 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from
output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage
and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side
MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side
MOSFET will be enabled again.
7.3.11 Thermal Shutdown
The TPS5450 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow-start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
7.4 Device Functional Modes
7.4.1 Operation near Minimum Input Voltage
The device is recommended to operate with input voltages above 5.5 V. The typical VIN UVLO threshold is
5.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the
actual UVLO voltage the device will not switch. If EN is floating or externally pulled up to greater up than 1.3 V,
when V(VIN) passes the UVLO threshold the device will become active. Switching is enabled and the slow-start
sequence is initiated. The TPS5450 device starts linearly ramping up the internal reference voltage from 0 V to
its final value over the internal slow-start time.
7.4.2 Operation With ENA Control
The enable start threshold voltage is 1.3 V maximum. With ENA held below the 0.5-V minimum stop threshold
voltage the device is disabled and switching is inhibited even if VIN is above its UVLO threshold. The IC
quiescent current is reduced in this state. If he EN voltage is increased above the threshold while VIN is above
its UVLO threshold, the device becomes active. Switching is enabled and the slow-start sequence is initiated.
The TPS5450 device starts linearly ramping up the internal reference voltage from 0 V to its final value over the
internal slow-start time.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The TPS5450 device is a 36-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device
is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output
current of 5 A. Example applications are: High Density Point-of-Load Regulators, LCD and Plasma Displays,
Battery Chargers, and 12-V and 24-V Distributed Power Systems. Use the following design procedure to select
component values for the TPS5450 device. This procedure illustrates the design of a high-frequency switching
regulator.
8.2 Typical Application
Figure 8-1 shows the schematic for a typical TPS5450 application. The TPS5450 can provide up to 5-A output
current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD underneath
the device must be soldered down to the printed-circuit board.

Figure 8-1. Application Circuit, 12 V to 5.0 V

8.2.1 Design Requirements

To begin the design process a few parameters must be decided upon. These requirements are typically
determined at the system levels. This example is designed to the following known parameters:
Table 8-1. Design Parameters
DESIGN PARAMETER(1) EXAMPLE VALUE
Input voltage range 10 V to 31 V
Output voltage 5V
Input ripple voltage 400 mV
Output ripple voltage 30 mV
Output current rating 5A
Operating frequency 500 kHz

(1) As an additional constraint, the design is set up to be small size and low component height.

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8.2.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS5450. Alternately, use
the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
[Link] Switching Frequency
The switching frequency for the TPS5450 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.
[Link] Output Voltage Setpoint
The output voltage of the TPS5450 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 2:

(2)

For any TPS5450 design, start with an R1 value of 10 kΩ. For an output voltage closest to but at least 5 V, R2 is
3.16 kΩ.
[Link] Input Capacitors
The TPS5450 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The minimum recommended decoupling capacitance is 4.7 μF. A high-quality ceramic type X5R or X7R is
required. For some applications, a smaller value decoupling capacitor may be used, so long as the input voltage
and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple.
This input ripple voltage can be approximated by Equation 3:

I OUT(MAX) × 0.25
ΔVIN = = I OUT(MAX) × ESR MAX
C BULK × ƒsw (3)

where
• IOUT(MAX) is the maximum load current
• f SW is the switching frequency
• CIN is the input capacitor value
• ESRMAX is the maximum series resistance of the input capacitor
For this design, the input capacitance consists of two 4.7-μF capacitors, C1 and C4, in parallel. An additional
high frequency bypass capacitor, C5 is also used.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 4:

I
OUT(MAX)
I =
CIN 2 (4)

In this case the input ripple voltage would be 281 mV and the RMS ripple current would be 2.5 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor
is rated for 50 V and the ripple current capacity is greater than 2.5 A each, providing ample margin. It is very
important that the maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance may be needed, especially if the TPS5450 circuit is not located within about
2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to

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handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage
is acceptable.
[Link] Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Since the TPS5450 is an internally
compensated device, a limited range of filter component types and values can be supported.
[Link] Inductor Selection
To calculate the minimum value of the output inductor, use Equation 5:

L =
V
OUT(MAX) × VIN(MAX)
– V
OUT ( )
MIN V ×K ×I ×F
IN(MAX) IND OUT SW(MIN) (5)

KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the peak
to peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch
current and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs
using the TPS5450, KIND of 0.2 to 0.3 yields good results. Low-output ripple voltages can be obtained when
paired with the proper output capacitor, the peak switch current will be well below the current limit set point and
relatively low-load currents can be sourced before discontinuous operation.
For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 10.4 μH. A higher
standard value is 15 μH, which is used in this design.
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 6:

I
L(RMS)
+ Ǹ I2 )
1
OUT(MAX) 12 ǒ V
V
OUT
IN(MAX)
ǒVIN(MAX) * VOUTǓ
L
OUT
F Ǔ
SW(MIN)
2

(6)

The peak inductor current can be determined with Equation 7:

V
OUT
ǒVIN(MAX) * VOUTǓ
I L(PK) + I )
OUT(MAX) 1.6 V IN(MAX) L F
OUT SW(MIN) (7)

For this design, the RMS inductor current is 5.004 A, and the peak inductor current is 5.34 A. The chosen
inductor is a Sumida CDRH1127/LD-150 15μH. It has a minimum rated current of 5.65 A for both saturation and
RMS current. In general, inductor values for use with the TPS5450 are in the range of 10 μH to 100 μH.
[Link] Capacitor Selection
The important design factors for the output capacitor are DC voltage rating, ripple current rating, and equivalent
series resistance (ESR). The DC voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value
of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the
desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
design of the internal compensation, it is desirable to keep the closed-loop crossover frequency in the range 3
kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed-loop crossover frequency will be between 2590 Hz and 24
kHz and also below the ESR zero of the output capacitor. Under these conditions the closed-loop crossover
frequency is related to the LC corner frequency by:

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[Link] SLVS757E – MARCH 2007 – REVISED JULY 2022

2
f LC
f CO +
85 VOUT
(8)

And the desired output capacitor value for the output filter to:

C OUT + 1
3357 L OUT f CO V OUT
(9)

For a desired crossover of 12 kHz and a 15-μH inductor, the calculated value for the output capacitor is 330
μF. The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR
should be:

ESR MAX + 1
2p C OUT f CO
(10)

The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage:

ESRMAX x VOUT x ( VIN(MAX) - VOUT )

VPP (MAX) =
NC x VIN(MAX) x LOUT x FSW
(11)

where
• ΔVPP is the desired peak-to-peak output ripple.
• NC is the number of parallel output capacitors.
• FSW is the switching frequency.
For this design example, a single 330-μF output capacitor is chosen for C3. The calculated RMS ripple current
is 143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB330M, rated at 10 V with a maximum ESR of 35 mΩ and a ripple current rating of 3 A. An
additional small 0.1-μF ceramic bypass capacitor, C6 is also used in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and 54
kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 12:

ICOUT(RMS) = 1
√12
× (
V
V
OUT ×
IN(MAX)
( VIN(MAX) –
×L
OUT
×F
SW
V
OUT
×N
C
)
) (12)

where
• NC is the number of output capacitors in parallel.
• FSW is the switching frequency.
Other capacitor types can be used with the TPS5450, depending on the needs of the application.
[Link] Boot Capacitor
The boot capacitor should be 0.01 μF.

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[Link] Catch Diode

The TPS5450 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the peak
to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that
the catch diode conduction time is typically longer than the high-side FET on-time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B540A is chosen, with a reverse voltage
of 40 V, forward current of 5 A, and a forward voltage drop of 0.5 V.
[Link] Advanced Information
[Link].1 Output Voltage Limitations
Due to the internal design of the TPS5450, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:

V OUTMAX + 0.87 ǒǒVINMIN * I OMAX Ǔ Ǔ ǒ

0.230 ) VD * I OMAX Ǔ
RL * VD
(13)

where
• VINMIN = minimum input voltage
• IOMAX = maximum load current
• VD = catch diode forward voltage.
• RL= output inductor series resistance.
This equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:

V OUTMIN + 0.12 ǒǒVINMAX * I OMIN Ǔ Ǔ ǒ

0.110 ) VD * I OMIN Ǔ
RL * VD
(14)

where
• VINMAX = maximum input voltage
• IOMIN = minimum load current
• VD = catch diode forward voltage.
• RL= output inductor series resistance.
This equation assumes nominal on resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be carefully
checked to assure proper functionality.
[Link].2 Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the TPS5450. These
designs are based on certain assumptions and will tend to always select output capacitors within a limited
range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal
compensation of the TPS5450. Equation 15 gives the nominal frequency response of the internal voltage-mode
type III compensation network:

ǒ1 ) 2p s Ǔ ǒ1 ) 2p
Fz1
s
Fz2
Ǔ
H(s) +
ǒ2p sFp0Ǔ ǒ1 ) 2p sFp1Ǔ ǒ1 ) 2p sFp2Ǔ ǒ1 ) 2p sFp3Ǔ
(15)

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where
• Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
• Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
• Fp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed-forward gain and output filter characteristics,
the closed-loop transfer function can be derived.

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8.2.3 Application Curves

The performance graphs (Figure 8-2 through Figure 8-8) are applicable to the circuit in Figure 8-1. TA = 25°C.
unless otherwise specified.

100 0.3

VI = 12 V 0.2
95
VI = 15 V

Output Regulation - %
0.1
Efficiency - %

90

0
VI = 28 V
85 VI = 24 V

-0.1

80
-0.2

75 -0.3
0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IO - Output Current - A IO - Output Current - A

Figure 8-2. Efficiency vs. Output Current Figure 8-3. Output Regulation % vs. Output
Current
0.3
VI = 200 mV/Div (AC Coupled)

0.2

IO = 0 A
Output Regulation - %

0.1
IO = 5 A

0
PH = 10 V/Div
IO = 2.5 A
-0.1

-0.2

-0.3
10 13 16 19 22 25 28 31
VI - Input Voltage - V t - Time - 1 ms/Div

Figure 8-4. Output Regulation % vs. Input Voltage Figure 8-5. Input Voltage Ripple and PH Node, IO =
5 A.
VOUT = 50 mV/div (AC Coupled, 20 MHz BWL)

VOUT = 50 mV/div (AC Coupled, 20 MHz BWL)

VPH = 10 V/div IOUT = 1 A/div

t - Time = 1 ms/div t - Time = 100 ms/div

Figure 8-6. Output Voltage Ripple and PH Node, IO Figure 8-7. Transient Response, IO Step 1.25 to
=5A 3.75 A.

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125

TJ - Junction Temperature - °C
100

75

50

25
0 0.5 1 1.5 2 2.5 3 3.5
IC Power Dissipation - W

Figure 8-8. TPS5450 Power Dissipation vs Junction Temperature.

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 5.5 V and 36 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS5450 converter
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
Connect a low-ESR ceramic bypass capacitor to the VIN pin. Take care to minimize the loop area formed by the
bypass capacitor connections, the VIN pin, and the TPS5450 ground pin. The best way to do this is to extend the
top-side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor as close
as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7-μF ceramic with a X5R or
X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown below.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very close to the PH pin and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device
to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT
pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.
If using the grounding scheme shown in Figure 10-1, use a via connection to a different layer to route to the ENA
pin.

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TPS5450
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10.2 Layout Example

Feedback Trace

BOOT OUTPUT
CAPACITOR INDUCTOR

INPUT Vout
EXPOSED BYPASS
BOOT POWERPAD
AREA
PH CAPACITOR PH Vin
NC VIN

NC GND OUTPUT
FILTER
CATCH CAPACITOR
VSENSE ENA DIODE
Route INPUT VOLTAGE
trace under the catch diode
and output capacitor
RESISTOR
or on another layer
DIVIDER TOPSIDE GROUND AREA

Signal VIA
Figure 10-1. Design Layout

0,45 1,27

2,15

3,10 2,49 5,75

Figure 10-2. TPS5450 Land Pattern

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 TPS5450
[Link] SLVS757E – MARCH 2007 – REVISED JULY 2022

10.3 Thermal Calculations

The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction Loss: Pcon = IOUT 2 x RDS(on) x VOUT/VIN
Switching Loss: Psw = VIN x IOUT x 0.01
Quiescent Current Loss: Pq = VIN x 0.01
Total Loss: Ptot = Pcon + Psw + Pq
Given TA → Estimated Junction Temperature: TJ = TA + Rth x Ptot
Given TJMAX = 125°C → Estimated Maximum Ambient Temperature: TAMAX = TJMAX – Rth x Ptot

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11 Device and Documentation Support

11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 7-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS5450DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5450 Samples

TPS5450DDAG4 ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5450 Samples

TPS5450DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5450 Samples

TPS5450DDARG4 ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5450 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 7-Apr-2024

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS5450 :

• Automotive : TPS5450-Q1
• Enhanced Product : TPS5450-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 8-Apr-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS5450DDA DDA HSOIC 8 75 506.6 8 3940 4.32
TPS5450DDAG4 DDA HSOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 1
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.1 0.25
2.5 GAGE PLANE

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0

4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.

[Link]
 EXAMPLE BOARD LAYOUT
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9

6X (1.27)

5
4

( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK

(1.3) TYP

(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221637/B 03/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 ([Link]/lit/slma002) and SLMA004 ([Link]/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.

[Link]
 EXAMPLE STENCIL DESIGN
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8

8X (0.6)

(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED SEE TABLE FOR

SYMM DIFFERENT OPENINGS
BY SOLDER MASK
FOR OTHER STENCIL
THICKNESSES
(5.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.91 X 3.47
0.125 2.6 X 3.1 (SHOWN)
0.150 2.37 X 2.83
0.175 2.20 X 2.62

4221637/B 03/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

[Link]
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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