Microprocessor I

Chapter 0 – Overview of Logic Circuit Design

Dr. Mohamad Mroué

Lebanese University - Faculty of Engineering

Beirut, Lebanon
1
Digital Circuits Advantages
Better immunity to noise

Easier to implement with IC techniques

More “adaptable” to variable uses

Design is done at a more abstract level

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Types of digital circuits
 Logic systems are classified into two types:
‒ Combinational Logic system: The output at any time depends only
on the current combination of its input values (memoryless
system)
‒ Sequential Logic system: The output at any time depends not only
on its current inputs but also the past sequence of inputs that
have been applied to it (system with memory)

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Types of digital circuits - Examples
 Combinational Logic Blocks:
‒ Multiplexers, DeMultiplexers, Decoders, Encoders, Three-State
Buffers, ROM memories, Multipliers, Adders, …

 Sequential Logic Blocks:

‒ Latches and Flip-Flops, Registers, Shift Registers, Counters, FIFO
and RAM memories, Sequential Multipliers, Sequential Adders, ...
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Combinational Logic
 A combinational logic system is one whose current outputs depend
only on its current inputs

x1 y1
… …
xn ym

 Combinational systems are memory-less. They do not contain

feedback loops.
‒ A feedback loop is a signal path that allows the output signal of a
system to propagate back to the input of the system.

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Analysis and Design of combinational logic systems

 Goal: analysis and design of logic functions whose current

outputs depends only on their current inputs

‒ Represent each of the inputs and outputs as binary patterns

‒ Formalize the function specification of the system in the form of a

table or an algebraic expression

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NOT, AND, OR
X Y
0 1
1 0

XY Z
00 0
01 0
10 0
11 1

XY Z
00 0
01 1
10 1
11 1

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Minimizing logic function

 The goal of digital design is to come out with a circuit that

implements the given logic function with minimum number of logic
gates.

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Which realization is best?
 Reduce number of inputs
‒ literal: input variable (complemented or not)
• The cost of logic gate can be approximated as 2 transistors per literal
‒ fewer literals means smaller gates
• smaller gates means less transistors
‒ fewer inputs implies faster gates
• gates are smaller and thus also faster
‒ fan-ins (# of gate inputs) are limited in some technologies

 Reduce number of gates

‒ fewer gates (and the packages they come in) means smaller circuits
• directly influences manufacturing costs

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Which realization is best?
 Reduce number of levels of gates
‒ fewer level of gates implies reduced signal propagation delays

 How do we explore tradeoffs between increased circuit delay and

size?
‒ automated tools to generate different solutions
‒ logic minimization: reduce number of gates and complexity
‒ logic optimization: reduction while trading off against delay

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Combinational Logic Blocks: Multiplexers
 A multiplexer (MUX for short) is a digital switch:
‒ it passes (connects) one of its data inputs to the output.
‒ the data input selected is a function of a set of control inputs called
selection inputs.
A Z I1 I0 A Z
0 I0 0 0 0 0
1 I1 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
Two alternative forms 1 1 0 1
for a 2:1 Mux truth table 1 1 1 1

Z = A' I0 + A I1

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Combinational Logic Blocks: Multiplexers
 Multiplexers

2 n 1
Z   mk I k
k 0

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Combinational Logic Blocks: Multiplexers
 Gate level implementation of multiplexers

– 2:1 mux

– 4:1 mux

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Combinational Logic Blocks: Multiplexers
 Cascading multiplexers
‒ Large multiplexers can be made by cascading smaller ones

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Combinational Logic Blocks: Multiplexers
 Multiplexers as general-purpose logic

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Combinational Logic Blocks: Multiplexers
 Multiplexer with bus inputs and outputs

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Combinational Logic Blocks: DeMultiplexers
 Demultiplexers

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Combinational Logic Blocks: Three-State Buffers
 Three-State Buffers

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Combinational Logic Blocks: Three-State Buffers
 Three-State Buffers

When the enable B is 1, the output C equals A.

When the enable B is 0, the output C acts like an open circuit.
In this case the output C is effectively disconnected from the
buffer output so that no current can flow.
This is often referred as Hi-Z (high-impedance) state because
the circuit offers a very high impedance to the flow of current.

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Combinational Logic Blocks: Three-State Buffers
 Tri-State Buffers application examples

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Combinational Logic Blocks: Three-State Buffers
 Tri-State Buffers application examples

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Combinational Logic Blocks: Three-State Buffers
 Tri-State Buffers application examples

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Combinational Logic Blocks: Decoders
 Decoders

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Combinational Logic Blocks: Decoders
 Decoders

A 4-to-10 Line Decoder

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Combinational Logic Blocks: Decoders
 Decoders

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Combinational Logic Blocks: Decoders
 Gate level implementation of decoders

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Combinational Logic Blocks: Decoders
 Decoders as general-purpose logic

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Combinational Logic Blocks: Decoders
 Decoders as general-purpose logic

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Combinational Logic Blocks: Encoders
 Encoders

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Combinational Logic Blocks: Encoders
 8-to-3 Priority Coder

y0 y1 y2 y3 y4 y5 y6 y7 a b c d
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
X 1 0 0 0 0 0 0 0 0 1 1
X X 1 0 0 0 0 0 0 1 0 1
X X X 1 0 0 0 0 0 1 1 1
X X X X 1 0 0 0 1 0 0 1
X X X X X 1 0 0 1 0 1 1
X X X X X X 1 0 1 1 0 1
X X X X X X X 1 1 1 1 1
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Combinational Logic Blocks: ROM memories
 Read-Only Memories

‒ A read-only memory (ROM) consists of an array of semiconductor devices

that are interconnected to store an array of binary data.

‒ Once binary data is stored in the ROM, it can be read out whenever desired,
but the data that is stored cannot be changed under normal operating
conditions.

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Combinational Logic Blocks: ROM memories
 Read-Only Memories

(a) Block diagram

An 8-Word x 4-Bit ROM

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Combinational Logic Blocks: ROM memories
 Read-Only Memories

Read-Only Memory with n Inputs

and m Outputs
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Combinational Logic Blocks: ROM memories
 Read-Only Memories

Basic ROM Structure

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Combinational Logic Blocks: ROM memories
 Read-Only Memories

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Sequential Circuits

 A sequential circuit is one whose outputs depend not only on its

current inputs, but also on the past sequence of inputs.

 In other words, sequential circuits must be able to ”remember” (i.e.,

store) the past history of the inputs in order to produce the present
output.

 The information about the previous inputs history is called the state
of the system.

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Sequential Circuits

 A circuit that uses n binary state variables to store its past history can
take up to 2n different states.

 Since n is always finite, sequential circuits are also called finite state
machines (FSM).

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Sequential Logic Blocks: Latches and Flip-Flops
 The two most popular varieties of storage cells used to build
sequential circuits are: latches and flip-flops.
‒ Latch: level sensitive storage element
‒ Flip-Flop: edge triggered storage element

 Common examples of latches:

‒ S-R latch, D latch

 Common examples of flip-flops:

‒ D-FF, JK-FF, T-FF

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Sequential Logic Blocks: Registers
 A collection of 2 or more D flip flops with a common clock
 Registers are often used to store a collection or related bits (e.g. a
byte of data in a computer)

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Sequential Logic Blocks: Registers
 Registers with Tri-State Ouput

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Sequential Logic Blocks: Registers
 Registers with clock enable

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Sequential Logic Blocks: Registers
 Registers application: Data Transfers

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Sequential Logic Blocks: Shift Registers
 It is a register that stores input values in sequence. At each clock tick
the values stored are shifted from one flip flop to the adjacent one.

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Sequential Logic Blocks: Shift Registers
 Application: Parallel-to-Serial conversion for serial transmission

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Sequential Logic Blocks: Shift Registers
 Application: Pattern Recognizer
‒ In this case, recognizing the pattern 1001

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Sequential Logic Blocks: Shift Registers
 Application: Ring Counter

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Sequential Logic Blocks: Shift Registers
 Application: Johnson Counter

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Ring and Johnson counter Timings

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Sequential Logic Blocks: Binary Counters

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Sequential Logic Blocks: Binary Counters

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Sequential Logic Blocks: Synchronous Binary Counters

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Clocked synchronous FSM
 Clocked: all storage elements employ a clock input (i.e. all storage
elements are flip-flops)

 Synchronous: all of the flip flops use the same clock signal

 FSM: state machine is simply another name for sequential circuits.

Finite refers to the fact that the number of states the circuit can
assume is finite

 A synchronous clocked FSM changes state only when a triggering

edge (or tick) occurs on the clock signal

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Clocked synchronous FSM structure

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FSM Types

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Clocked synchronous FSM structure
 Mealy machine

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Clocked synchronous FSM structure
 Moore machine

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Comparison of Mealy and Moore FSM
 Mealy machines have less states
‒ outputs are on transitions (n2) rather than states (n)

 Moore machines are safer to use

‒ outputs change at clock edge (always one cycle later)
‒ in Mealy machines, input change can cause output change as soon as logic is
done – a big problem when two machines are interconnected –
asynchronous feedback may occur if one isn’t careful

 Mealy machines react faster to inputs

‒ react in same cycle – don't need to wait for clock
‒ outputs may be considerably shorter than the clock cycle
‒ in Moore machines, more logic may be necessary to decode state into
outputs – there may be more gate delays after clock edge

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Design of clocked sequential circuits
 Step1. Deriving state diagram

 Step2. Deriving state transition table and output table

 Step3. Determining next state and output functions

 Step4. Implementing logic functions with combinational gates and

flip-flops.

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Design of clocked sequential circuits

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Design of clocked sequential circuits

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Design of clocked sequential circuits

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Design of clocked sequential circuits

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Design of clocked sequential circuits

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Design of clocked sequential circuits

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Design of clocked sequential circuits

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Design of clocked sequential circuits

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