EE204

Logic Circuits
Lecture Notes
Part-2 Sequential Circuits

Avni Morgül
Sequential Circuits
• Sequential circuits employ storage elements in addition to logic
gates.
• Their outputs are a function of the present inputs and the
previous inputs which are stored in the storage elements.
• The sequential properties:
1. The system must have some memory
2. The system must have at least one feedback path from the
memory element to the system inputs.
• Combinational properties:
1. The output must be strictly a function of the present inputs
2. No feedback path may exist from the output to the input.
 Sequential Circuits
• Finite State Machine is a sequential circuit
that has a limited number of States (Output
values of the memory elements).
• It also contains combinational circuits to
which storage (memory) elements are
connected, to form a feedback path.
• The binary information stored in memory
elements defines the state of the sequential
circuit.
• A sequential circuit is specified by a time
sequence of inputs/outputs, and internal
states
 Sequential Circuits
INPUTS
FEEDBACK

... ...

• Finite State Machine is a sequential circuit Next State Decoder

that has a limited number of States (Output (Input/Output Transforming
Combinational Logic )
values of the memory elements).
• It also contains combinational circuits to
which storage (memory) elements are Memory Elements
connected, to form a feedback path.
...
• The binary information stored in memory
elements defines the state of the sequential State Variables
circuit.
• A sequential circuit is specified by a time Output Decoder

sequence of inputs/outputs, and internal

states
OUTPUTS
Types of Sequential circuits
• There are two main types of sequential SEQUENTIAL
circuits CIRCUITS
1. Synchronous Sequential circuits
2. Asynchronous Sequential circuits
• This classification is a function of the timing
of their signals. Synchronous Asynchronous
Sequential Sequential
1. A synchronous sequential circuit is a system Circuits Circuits
whose behavior can be defined at the discrete
instants of time (Uses a clock signal).
level
2. The behavior of an asynchronous sequential
circuit depends upon the input signals at any
instant of time and the order in which the
time
inputs change. Clock Signal
Storage (MEMORY) Elements
• A storage (memory) element can maintain a binary state (0 or 1)
indefinitely (as long as power is delivered to the circuit), until
directed by an input signal to change state.
• Storage elements that operate with signal levels (rather than
signal transitions) are referred to as latches.
• A latch is a binary cell which can store one bit of binary
information.
• The latches that controlled by a clock transition are called
flip-flops.
The Binary Cell (SR latch)
• The SR latch is a circuit with two cross-coupled NOR gates or NAND
Gates. The inputs are labeled S for set and R for reset.
• To store a logic 1 the cell must be SET
• To store a logic 0 the cell must be RESET
• A Binary Cell or SR Latch may be constructed by using two cross-coupled
NOR Gates or NAND Gates.

R(reset) S(set)
Q Q

S(set) Q R(reset) Q

NOR Gate Implementation NAND Gate Implementation

The Binary Cell (SR latch)
• The Characteristic Tables of Binary Cell

R(reset)
Q S(set) Q

S(set) Q Q
R(reset)

S R Qn+1 Q̅n+1 Comment S̅ R̅ Qn+1 Q̅n+1 Comment

0 0 Qn Q̅n No change 0 0 Ø Ø Don’t do
0 1 0 1 Reset 0 1 1 0 Set
1 0 1 0 Set 1 0 0 1 Reset
1 1 Ø Ø Don’t do 1 1 Qn Q̅n No change

The Characteristic tables

SR Latch with NAND gate
NAND gate SR Lach circuit
S̅ R̅ Qn Qn+1=S+ R̅·Qn Comment
S Q S Q 0 0 0 1+0·0=1
DON’T DO !
0 0 1 1+0·1=1
R Q’ R Q 0 1 0 1+1·0=1
SET
0 1 1 1+1·1=1
1 0 0 0+0·0=0
ത
𝑄′ = [𝑄𝑛 ∙ 𝑅] RESET
1 0 1 0+0·1=0
1 1 0 0+1·0=0
NO CHANGE
1 1 1 0+1·1=1
The Characteristic equation
Synchronous Sequential Circuits
• The output of a synchronous sequential circuit changes only at
predetermined instants which is controlled by a clock signal.
• Synchronous sequential circuits use memory elements that are
called ̋ Clocked Flip-Flops ̏ shown below.

SET
Q
Set/Reset Basic Outputs
1 Decoder Cell
0 CLOCK RESET Q
The SR (Set/Reset) Flip-Flop

S S CLK
S Q
Q
HIGH 1
CLK CLK
LOW 0
Q Time
R Q
R R Q can change only when
CLK=1 (HIGH)
Block diagram Circuit diagram
 Analysis of the SR flip-flop
Flip-flops may be analysed by using Qn Qn+1 S R Comment
different graphical & analytical tools 0 0 0 Ø Don’t care R but no S
0 1 1 0 Definite SET and no RESET
SR 1 0 0 1 Definite RESET and no SET
Qn 00 01 11 10 1 1 Ø 0 Don’t care S but no R
0 0 0 Ø 1
3. The Excitation TABLE (for Design)
1 1 0 Ø 1 (Gives the required inputs to obtain
the desired next state)

SR=10
SR=0Ø SR=Ø0
0 1
2. The Characteristic EQUATION
(for Analysis) SR=01
1. The Characteristic TABLE (for Analysis)
4. The State Diagram
(Gives the value of the next state if inputs
are given)
The D Flip-Flop (Latch)
• The input D is transferred to the output (Latched) at the rising edge of the
CLOCK. The output doesn’t change until the input changes and next clock
pulse comes.
D D
D Q Q Qn 0 1
CLK
CLK 0 0 1
Q Q 1 0 1
2. The Characteristic EQUATION

D=1
D=0 D=1
0 1

D=0
1. The Characteristic TABLE 3. The Excitation TABLE 4. The State Diagram
 The JK Flip-Flop
The JK-Flip-Flop is the most versatile FF. It is possible to convert
the JK FF to other FF’s very easily.

J JK
J Q J Qn 00 01 11 10
Q
CLK
0 0 0 1 1
CLK 1 1 0 0 1
K Q K Q
K

2. The Characteristic
J=1 EQUATION
J=0 K=0
0 1 1. The Characteristic TABLE

K=1
3. The Excitation TABLE 4. The State Diagram
The T Flip-Flop (Toggle FF)
• The T Flip-Flop is obtained by setting the T=J=K of JK Flip-Flop

T
T Qn 0 1
T Q Q 0 0 1
CLK CLK 1 1 0
Q Q
1. The Characteristic TABLE

T=1
T=0 T=0
0 1
2. The Characteristic
EQUATION T=1
3. The Excitation TABLE 4. The State Diagram
 Summary of the Flip-Flops
RS D JK T

S Q J Q T Q
D Q
CLK CLK CLK
CLK
Q
R Q Q K Q

D=1 J=1 T=1

SR=10
SR=0Ø SR=Ø0 D=0 D=1 J=0 K=0 T=0 T=0
0 1 0 1 0 1
0 1
SR=01 D=0 K=1 T=1
 Conversion of Flip-Flops
• It is possible to convert one type of
clocked flip-flop to another type of flip-flop.
Q
• A Combinational conversion logic circuit Conversion Given
should be added to the input of the flip- Logic Flip-Flop
Outputs
flop. Q

To develop the conversion logic:

1. Draw a combined table of Excitation Feedback
Tables of given FF and the desired FF in a
single form.
2. Derive the conversion tables and input
functions for each input of the given FF.
3. Draw the conversion circuit diagram.
Conversion of Flip-Flops (Examples)
Example 1: Conversion of an Example 2: Conversion of a
SR flip-flop to a D flip-flop D flip-flop to an SR flip-flop
D flip-flop SR
Qn 00 01 11 10
0 0 0 Ø 1
D S Q Q 1 1 0 Ø 1
SR
CLK SR flip-flop
ff
R Q Q
S D Q Q

CLK Dff
D D
Qn 0 1 Qn 0 1 R Q Q
0 0 1 0 Ø 0
1 0 Ø 1 1 0
 Quiz
• Convert a JK flip-flop to an SR flip-flop. Show the conversion
table and draw the circuit diagram.
Advanced Flip-Flops
• Normally, one change is expected for each clock pulse.
However, it is possible to obtain more than one change if the
input changes more than once while the clock pulse is high.
This is an undesired operation.
• There are three solutions to this problem:
1. Making the clock pulse very narrow
2. Using a master-slave type flip-flop circuit
3. Using an edge triggered type flip-flop
The easiest solution is using very short clock pulses. But this
solution may not be suitable for every application.
Master-Slave Flip-Flops
• Two basic flip-flop are used to construct a
Master-Slave flip-flop. The first flip-flop is Y
called the MASTER and the second flip-flop is S S1 Q S2 Q Q
called the SLAVE. MASTER CLK SLAVE
• The inputs S1, R1 is loaded and the outputs of
ത are generated and latched
the master FF, Y, 𝑌, Y
R R1 Q R2 Q Q
when the clock input goes HIGH (logic 1).
However the clock input of the slave flip-flop
CLK
(CLK’) is LOW and the output does not
change.
• The inverted clock signal (CLK’) is HIGH when CLK
the CLK input goes LOW (logic 0) and Y, 𝑌, ത is CLK
May go down
transferred to the SLAVE flip-flop and output any time
Q, 𝑄ത is generated. The input signal does not S
affect the output because the MASTER flip
flop is disabled antil the next periode of the Y Only this value affects
CLK comes. Q
time
 Edge Triggered Flip-Flop
• A change in the output of the flip-flop can be triggered only during the transition of the clock from 0 to 1
(Rising edge triggered flip-flop)
• The S and R inputs of the output latch are maintained at the logic-1 level when Clk=0. The output to remain
in its present state. If D=0 when Clk becomes 1, R changes to 0. This causes the flip-flop to go to the reset
state, making Q=0. If there is a change in the D input while Clk=1, terminal R remains at 0 because Q is 0.
Thus, the flip-flop is locked out and is unresponsive to further changes in the input.

• When the clock returns to 0, R amplitude

goes to 1, placing the output
S
latch in the quiescent condition Q
without changing the output. active
• If D=1 when Clk goes from 0 to transition CLK
point Q
1, S changes to 0. This causes
the circuit to go to the set state, time R
making Q=1. Any change in D inputs can Data loced-out
Setup Data
change up to (input may
while Clk=1 does not affect the time hold D
this time change from
time
output. this point)

Input signal transition and the circuit diagram of a D-Type Rising edge triggered flip-flop
ANALYSIS OF
CLOCKED SEQUENTIAL
CIRCUITS
ANALYSIS OF
CLOCKED SEQUENTIAL CIRCUITS
• The behavior of a clocked sequential circuit can be described
algebraically by means of state equations.
• The State is the logic value of the flip-flop output variable(s) at a
given time.
• A state equation specifies the next state as a function of the present
state and inputs. Example:
A(t+1)=A(t) x + B(t) x
Where
A(t+1): Next State;
A(t), B(t): Present States;
x : Input variable
STATE DIAGRAM
• The state diagram is a pictorial guide used to describe the state to state
transitions. It is an equivalent tool of the truth table of combinational circuit.
Combinational Analysis → Truth Table
Sequential Analysis → State Diagram b
Previous state
Output for
state c
Next state c Present state
input code Q 1Q 2
XX/ZZ YY/WW
Next state Next state
d e

State Diagram
STATE DIAGRAM EXAMPLE
• Problem: A sequential circuit which has an input x, two outputs A, B. The
output changes from 00 to 01, 10, 11 if x=1, it holds the present state if x=0
at any time. Draw the state diagram.

State A B
x Seq. A a 0 0
CLK Circuit B b 0 1
c 1 0
d 1 1
STATE DIAGRAM EXAMPLE
• A sequential circuit which has an input x, two outputs A, B. The output
changes from 00 to 01, 10, 11 if x=1, it holds the present state if x=0 at any
time. Draw the state diagram.
0/00
Branch format: x/AB
State A B a
x Seq. A a 0 0 00 1/11
1/00
CLK Circuit B b 0 1 0/01 0/11
c 1 0 b d
d 1 1 01 11
1/01 c The
1/10
10 State
0/10 Diagram
 STATE DIAGRAM EXAMPLE
• A sequential circuit which has an input x, two outputs A, B. The output
changes from 00 to 01, 10, 11 if x=1, it holds the present state if x=0 at any
time. Draw the state diagram.
0/00
Branch format: x/AB
State A B a
x Seq. A a 0 0 00 1/11
1/00
CLK Circuit B b 0 1 0/01 0/11
c 1 0 b d
d 1 1 01 11

Sequences for x=1: 00 → 01 → 10 → 11 → 00 1/01 c The

1/10
10 State
cloc # 1 2 3 4 0/10 Diagram
time
state 00 01 10 11 00
 ANALYSIS PROCEDURE
Analysis of a sequantial circuit means that
obtaining the state transition diagram of the
circuit of which the circuit diagram is given.
x
A
The procedure: D1 Q
1. Identify the
• INPUT (Next State) DECODER y
Q A
• MEMORY
• OUTPUT DECODER
2. Write the Boolean expression for B Output
each of the outputs of the Next State D2 Q Decoder
decoder, inputs of MEMORY
elements (FFs) Input
Decoder Q B
A(t+1)=D1(t)=Ax+Bx
B(t+1)=D2(t)= Ax clock
Memory
Elements
3. Write the output expression
Example Circuit
y = x (A+B)
ANALYSIS PRECEDURE
4. By using the equations (or using the Karnough maps) perform the
present and next state map.
5. Determine the NEXT STATE by using this maps and the characteristic
tables of FFs
6. Plot the STATE DIAGRAM by using this map.
Present Next State Next
Input Output A(t+1) = D1(t) =Ax+Bx 0/0
State Input Code State
A B x DA DB y A B B(t+1) = D2(t) = Ax Branch format: x/y
y = x (A+B)
0 0 0 0 0 0 0 0 1/0 00
0/1
0 0 1 0 1 0 0 1 0/1
D=1
0 1 0 0 0 1 0 0 01 0/1 10 1/0
D=0 D=1
0 1 1 1 1 0 1 1 0 1
1/0
1 0 0 0 0 1 0 0 11 1/0 State: AB
D=0
1 0 1 1 0 0 1 0
1 1 0 0 0 1 0 0 STATE DIAGRAM
of D flip-flop STATE DIAGRAM of the system
1 1 1 1 0 0 1 0
Present-Next STATE Map
Procedure
Pres St. In N.S. [Link] Out Next St. Pres St. In N.S. [Link] Out Next St.
A B x DA DB y A B A B x DA DB y A B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A(t+1) = D1(t) =Ax+Bx
0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 B(t+1) = D2(t) = Ax
0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 y = x (A+B)
1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0
1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0
1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0
1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 0

Pres St. In N.S. [Link] Out Next St. Pres St. In N.S. [Link] Out Next St.
A B x DA DB y A B A B x DA DB y A B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1
1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0
1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0
1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0
1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 0
 Analysis Example 2 Present
State
A B
Input Next State Input Code Output
x SA RA SB RB y
Next
State
A B
x
x A 0 0 0 0 0 0 0 0 0 0
S Q 0 0 1 0 1 1 0 0 0 1
B
0 1 0 1 0 0 0 0 1 1
0 1 1 0 0 1 0 0 0 1
x A y y = xAB
R Q 1 0 0 0 0 0 1 0 1 0
B
1 0 1 0 1 0 0 1 0 0
Output
x B Decoder 1 1 0 1 0 0 1 0 1 0
S Q 1 1 1 0 0 0 0 0 1 1
A

STATE DIAGRAM 0/0 Branch format: x/y

x B of the circuit
R Q 1/0 00
A 1/1
SR=10 1/0
SR=0Ø SR=Ø0 01 10 0/0
Input Memory 0 1
clock

Decoder Elements 0/0

11 0/0 State: AB
SR=01
LOGIC DIAGRAM of the circuit STATE DIAGRAM of SR flip-flop 1/0

Result: If x=0 the circuit remains at 00 state. If x is set to 1 once and goes back to 0, it goes to 01 and continuos to states 11,
10 and stops there. Then, if input x=1 again it goes to 00 and generates an outpu 1 during the last transition and stops.