Indian Institute of Technology Roorkee
ECN-205:
Analog Circuits
Tutorial -6 (Set-B)
Problems on Feedback:
Problem:1 The circuit of Figure.1 must achieve a closed-loop -3 dB bandwidth of B. Determine
the required value of K. Neglect the other capacitances and assume 𝜆 > 0
Figure 1
Problem:2 Consider the feedback circuit shown in Figure 2, where R1 + R2 >> RD. Compute the
closed-loop gain and I/O impedances of the circuit. Assume 𝜆 = non-zero
Figure 2
Problem:3 Determine the closed-loop I/O impedances of the circuit shown in Figure 3
Figure 3
Problem:4 The amplifier depicted in Figure 4 consists of a common-gate stage (M1 and RD) and
a feedback network (R1, R2, and M2). Assuming R1 + R2 is very large and 𝜆 > 0, compute the
closed-loop gain and I/O impedances.
Figure 4
Problem:5 Consider the feedback system shown in Figure 5, where the common-source stage
serves as the feedforward network. Assume 𝜇𝑛 𝐶𝑜𝑥 may vary by ±10% and 𝜆 by ± 20%. What is
the minimum loop gain necessary to guarantee that the closed-loop gain varies by less than ±
5%?
Figure 5
Problems on Op-amp:
Problem:6 Design the op amp of Figure 6 for the following requirements: maximum differential
swing = 2.4 V, total power dissipation = 6 mW. (Assume that the gate of M2 is never shorted to
the output.)
Figure 6
Problem:7 In the circuit of Figure 7, each branch is biased at a current of 0.5 mA. Choose the
dimensions of M7 and M8 such that the output CM level is equal to 1.5 V and VP = 100 mV.
Figure 7
Problem:8 Suppose that in Figure 8, I1 = 100 μA, I2 = 0.5 mA, and (W/L)1−3 = 100/0.5. Assuming
that I1 and I2 are implemented with PMOS devices having (W/L)P = 50/0.5,
(a) Calculate the gate bias voltages of M2 and M3.
(b) Determine the maximum allowable output voltage swing.
(c) Calculate the overall voltage gain and the input-referred thermal noise voltage
Figure 8
Problem:9 The amplifier sensing V out, CM is to be implemented as a different pair with active
current mirror load as shown in Figure 9
(a) Should the input pair of the amplifier use PMOS devices or NMOS devices?
(b) Calculate the loop gain for the CMFB network.
Figure 9
Problem:10 Assume a power budget of 6 mW, a required output swing of 2.5 V, and Leff = 0.5 μm
for all devices.
(a) Allocating a current of 1 mA to the output stage and roughly equal overdrive voltages to M5
and M6, determine (W/L)5 and (W/L)6. Note that the gate-source capacitance of M5 is in the
signal path, whereas that of M6 is not. Thus, M6 can be quite a lot larger than M5.
(b) Calculate the small-signal gain of the output stage.
Figure 10
