UNIT-4 ANALYSIS OF CLOCKED (Synchronous )SEQUENTIAL CIRCUITS To analyze a sequential circuit, we can use © State equations * State table © State diagram © Flip-Flop input equations Remember Characteristics Equation of FF. = D flip-flop: , Qt+)H)=D « JK flip-flop: Ot+)=JO+K'O = T flip-flop: O(t+1)=T ®QO=TO'+T'O ° State Equations (Transition Equation) Specify the next state as a function of the present state and inputs. Also called transition equation, Analyze the combinational part directly. Example: For Synchronous sequential circuit. ACt) 1 x p—— > ACD “ ae a =UNIT-4 State Equetion: A(t+1) = A(E)x(t) + BCEx(t) B(t+1) = A(t) x(t) Short form of state equation. me> A(t+1) = Ax + Bx , => B(t+1) = ax Next State ray YC)=TAC)-+8(t)] x(t) Short form of out put => y=(A+B)x’ State Table (Transit n Table): Enumerate the time Sequence of inputs, outputs, and flip-flop states. Also called transition table. Similar to list the truth table of state equations Consist of four sections Present state, input, next state, and output A sequential circuit with m flip-flops and n inputs need 2™** rows in the state table, Put the value of present state (A, B) and input X into state equation, calculate the value of next state and out-put . : Present | input [Nex t+3) Output state state Hie Ielolololaly Ble lololm/H/ ololg BIO}HIO/K/Olololp O/O}ololHlolH/o/m OlK/OlMlalMlolol< HIO|MlolMlolH/o/x : Ic IS = is = jo J so = ieUNIT-4 ‘r The state table has only three section: present state, next state, and output = The input conditions are enumerated under next state and output sections Present Next State Output State X=0 X=1 =0 | X=1 A [Sonam SemiAness | vo lever’ 0 || (oni SRomltone| voy | a CMeee | |) OP etl 4 | “0m om eront ae |. #_| 40m ome etal ram: Graphically represent the information in a state table Circle: a state (with its state value inside) Directed lines: state transitions (with inputs/outputs above). : starting from state 00 If the input is 0, it stays at state 00 with output=0 Tf the input is 1, it goes to state 01 with output=0 The state table is easier to derive from a given logic diagram and state equations ‘The state diagram is suitable for human interpretation. input/ out-put Analysis with D Flip-FlopUNIT-4 © Ct. diagram is given as 1> eo oe Sa LK * List the Boolean expressions of the combinational circuits Input equation: Dxa=ASxSy * Write characteristics equation of given FF of Ckt. Here FF is D type. So characteristics equation is Q@+) =D So, A(t+l) = Dai) Equations (Transition Equation) A(t+1) =AMSx(y SY A(t) =Abxdy T: i Seem Ooooh we oOmm Oo MOnOR ORD BOGHOHHO : (0b) State table diagram (in this ckt no output ) 01,10 (©) State diagramUNIT-4 Analysis with JK Flip-Flops: given ckt. * Uist the Boolean expressions of the combinational circuits Step 1: input equations J,=B K,=Bx’ Jg=x' K=AGx’ * Write characteristics equation of J-K Flip flop QH+) =F QMY +E Q(ny Step 2: state equations . A(t+1)= JA'+K'A = BA’ + (Bx')'A = AB + AB’ + Ax B(t+1)= JB + KB = XB’ + (ADx)B = BX’ + ABx + By’UNIT-4 Step 1: input equations T,=Bx Tg=x y=AB * Write characteristics equation of T Flip flop Q+=T Qn) +Q@y T Step 2: state equations A(t+1)= TA +TAX = (Bx)'A + (Bx)A’ = AB’ + AX’ + A'Bx B(t+1)= TB + TB’ =X'B + xB’ =xoB Step 3: state table Step 4: state diagram Present | Input i | Tyee Et { Fo {b) State diagram KIelololololololkUNIT-4 Mealy and Moore Model for finite Machine = Mealy model : J = The output is a function of both the Present state and input _ The output may change if the inputs chi duri clock . utp y chang je input ange during’a loc! kaye Inputs} Next State Logic| Output Logic Jp. Mealy (combinational) (combinational) Outputs ZF = Moore model : = The output is a function of the present state only = The output are synchronized with the clock ~ Inputs Output Logic Moc (combinational > Outputs State Reduction and Assignment Reduction: Reducing the number of states in a state table, while keeping the external ut requirements unchanged. It reduced the cost of CKT.Fis. 5-22 State Diagram State Reduction Rules: = Two states are said to be equivalent if, for every possible inputs, they give exactly the sarne output and have equivalent next state Present | Next State Output Present | Next State Output State _|X=0 X=1/xX=0 X=1 State |X=0 X=1/xX=0 X=1 0 a a bilo uo b [ce dfo o ¢ a a a) d e f 0 1 e a f oO 1 f e if 0 1 ea delete state gand replaced with state eUNIT-4 = After the first reduction, we can see that state d and state f will have the same output and next state for both x=0 and x=1 = Further reduce one state Present [Next State | Output Present | Next State | Output State |X=0 X=1/x=0 X=1 State |X=0 x=1/x=0 X= a ab] o o a ae be ee 0 b cd foo b ed [oo c ad |o © adlo o DT ee d e Cp] o a e a eof |o 4 e a CDT o a er ae i : ie delete state f and replaced with state d luced State Diagram: Fig. 5-23 Reduced State Diagram State Assignment:UNIT-4 = Binary: assign the states in binary order = Typical method without other considerations «= Gray code: assign the states by gray code = Lower power consumption during state transitions (if in order) = One-hot: assign a specific flip-flop for each state = Simplify the circuit design but may have larger hardware cost —=—_oOO State Assignment 1 Assignment 2 Assignment 3 Binary Gray code One-hot a 000 000 00001 b 001 001 00010 c 010 O11 00100 d O11 010 01000 e 100 110 10000 * Design procedure of synchronous sequential circuits: * Derive a state diagram for the circuit from specifications ¢ Reduce the number of states if necessary Assign binary values to the states © Obtain the binary-coded state table * Choose the type of flip-flop to be used * Derive the simplified flip-flop input equations and output equations * Draw the logic diagram : .N.1: Design a sequential ckt. Using D- FF for given state diagram, OR, design a circuit that detects 3 or more consecutive I.s at inputs wer:AGH) = DiA4,B,x) = 35.7) B+) = Di 4,8.) = 5,7) WA,B.x) => (6,7) i 5 o ame y x 2 ff af: thy poe nee LE) Dyn are os Fia,5:26 Logie Diagram of Sequence Detector .2. A sequential circuit with two D ip-flops 4 and B, two inputs, x and y ; and one output 2 'S specified by the following next-state and output equationsUNIT-4 may! +B 5A + xB" A(t +1) BO+ 1) Answer: fa) (tN 1090 91m Ie ealnnnn, aime S283 os ~ccfos a, sm “lo ~e cle ~ocloccslenan ory os Slo oe. seat hes, éUNIT-4 by nat fantial cireuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations: hax Kins Sn=x Kp-a (9) Derive the state equations A(t+ 1) and 8(¢ +1) by substituting the input equations for the J and K variables. (b) Draw the state diagram of the circuit. A(t+l) =J,A' + A= xA"+ BA B(t+l) =J,B'+ KB =x8'+4'B 5.10 A sequential circuit has two JK flip-flops A and B, two inputs x and J, and one output z. The flip-flop input equations and circuit output equation are Ig= But By’ Ky= B'xy' In=A't Kym Atay! At'y' + Br'y’ (a) Draw the logic diagram of the circuit. (b) Tabulate the state table, (©) Derive the state equations for A and B,UNIT-4 Draw logic a= Any + Bey ® + a ts Ve ae ~ a ne ze ax i) diagram Your self ze the © gos nding. avons *a] PON =| ams a yaleaoen a => = qo » | elke ‘ 8 fe le = cs 7 i + | ma ile & = ele a8 Ne = s| . ake leo Nee 4 & 5 i 3 cone } 5 ele le 5 ER 8 ae & = a oe (5 a