Chipledga sang fr ekceence SCAN-JTAG Lab Manual 6 Lab6a Learning Objective In this Lab, you will understand insertion of JTAG logics into the design and understand different instructions. You can analyze boundary scan logis inserted to operate in different modes. This Lab is more of command based & executing the command based labs helps for better understanding. There are questions added in the Lab manual in order to improve your knowledge and analysis skills. 1 Tab6a | JTAG insertion with Boundary sean At the end of the Lab, you should be able to, ¢ Understand JTAG architecture ¢ Insert JTAG using different BSD cells © Understand different JTAG instructions Tasks: Lab 6a: JTAG Insertion Copy the lab database to your home directory ChipEdge Technologies Pvt LtdChipEdgé siiing fre Go through the directory structure & files, Input/design_wpads.v _-> Top level netlist with pads Scripts -> Scripts directory to invoke BSD Compiler Scripts/run -> Run script to invoke BSD Compiler Scripts/[Link] ->To insert JTAG logies Reports, -> Directory to save all reports, Output -> To write out JTAG inserted netlist This command invoke the BSD Compiler in Shell mode linux > tesh linux >which de_shell inux > dco_shell -output_log file logs/[Link] Log file will be saved in the logs directory. Set the library path de_shell> set lib path /tools/libraries/29nm/SAED32_EDK c_shell> set search path [list™ $project_path ] end searéh ‘path "/home/dft/scan/Séan_labs/B3/week4_labs/LAB4a /tools/synopsys/installets/designcomplier/libraries/syn /tools/new_libs /tools/libraries/28nm/SAED32_EDK/tech/milkyway /tools/librarig$/28nm/SAED32_EDK/lib/stdcell_hvt/db_nldm /tools/librarites/2@nm/SAED32_EDK/1ib /tools/librar: 7 EDK/1ib/stdcell_lvt/db_n1dm /tools/librawies/28nm/SAED32_EDK/lib/stdcell_rvt/db_nldm /tools/librartes/2énm/SAED32_EDK/1ib" dc_shell>)set_app_var link library {saed. 2: [Link] saed32hvt_ss0p9. 921 vt_ss0p95v125c.db 5v125¢.db pads [Link] var target [Link] sae ibrary {saed321vt 2hvt_ss0p95 jp9Sv125e -_ss0p9 [Link] pads_m db [Link]} 6 8 dc_shell> set_app var hdlin_enable_rtldre_info true Read the netlist ChipEdge Technologies Put Ltd“ ChiplEdgé ‘Skiling for excellence de_shell > read_file input/design_wpads.v -format verilog Set Current design to TOP module, i.edig_top pads dce_shell > set current_design dig top_pads Link the design with libraries de_shell >link Enable boundary scan design insertion dce_shell > set_dft_configuration -bsd enable -sean disable Define JTAG ports de_shell > set_dft_signal -view spec -type tdi -port tdi_pad de_shell > set_dft_signal -view spec -type’tdo -port tdo_pad de_shell > set_dft_signal -view spec\stype tck -port tck_pad de_shell v set_dft_signal -yiew/spec -type tms -port tms_pad v de_shell > set_dftfsignal -yiew spec -type trst -port \ trst_mpéd -active_state 0 Configure the Boundary Scan by defining reset, Instruction register width, encoding style de_Shell >\set_bsd_configuration -asynchronous_reset true \ -ir_width 4 -check_pad_designs all -style \ synchronous -instruction_encoding binary Define boundary cell for particular port de_shell > set_boundary_cell -class bsd -type BC_4 -ports \ [list adcl_analog_in4_pad] ChipEdge Technologies Put LtdChipEdgé siiing fre Define JTAG Instructions © EXTEST)\ 1 t BYPASS]\ [list 1111] -regis de_shell > set_bsd_instruction -view spec [list SAMPLE] \ 1100] -register BOUNDARY de_shell > set_bsd_instruction -view spec [list PRELOAD]\ -code [list 1100] -register BOUNDARY, Preview the Boundary scan design and generate reports de_shell > preview_dft -bsd tap de_shell > preview dft -bsd instructions dce_shell > preview_dft -bsd all Insert BSD de_shell > insertydft Write the BSD inserted netlist de hell\> write “format Verilog -hierarchy -output \ output /dig top_bsd.v Qu: Check the instruction codes of all the instructions Qe: Understand the TAP configurations Qa: Analyze BSD inserted netlist ChipEdge Technologies Put LtdChipledge sang fr ekceence HoH Hoe HEE nd of LabGattti tet eeeenenene ees ChipEdge Technologies Put Ltd