Department of Electrical Engineering
SEECS, NUST
EE 421: Digital System Design
Spring 2024
Lab - 02
Combinational Circuits Design and Dataflow
Modelling
Department of Electrical Engineering, SEECS, NUST
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1. Objective
The objective of this lab is to design combinational circuits and implement them on a
DE1-SoC board. The focus of this lab is to describe combinational circuits using the dataflow
method.
2. Dataflow Modelling
Dataflow modeling provides the means of describing combinational circuits by their function
rather than by their gate structure. Dataflow modeling uses a number of operators that act on
operands to produce the desired results. Verilog HDL provides about 30 operator types.
In dataflow modelling, the assign keyword is used to create continuous assignments.
Continuous assignments are used to model combinational logic in hardware description
languages. They specify how signals are related to each other in terms of logic expressions.
To illustrate this let us consider a very basic example of the AND gate. An AND gate can be
described by using a single assign statement.
module andgate(output f, input a, input b);
assign f = a & b;
endmodule
& is an operator which will perform bit wise AND operation on inputs a and b. After
evaluation, the result is assigned to output f. Consider a 4-input AND gate of figure 1.
Figure 1. 4-input AND gate
This can be described by using a single assign statement and by using & operators.
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module andgate_4input(output f, input a, input b, input c, input d);
assign f = (a & b) & (c & d);
endmodule
The above code performs bit wise AND operation on inputs a,b and c, d separately first and
the result of these two will be performed by another AND operation.
Task 1 : Understanding FPGA Input/Output using Constraint File
In Lab 1, you used a pin assignment planner in Quartus for assigning inputs to switches and
outputs to LEDs. In this task, we will use Quartus system file having .qsf as file extension
for pin assignment for 2 input AND gate.
module andgate(output f, input a, input b);
assign f = a & b;
endmodule
Figure 2. 2-input AND gate
The qsf file describes the pin locations of various peripherals that are connected with FPGA.
● To add qsf file, go to Assignments > Export Assignments & then Open *.qsf from
'File'->'Open' Menu. Once this file is added in the project you will see it in the
directory of your project.
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Figure 3. .qsf file for DE1 SoC FPGA Board
● Open this file in notepad and navigate to the lines where switch locations are
specified
Figure 4. A Sample .qsf File
● Modify the line
set_location_assignment PIN_AB12 -to SW[0]
with the following
set_location_assignment PIN_AB12 -to a
● Similarly, for input b we assign it to pin AC12
set_location_assignment PIN_C12 -to b
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● On the same lines navigate to set_location_assignment PIN_V16 -to LEDR[0] and
change LEDR[0] with f.
● Save the file and recompile the design and load it onto the FPGA. Test the
functionality of the AND gate by applying different input combinations of a and b such
as (0,0), (0,1), (1,0) and (1,1).
● Analyze the synthesis report to figure out the utilization of FPGA resources. To see
how much logic is used to synthesize the design, select Processing > Compilation
Report. Click on Analysis & Synthesis > Place Stage > Resource Usage
Summary. The Analysis & Resource usage summary window will show the number
of resources used after synthesis.
Figure 5. Resource Utilization Summary
● To see how much of the device is used to implement the design, select Processing >
Compilation Report. Click on Fitter > Resource Section > Resource Usage
Summary.
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Figure 6. Resource utilization summary after implementation
Task 2 : Implementation of Half Adder on FPGA
● In this task, you are supposed to describe the Half Adder design in Verilog HDL,
simulate it and implement it on an FPGA. You need to follow the same procedure as
described in Task 1.
● Test the Half Adder for all possible input combinations from the input switches and
analyze the output on LEDs.
● Analyze the synthesis report for FPGA resource utilization.
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Task 3 : Binary-2-Seven Segment Converter
● Design a Binary-2-Seven Segment Converter
● Using a truth table, derive the equations of the Seven Segment display.
● From the equations, express the Seven Segments outputs using assign statements.
● Simulate your design by writing its test bench.
● Make a constraints file to take input from switches and display the result on Seven
Segment Display in hexadecimal format.
● Test all the possible input combinations.
Task 4 : 4-bit Adder/Subtractor Output on Single Seven Segment Display
● Take the 4-bit Adder/Subtractor circuit designed as part of assignment.
● Integrate the Seven Segment module with 4-bit Adder/Subtractor in a top module.
● Simulate the integrated system and check whether it is working as per expectation.
Figure out the limitations with this design in terms of display of the output.
● Create a constraints file to map inputs and seven segment display.
● Implement the design on the FPGA board and verify the results.
● Analyze the synthesis report and see whether the resource utilization makes sense.
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Task 5 : 4-bit Adder/Subtractor Display
● Modify Task 4 so that the output can be displayed properly. The output should be
displayed for all possible input combinations.
3. Learning Outcomes Checklist
After this lab, you will be able to:
🗹 Understand data flow modelling by making use of assign statements
🗹 Use of Quartus System File for pin assignments
🗹 How to integrate different modules in a top level design
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