Question Bank Answers for Module-2

2(a)Explain the FPGA Design Flow

(Ans) The design flow illustrates the pipeline for implementing and programming any
given logic on the physical board. I chose to dub this design flow as FPGA Development
Life Cycle or FDLC because of its analogy with SDLC.

FPGA architectural design flow comprises design entry, logic synthesis, design
implementation, device programming, and design verification. However, the exact
steps vary with manufactures.

Design Entry

The description of the logic can be made using either a schematic editor, a finite state
machine (FSM) editor, or a hardware description language (HDL). This is done by
selecting components from a given library and providing a direct mapping of the
design functions to selected computing blocks.
 When designs with a very large amount of function become difficult to manage
graphically, HDL may be used to capture the design either in a structural or in a
behavioral way. Besides VHDL and Verilog, which are the most established HDLs,
several C-like languages are also available such as Handel-C, Impulse C, and SystemC.

Logic Synthesis

This process translates the above VHDL code into a device netlist format for depicting a
complete circuit with logical elements. Synthesis involves checking the code syntax and
analyzing the hierarchy of the design architecture. Next, the code is compiled along with
optimization and the generated netlist is saved as a .ngc file.

Design Implementation

The design implementation process consists of the following steps:

Translate: This process combines all the input netlists into the logic design file which is saved
as a .ngd file. Here user constraints file assigns the ports to the physical elements.

 Map: This involves mapping the logic defined by the .ngd file into the components of
FPGA and then generating a .ncd file.
  Place and Route: Here routing places the sub-blocks from the above process into
the logic blocks according to the constraints and then connect those blocks.

Device Programming

The above mentioned routed design must be loaded and converted into a format supported
by the FPGA. Hence, the routed .ncd file is given to the BitGen program, which generates a
bitstream file that contains all the programming information for an FPGA.

Design Verification

This is done all along with the design flow for ensuring that the logic behaves as intended.
The following simulations are involved in this process:

 Behavioral Simulation (RTL Simulation)

 Functional Simulation
 Static Timing Simulation

These simulations are done in order to emulate the behavior of the components by
providing test patterns to the inputs of the design and observing the outputs.

2(b)Explain the programming Technologies

(Ans) The Programming elements are used to implement the programmable
connections among FPGA’s logic blocks and a typical FPGA may contain more than
100,000 programming elements. For these reasons the elements should have the
following properties:
EPROM transistors and they require multiple voltage sources (for reprogramming)
which might not otherwise be required.

3. Explain the configurable logic block

(Ans) The array of CLBs provides the functional elements from which the
user’s logic

is constructed. The logic blocks are arranged in a matrix within the perimeter

of IOBs. [For example, the XC3020A has 64 such blocks arranged in 8 rows

and 8 columns.] The development system is used to compile the

configuration

data which is to be loaded into the internal configuration memory to define

the

operation and interconnection of each block. User definition of CLBs and their

interconnecting networks may be done by automatic translation from a

schematic-capture logic diagram or optionally by installing library or user

macros.

Each CLB has a combinatorial logic section, two flip-flops, and an internal

control section. See Fig. 4.4. There are: five logic inputs (A, B, C, D and E); a

common clock input (K); an asynchronous direct RESET input (RD); and an

enable clock (EC). All may be driven from the interconnect resources
adjacent

to the blocks. Each CLB also has two outputs (X and Y) which may drive

interconnect networks. Data input for either flip-flop within a CLB is supplied
from the function F or G outputs of the combinatorial logic, or the block
input,

DI. Both flip-flops in each CLB share the asynchronous RD which, when

enabled and High, is dominant over clocked inputs. All flip-flops are reset by

the active-Low chip input, RESET, or during the configuration process. The

flip-flops share the enable clock (EC) which, when Low, recirculates the flip

flops’ present states and inhibits response to the data-in or combinatorial

function inputs on a CLB. The user may enable these control inputs and
select

their sources. The user may also select the clock net input (K), as well as its

active sense within each CLB. This programmable inversion eliminates the

need to route both phases of a clock signal throughout the device.

Fig. 4.4 Xilinx: XC3000 series CLB

4. Explain programmable interconnects & Configurable IO blocks

(Ans) Programmable Interconnects:

Implementing an entire design on the LCA requires interconnecting the
various
CLBs and IOBs. This facilitated by the programmable interconnect resources,
which consist of a grid of two layers of metal segments, programmable
interconnect points (PIPs) and switch boxes. A PIP comprises in Fig. 4.7.
Dropping a “1” into the RAM Cell establishes a connection between two
points.
Fig. 4.7 The Programmable Interconnect: RAM Cell and PIP
Different routing resources are available for different circumstances. Vertical
and horizontal long lines run the entire height and width of the interconnect
area. They used to carry high-fanout signals or signals that need to travel
long
distance with low skew. Direct connection is available between adjacent
CLBs
and IOBs for short-distance and low-delay communication. General-purpose
interconnect is the most versatile of all. It consists of a network of switching
matrices and wore segments to facilitate general network branching and
routing.
The general-purpose interconnects are to the Xilinx device what the routing
channels are to gate arrays. In the XC3000 family, they consist of five
horizontal and five vertical lines located between the rows and columns of
CLBs. At the intersection of vertical and horizontal lines, there is a switch
box,
also called a switching matrix, as shown in the Fig. 4.8. Twenty admissible
interconnect options of a Xilinx XC3000 switch box are depicted in Fig. 4.9.
Some signal-restoring buffers are available along some routing resources to
restore signal levels due to degradation through the pass transistors inside
the
switch boxes.
Each XC2000 and XC3000 CLB can be directly connected to its neighboring
blocks. The X-output of a CLB is directly connected to the B-output of the CLB
immediately to its right and the C-input of the CLB to its left. The Y-output is
connected to the A- and D- input of the CLB below and above, respectively.
Direct interconnect is also provided between the CLBs (along the logic cell
boundary) and some IOBs. Direct interconnect typically has less routing
delay
than general-purpose interconnect and long lines.
Long interconnect lines or long lines are available along the vertical and
horizontal channels. They bypass the switch boxes and have less skew than
general-purpose interconnect. The horizontal long lines in a XC3000 or
XC4000 device may be connected to the tri-state buffers that are accessible
to
CLBs. This feature allows the formation of busses, multiplexers, and wired
AND functions. As in the case of direct interconnections, long lines have the
advantage of minimizing delays for high-fanout nets and lowering skew. The
interconnect facility in the series 4000 devices is significantly different. In
particular, the switch box connections are much simpler.

Fig. 4.8 Xilinx: General Interconnects

Fig. 4.9 Possible switch box connectivities

Configurable IO blocks

The XC3000 IOB, is shown in Fig. 4.6, provides an interface between the
Logic
Cell Array (LCA) and the external world. There is one IOB for every
programmable pin on the LCA package. The XC3090, for instance, provides
144 such I/O pins. Each IOB contains input and output buffers to facilitate
compatibility with TTL and CMOS threshold levels. The IOB can serve as an
input, output or tri-stated bidirectional path. The input signal can be
introduced to the internal logic directly or via a D-flip-flop (registered) or a
transparent latch. Similarly, the output can optionally be registered or
directly
connected to the pad. The output buffer is provided with skew control as well
as tri-state control. Generally the number of I/O pads and IOBs increase with
the logic capacity of the part type. There may be some unbounded pads that
are inaccessible to the IOBs. Electrically, the XC3000 IOB can either sink or
source 4mA of current. External buffers are usually needed to interface the
IOB
to current demanding devices.
The 4000 family has an additional I/O feature, the boundary scan circuitry,
which greatly facilitates board-level interconnect testing. The XC4000 IOB
can

either sink 12 mA or source 2 mA of current.

Fig. 4.6 The I/O block of Xilinx: XC3000 series CLB

5. Discuss logic synthesis with Boolean diagram
6. Draw the mapping using Dynamic Programming

(Ans)
9. Discuss Static Ram Programming Technology

(Ans)
10. Discuss Anti –fuse programming Technology

(Ans)
11. Explain EPROM & EEPROM Programming Technology

(Ans)
EPROM transistors and they require multiple voltage sources (for reprogramming)
which might not otherwise be required.
12. Discuss summary of Programming Technologies

(Ans)