Digital Systems and
Microprocessors Lab
Mini-Project
-By-
2021300001 – Shaan Agarwal
2021300004 – Mohammed Shanouf Valijan
Ansari
F.Y. B-Tech. Computer Engineering – Batch A1
-Faculty-
Prof. Sneha Weakey
Aim:
To implement a 2-bit Multiplier using the Integrated circuits (ICs)
of the basic logic gates.
Source of the Idea:
This idea was thought about while surfing the internet looking
for the topics where the concepts of SOP (Sum of Product) and
K-maps (Karnaugh maps) could be used to implement a
particular circuit.
Equipment Required:
IC 7404 (Hex 1 input NOT gate)
IC 7408 (Quad 2 input AND gate)
IC 7432 (Quad 2 input OR gate)
IC 7486 (Quad 2 input XOR gate)
Software Used:
Proteus-8 by Labcenter Electronics (The software was used to
demonstrate the
final circuit diagram as a whole and its working).
Theory:
A binary Multiplier is a digital combinational circuit used in
digital electronics to multiply two binary numbers. The result is
obtained as the output which is binary as well and can be
converted to decimal digits using 7-segment display module.
The method used to multiply two binary numbers is similar to
the regular approach that is followed in pure mathematics which
is based on calculating partial products, shifting them and
adding them together. Multiplication is much easier in binary
since 1 and 0 are the only digits that one has to work with.
In this mini-project, we have implemented a 2-bit binary
multiplier, a block diagram of which is attached below. The
image demonstrates a circuit where we have 4 inputs and 4
outputs (each representing a single bit). Here two 2-bit numbers
A & B are multiplied to produce a 4-bit output P. Note that A1, B1
and P3 are the most significant bits (MSB) while A0, B0 and P0 are
the least significant bits (LSB). The output is a 4-bit number
since the maximum product that can be obtained is by
multiplying 3 with itself, giving a result of 9 which is 1001 in
binary (A 4-bit number).
Figure-1: A block diagram of a 2-bit binary multiplier
The Truth-Table for a 2-bit Multiplier is as follows: -
Inputs Outputs
A B P
A1 A0 B1 B0 P3 P2 P1 P0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1
The above truth table was obtained by manually multiplying all
the input combinations and writing the results obtained in 4-bit
binary format.
From the above truth table, using the concepts of SOP, one can
obtain the expression for each of the output bits P3 , P 2 , P1 , P0.
Given below is the standard SOP form for all the output
bits: -
P0 =∑ m(5 ,7 , 13 , 15)
P1= ∑ m(6 ,7 ,9 ,11, 13 , 14)
P2= ∑ m(10 ,11, 14)
P3= ∑ m(15)
In order to minimize the above expressions, we have used the
concept of Karnaugh Maps as follows: -
1 1 1 1
1 1 1 1
1 1
Figure-2: K-maps for the outputs P0 and P1 respectively
1 1
1 1
Figure-3: K-maps for the outputs P2 and P3 respectively
From the above K-maps, following are the minimized
expressions for the respective output bits: -
P0 = A0 B0
P 1= A 1 B 1 B 0 + A1 A 0 B 0 + A 1 A 0 B 1+ A 0 B1 B 0
P 2= A 1 A 0 B 1 + A 1 B 1 B 0
P3 = A1 A 0 B 1 B0
Note that the expression for P1can be modified as follows:
-
P 1= A 1 B 1 B 0 + A1 A 0 B 0 + A 1 A 0 B 1+ A 0 B1 B 0
P1= A1 B 0 (A 0 B 1)+ A0 B1 (A 1 B0 )
P 1= A 1 B 0+ A 0 B1
Further, these expressions can be used to implement the circuit
of a 2-bit binary multiplier.
Procedure:
I. Mount the respective Integrated Circuits in the sockets
available for the same on the workspace.
II. With the help of the pin diagrams of the respective ICs,
locate the pins for inputs, outputs, VCC and GND.
III. Using jumper male to male wires connect the VCC of each
IC to the supply of +5V. Also, connect the GND of each IC to
0V.
IV. As per the expressions obtained of the respective bits,
make the required connections using male to male jumper
wires.
V. In order to view the output obtained, connect the final
output pins to the LEDs using male to female jumper wires.
VI. Connect the workspace with the transformer, and connect
the transformer to the power supply.
VII. Verify the correctness of the circuit implemented using the
constructed truth table.
Results/Observations:
Following are the various images of the circuit that was
implemented showing different test cases. The corresponding
implementation of the circuit on proteus is included as well for
proper demonstration of each of the test cases: -
Figure-4: The output of the multiplier being 0000 when
inputs are 11 and 00
Figure-5: The corresponding test case as implemented on
proteus software
Figure-6: The output of the multiplier being 0100 when
inputs are 10 and 10
Figure-7: The corresponding test case as implemented on
proteus software
Figure-8: The output of the multiplier being 0110 when
inputs are 10 and 11
Figure-9: The corresponding test case as implemented on
proteus software
Figure-10: The output of the multiplier being 1001 when
inputs are 11 and 11
Figure-11: The corresponding test case as implemented
on proteus software
Conclusion:
