MP1475S

High-Efficiency, 3A, 16V, 500kHz

Synchronous, Step-Down Converter
The Future of Analog IC Technology

DESCRIPTION FEATURES
The MP1475S is a high-frequency, • Wide 4.5V to 16V Operating-Input Range
synchronous, rectified, step-down, switch-mode • 120mΩ/50mΩ Low RDS(ON) Internal Power
converter with built-in power MOSFETs. It MOSFETs
offers a compact solution to achieve a 3A • High-Efficiency Synchronous-Mode
continuous output current with excellent load Operation
and line regulation over a wide input-supply • Fixed 500kHz Switching Frequency
range. The MP1475S has synchronous-mode • Synchronizes from a 300kHz to 2MHz
operation for higher efficiency over the output External Clock
current-load range. • Power-Save Mode at Light Load
Current-mode operation provides fast, transient • Internal Soft-Start
response and eases loop stabilization. • Power Good Indicator
Full protection features include over-current • Over-Current Protection and Hiccup
protection (OCP) and thermal shut down (TSD). • Thermal Shutdown
• Output Adjustable from 0.8V
The MP1475S requires a minimal number of • Available in a 8-pin TSOT-23 Package
readily available, standard, external
components and is available in a space-saving APPLICATIONS
8-pin TSOT23 package. • Notebook Systems and I/O Power
• Digital Set-Top Boxes
• Flat-Panel Television and Monitors
• Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.

TYPICAL APPLICATION

12V

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ORDERING INFORMATION
Part Number* Package Top Marking
MP1475SGJ TSOT23-8 See Below

* For Tape & Reel, add suffix –Z (e.g. MP1475SGJ–Z);

TOP MARKING

AMX: product code of MP1475SGJ;

Y: year code;

PACKAGE REFERENCE

TOP VIEW

PG 1 8 FB

IN 2 7 VCC

SW 3 6 EN/SYNC

GND 4 5 BST

TSOT23-8

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ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance

(5)
θJA θJC
VIN ................................................ -0.3V to 17V TSOT23-8 ............................. 100 ..... 55 ... °C/W
VSW ....................................................................
Notes:
-0.3V (-5V for <10ns) to 17V (19V for <10ns) 1) Exceeding these ratings may damage the device.
VBST ...................................................... VSW+6V 2) About the details of EN/SYNC pin’s ABS MAX rating, please
All Other Pins ................................ -0.3V to 6V (2) refer to Page 12, Enable/SYNC control section.
(3) 3) The maximum allowable power dissipation is a function of the
Continuous Power Dissipation (TA = +25°C) maximum junction temperature TJ (MAX), the junction-to-
.......................................................... 1.25W ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
Junction Temperature .............................. 150°C any ambient temperature is calculated by PD (MAX) = (TJ
Lead Temperature ................................... 260°C (MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
Storage Temperature ................. -65°C to 150°C regulator will go into thermal shutdown. Internal thermal
(4) shutdown circuitry protects the device from permanent
Recommended Operating Conditions damage.
Supply Voltage VIN .......................... 4.5V to 16V 4) The device is not guaranteed to function outside of its
operating conditions.
Output Voltage VOUT............... 0.8V to VIN*DMAXV 5) Measured on JESD51-7, 4-layer PCB.
Operating Junction Temp. (TJ). -40°C to +125°C

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ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Typical value is tested at TJ=+25°C.
Parameter Symbol Condition Min Typ Max Units
Supply Current (Shutdown) IIN VEN = 0V 2 μA
Supply Current (Quiescent) Iq VEN = 2V, VFB = 1V 0.5 1 mA
HS Switch-On Resistance HSRDS-ON VBST-SW =5V 120 mΩ
LS Switch-On Resistance LSRDS-ON VCC =5V 50 mΩ
Switch Leakage SW LKG VEN = 0V, VSW =12V or 0V 1 μA
(6) Under 40% TJ=+25°C 3.7 5 A
Current Limit ILIMIT Duty Cycle TJ=-40°C to +125°C 3.5 A
TJ=+25°C 410 500 630 kHz
Oscillator Frequency fSW VFB=0.75V
TJ=-40°C to +125°C 350 650 kHz
Foldback Frequency fFB VFB<400mV 0.5 fSW
Maximum Duty Cycle DMAX VFB=700mV 90 95 %
(6)
Minimum On Time TON-MIN 40 ns
Sync Frequency Range fSYNC 0.3 2 MHz
TJ =25°C 791 807 823
Feedback Voltage VFB (7) mV
-40°C<TJ<+125°C 787 807 827
Feedback Current IFB VFB=830mV 10 50 nA
EN Rising Threshold VEN-RISING 1 1.4 1.75 V
EN Falling Threshold VEN-FALLING 0.9 1.25 1.6 V
VEN=2V 2 μA
EN Input Current IEN
VEN=0 0 μA
EN Turn-Off Delay ENtd-off 8 μs
Power-Good Rising Threshold PGvth-Hi 0.9 VFB
Power-Good Falling Threshold PGvth-Lo 0.85 VFB
Power-Good Delay PGTd 0.6 ms
Power-Good Sink-Current
VPG Sink 2mA 0.4 V
Capability
Power-Good Leakage Current IPG-LEAK 1 μA
VIN Under-Voltage Lockout
INUVVth 3.6 3.9 4.3 V
Threshold—Rising
VIN Under-Voltage Lockout
INUVHYS 700 mV
Threshold—Hysteresis
VCC Regulator VCC 5 V
VCC Load Regulation ICC=5mA 2 %
Soft-Start Period TSS Vo from 10% to 90% 1.2 ms
(6)
Thermal Shutdown TSD 150 °C
(6)
Thermal Hysteresis TSD HYS 20 °C
Notes:
6) Guaranteed by design.
7) Not tested in production; guaranteed by over-temperature correlation.

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TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.
Line Regulation Case Temperature Rise vs.
VOUT=3.3V, VIN=5-16V Output Current
IOUT=0A-3A
0.7 0.2 50
0.5 0.15 45

VIN=12V 0.1 40
0.3
35
0.05 IOUT=1.5A
0.1 30 VOUT=5V
VIN=5V 0 25
-0.1
-0.05 IOUT=3A 20
-0.3 IOUT=0A 15
-0.1
VIN=16V 10 VOUT=3.3V
-0.5 -0.15
5
-0.7 -0.2 0
0 0.5 1 1.5 2 2.5 3 3.5 4 8 12 16 0 0.5 1 1.5 2 2.5 3
LOAD CURRENT(A) VIN(V) OUTPUT CURRENT(A)

Current Limit vs. Disabled Supply Current Enabled Supply Current

Duty Cycle vs. Input Voltage vs. Input Voltage
VIN=4.5V to 16V VEN=0V VIN=4.5V to 16V VFB=1V
6 6 530
520
5.5 5
510
CURRENT LIMIT(A)

5 4
500

4.5 3 490
480
4 2
470
3.5 1 460

3 0 450
0 10 20 30 40 50 60 70 80 4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 18
INPUT VOLTAGE(V) INPUT VOLTAGE(V)

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.
Short Entry Short Recovery Start-Up through Enable
IOUT=0A IOUT=0A IOUT=0A

VOUT VOUT VOUT

2V/div. 2V/div. 2V/div.
VPG VPG VPG
5V/div. 5V/div. 5V/div.

VIN VIN VEN

10V/div. 10V/div. 5V/div.
VSW VSW VSW
10V/div. 10V/div. 10V/div.

IINDUCTOR IINDUCTOR IINDUCTOR

5A/div. 5A/div. 2A/div.

Start-Up through Enable Shutdown through Shutdown through

IOUT=3A Enable Enable
IOUT=0A IOUT=3A

VOUT VOUT VOUT

2V/div. 2V/div. 2V/div.
VPG VPG VPG
5V/div. 5V/div. 5V/div.

VEN VEN VEN

5V/div. 5V/div. 5V/div.
VSW VSW VSW
10V/div. 10V/div. 10V/div.

IINDUCTOR IINDUCTOR IINDUCTOR

2A/div. 2A/div. 2A/div.

Start-Up through Input Start-Up through Input Shutdown through

Voltage Voltage Input Voltage
IOUT=0A IOUT=3A IOUT=0A

VOUT VOUT VOUT

2V/div. 2V/div. 2V/div.
VPG VPG
VPG 5V/div.
5V/div. 5V/div.

VIN VIN VIN

5V/div. 5V/div. 5V/div.
VSW VSW VSW
5V/div. 5V/div. 5V/div.

IINDUCTOR IINDUCTOR IINDUCTOR

2A/div. 2A/div. 2A/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.

Shutdown through Input / Output Ripple Load Transient Reponse

Input Voltage IOUT=3A IOUT=1.5A-3A
IOUT=3A

VOUT/AC
VOUT 20mV/div.
2V/div.
VPG VIN/AC VOUT/AC
5V/div. 100mV/div.
200mV/div.

VIN
5V/div.
VSW
VSW 10V/div.
5V/div.
IOUT
IINDUCTOR 2A/div.
IINDUCTOR
2A/div.
2A/div.

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PIN FUNCTIONS
Package
Name Description
Pin #
Power Good Indicator. PG is the open drain of the internal MOSFET and should be
connected to VCC (or another voltage source) through a resistor (e.g. 100k). When the FB
1 PG
voltage reaches 90% of the REF voltage, PG is pulled high (after a 0.6ms delay). After the
FB voltage drops to 85% of the REF voltage, PG is pulled low.
Supply Voltage. IN supplies power for the internal MOSFET and regulator. The MP1475S
operates from a +4.5V to +16V input rail; it requires a low ESR and a low-inductance
2 IN
capacitor (C1) to decouple the input rail. Place the input capacitor very close to IN and
connect it with wide PCB traces and multiple vias.
Switch Output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to VIN
by the high-side switch during the PWM duty cycle on-time. The inductor current drives
3 SW
SW negative during the off-time. The on resistance of the low-side switch and the internal
body diode fixes the negative voltage. Connect using wide PCB traces and multiple vias.
System Ground. GND is the reference ground of the regulated output voltage. PCB layout
4 GND requires extra care (see recommended “PCB Layout Guidelines” on page 16). For best
results, connect to GND with copper and vias.
Bootstrap. BST requires a capacitor connected between SW and BST to form a floating
5 BST
supply across the high-side switch driver.
Enable/Synchronize. EN/SYNC=high to enable the MP1475S. Apply an external clock to
6 EN/SYNC change the switching frequency. For automatic start-up, connect EN/SYNC to VIN with a
100kΩ resistor.
Internal 5V LDO Output. VCC powers the driver and control circuits. Decouple with a
7 VCC
0.1μF to 0.22μF capacitor. Do NOT use a capacitor ≥0.22μF.
Feedback. Connect FB to the tap of an external resistor divider from the output to GND to
set the output voltage. To prevent current-limit runaway during a short-circuit fault, the
8 FB frequency foldback comparator lowers the oscillator frequency when the FB voltage is
below 400mV. Place the resistor divider as close to FB as possible. Avoid placing vias on
the FB traces.

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FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

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OPERATION
The MP1475S is a high-frequency, value set by VCOMP (after a period of dead time),
synchronous, rectified, step-down, switch-mode and the low-side MOSFET (LS-FET) turns on
converter with built-in power MOSFETs. It and remains on until the inductor-current value
offers a compact solution that achieves a 3A decreases to zero. The device repeats the
continuous output current with excellent load same operation in every clock cycle to regulate
and line regulation over 4.5V to 16V input- the output voltage (see Figure 3).
supply range.
The MP1475S has three working modes:
advanced asynchronous modulation (AAM)
mode, discontinuous conduction mode (DCM),
and continuous conduction mode (CCM). The IL
load current increases as the device transitions
from AAM mode to DCM to CCM.
AAM Control Operation
Figure 3. DCM Control Operation
In a light-load condition, MP1475S works in
advanced asynchronous modulation (AAM) CCM Control Operation
mode (see Figure 2). The VAAM is an internal The device enters continuous conduction mode
fixed voltage when input and output voltages (CCM) from DCM once the inductor current no
are fixed. VCOMP is the error-amplifier output longer drops to zero in a clock cycle. In CCM,
(which represents the peak inductor-current the internal clock initiates the PWM cycle, the
information). When VCOMP is lower than VAAM, HS-FET turns on and remains on until VILsense
the internal clock is blocked. This causes the reaches the value set by VCOMP (after a period
MP1475S to skip pulses, achieving the light- of dead time), and the LS-FET turns on and
load power save. Refer to AN032 for additional remains on until the next clock cycle begins.
details. The device repeats the same operation in every
clock cycle to regulate the output voltage.
The internal clock re-sets every time VCOMP is
higher than VAAM. At the same time, the high- If VILsense does not reach the value set by VCOMP
side MOSFET (HS-FET) turns on and remains within 95% of one PWM period, the HS-FET is
on until VILsense reaches the value set by VCOMP. forced off.
Internal Regulator
The light-load feature in this device is optimized A 5V internal regulator powers most of the
for 12V input applications. internal circuitries. This regulator is supplied by
VIN and operates in the full VIN range. When VIN
exceeds 5V, the output of the regulator is in full
regulation. When VIN is less than 5V, the output
decreases, and the device requires a 0.1µF
ceramic decoupling capacitor.
Error Amplifier (EA)
The error amplifier compares the FB voltage to
Figure 2. Simplified AAM Control Logic the internal 0.807V reference (VREF) and
DCM Control Operation outputs a current proportional to the difference
The VCOMP voltage ramps up as the output between the two. This output current then
current increases. When its minimum value charges or discharges the internal
exceeds VAAM, the device enters discontinuous compensation network to form the COMP
conduction mode (DCM). In DCM, the internal voltage, which controls the power MOSFET
clock initiates the PWM cycle, the HS-FET turns
on and remains on until VILsense reaches the

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current. The optimized, internal compensation Figure 5). For best results, set the UVLO falling
network minimizes the external component threshold (VSTOP) above 4.5V using the
count and simplifies the control loop design. enable resistors. Set the rising threshold
(VSTART) to provide enough hysteresis to
Enable/SYNC Control
allow for input-supply variations.
EN/SYNC is a digital control pin that turns the
regulator on and off. Drive EN/SYNC high to
turn on the regulator; drive EN/SYNC low to
turn off the regulator. An internal 1MΩ resistor
from EN/SYNC to GND allows EN/SYNC to be
floated to shut down the chip.
REN_UP
EN/SYNC is clamped internally using a 6.5V
series-Zener-diode (see Figure 4). Connecting
EN/SYNC through a pull-up resistor to the
voltage on IN limits the EN/SYNC input current REN_DOWN EN/SYNC
to less than 100µA.
For example, with 12V connected to IN, RPULLUP
≥ (12V – 6.5V) ÷ 100µA = 55kΩ. Figure 5. Adjustable UVLO
Connecting EN/SYNC directly to a voltage Internal Soft-Start (SS)
source without a pull-up resistor requires The soft-start prevents the converter output
limiting the amplitude of the voltage source to voltage from overshooting during start-up.
≤6V to prevent damage to the Zener diode. When the chip starts up, the internal circuitry
generates a soft-start voltage (VSS) that ramps
up from 0V to 1.2V. When VSS is less than VREF,
the error amplifier uses VSS as the reference.
When VSS exceeds VREF, the error amplifier
uses VREF as the reference. The SS time is set
internally to 1.2ms.
Pre-Bias Start-Up
Figure 4. 6.5V Zener Diode Connection
For external clock synchronization, connect a The MP1475S is designed for a monotonic
clock with a frequency range between 300kHz start-up into pre-biased loads. If the output is
and 2MHz. The internal clock rising edge pre-biased to a certain voltage during start-up,
synchronizes with the external clock rising edge. the BST voltage is refreshed and charged. Also,
Select an external clock signal with a pulse the voltage on the soft-start capacitor is
width less than 1.7μs. charged. If BST voltage exceeds its rising
threshold voltage, and the soft-start capacitor
Under-Voltage Lockout (UVLO) voltage exceeds the sensed-output voltage at
The MP1475S has under-voltage lockout FB, the device starts to operate normally.
protection (UVLO). When the VCC voltage
exceeds the UVLO rising threshold voltage, the Power Good Indicator (PG)
device begins to power-up. The device shuts off MP1475S has an open-drain pin as the power
when the VCC voltage drops below the UVLO good indicator (PG). Pull PG up to VCC (or
falling threshold voltage. This is non-latch another external source) through a 100kΩ
protection. resistor. When VFB exceeds 90% of VREF, PG
goes high (after a 0.6ms delay time). If VFB falls
The MP1475S is disabled when the input below 85% of VREF, an internal MOSFET pulls
voltage falls below 3.2V. If an application PG down to ground.
requires a higher under-voltage lockout (UVLO)
threshold, use EN/SYNC to adjust the input
voltage UVLO using two external resistors (see

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Over-Current Protection (OCP) and Hiccup If both VIN and VEN exceed their respective
The MP1475S has a cycle-by-cycle over- thresholds, the chip starts up. The reference
current limit when the inductor current peak block starts first, generating stable reference
value exceeds the set current-limit threshold. voltage and currents, then the internal regulator
Meanwhile, the output voltage drops until VFB is is enabled. The regulator provides a stable
below the under-voltage (UV) threshold (50% supply for the remaining circuitries.
below the reference, typically). Once UV is
Three events can shut down the chip: VEN low,
triggered, the MP1475S enters hiccup mode to
VIN low, and thermal shutdown. During the
re-start the part periodically. This protection
shutdown procedure, the signaling path is
mode is useful when the output is dead-shorted
blocked first to avoid any fault triggering. The
to ground and greatly reduces the average
COMP voltage and the internal supply rail are
short-circuit current to alleviate thermal issues
then pulled down. The floating driver is not
and protect the regulator. The MP1475S exits
subject to this shutdown command.
hiccup mode once the over-current condition is
removed.
Thermal Shutdown (TSD)
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the die temperature exceeds 150°C, it
shuts down the whole chip. When the
temperature drops below its lower threshold
(130°C, typically), the chip is enabled again.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. The
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally by VIN through D1,
M1, R3, C4, L1, and C2 (see Figure 6). If (VIN-
VSW) exceeds 5V, U1 regulates M1 to maintain
a 5V BST voltage across C4. It is
recommended strongly to place a 20Ω resistor
between the SW and BST cap to reduce SW
spike voltage.

D1
VIN

M1
BST

5V U1 R3
C4

VOUT
SW L1 C2

Figure 6. Internal Bootstrap Charging Circuit

Start-Up and Shutdown

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APPLICATION INFORMATION VOUT × (VIN − VOUT )

L1 =
Setting the Output Voltage VIN × ΔIL × fOSC
The external resistor divider sets the output Where ΔIL is the inductor-ripple current.
voltage (see “Typical Application” on page 1).
Choose R1 around 40.2kΩ; R2 is then given by: Choose an inductor-ripple current
approximately 30% of the maximum load
R1 current. The maximum inductor peak current is
R2 = calculated by the following equation:
VOUT
−1 ΔIL
0.807V IL(MAX ) = ILOAD +
2
The T-type network is recommended highly
Use a larger inductor for improved efficiency
when VOUT is low (see Figure 7).
under light-load conditions (below 100mA).
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, therefore it requires a capacitor
to supply the AC current while maintaining the
DC input voltage. Use low ESR capacitors for
optimum performance. Use ceramic capacitors
Figure 7. T-Type Network with X5R or X7R dielectrics for best results
Table 1 lists the recommended T-type resistor because of their low ESR and small
values for common output voltages. temperature coefficients. For most applications,
use a 22µF capacitor.
Table 1. Resistor Selection for Common Output
Voltages
(8)
Since C1 absorbs the input-switching current, it
VOUT requires an adequate ripple-current rating. The
R1 (kΩ) R2 (kΩ) Rt (kΩ) RMS current in the input capacitor is estimated
(V)
1.0 20.5 84.5 82 by:
1.2 30.1 61.9 82 VOUT ⎛⎜ VOUT ⎞
I C1 = ILOAD × × 1− ⎟
1.8 40.2 32.4 33 VIN ⎜⎝ VIN ⎟
⎠
2.5 40.2 19.1 33
The worst case condition occurs at VIN = 2VOUT,
3.3 40.2 13 16 where:
5 40.2 7.68 16
Notes: ILOAD
IC1 =
8) The recommended parameters are based on a 500kHz 2
switching frequency; a different input voltage, output-inductor
value, and output-capacitor value may affect the selection of For simplification, choose an input capacitor
R1, R2, and Rt. For additional component parameters, please that has a RMS current rating greater than half
refer to the “Typical Application Circuits” section on pages 17
and 18. of the maximum load current.
Selecting the Inductor The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
For most applications, use a1µH to 22µH capacitors, a small, high-quality ceramic
inductor with a DC current rating at least 25% capacitor (e.g. 0.1μF) should be placed as
higher than the maximum load current. For close to the IC as possible. When using
highest efficiency, use an inductor with a DC ceramic capacitors, ensure that they have
resistance less than 15mΩ. For most designs, enough capacitance to provide sufficient charge
the inductance value is derived from the
following equation:

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External Bootstrap Diode

in order to prevent excessive voltage ripple at
input. The input-voltage ripple caused by In particular conditions, BST voltage may
capacitance is estimated as: become insufficient (see equations below).
ILOAD V ⎛ V ⎞ During these conditions an external bootstrap
ΔVIN = × OUT × ⎜ 1 − OUT ⎟ diode can enhance the efficiency of the
fS × C1 VIN ⎝ VIN ⎠
regulator and avoid insufficient BST voltage at
Selecting the Output Capacitor light-load PFM operation. Insufficient BST
The output capacitor (C2) maintains the DC voltage is more likely to occur during either of
output voltage. Use ceramic, tantalum, or low the following conditions:
ESR electrolytic capacitors. For optimum z VIN is below 5V
results, use low ESR capacitors to keep the z VOUT is 5V or 3.3V; and Duty cycle is high:
output-voltage ripple low. The output-voltage VOUT
ripple is estimated as: D= >65%
VIN
VOUT ⎛ VOUT ⎞ ⎛ 1 ⎞ If the BST voltage is insufficient, the output-
ΔVOUT = × ⎜1 − ⎟ × ⎜ RESR + ⎟
fS × L1 ⎝ VIN ⎠ ⎝ 8 × fS × C2 ⎠ ripple voltage may become extremely large
during a light-load condition. If this occurs, add
Where L1 is the inductor value and RESR is the an external BST diode from VCC to BST (see
equivalent series resistance (ESR) value of the Figure 8).
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching MP1475S
frequency, and the capacitance causes the
majority of the output-voltage ripple. For
simplification, the output-voltage ripple can be
estimated as:
VOUT ⎛ V ⎞ Figure 8. Optional External Bootstrap Diode to
ΔVOUT = × ⎜ 1 − OUT ⎟ Enhance Efficiency
8 × fS × L1 × C2 ⎝
2
VIN ⎠
The recommended external BST diode is
For tantalum or electrolytic capacitors, the ESR IN4148, and the BST capacitor value is 0.1µF
dominates the impedance at the switching to1μF.
frequency. For simplification, the output-ripple is
approximated as:
VOUT ⎛ V ⎞
ΔVOUT = × ⎜ 1 − OUT ⎟ × RESR
fS × L1 ⎝ VIN ⎠

The characteristics of the output capacitor

affect the stability of the regulation system. The
MP1475S can be optimized for a wide range of
capacitance and ESR values.

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PCB Layout Guidelines (9)

Efficient PCB layout is critical to achieve stable VOUT

operation, especially for the placement of the GND

VCC capacitor and input capacitor. For best VCC

results, refer to Figure 9 and the guidelines EN/SYNC

below:
BST

1. Use large ground plane to connect directly

SW
to GND. If the bottom layer is ground plane,
add vias near GND.
2. Place the VCC capacitor as close as
possible to VCC and GND. The trace
length of VCC to the VCC capacitor anode
to the VCC capacitor cathode to GND
should be as short as possible. GND
3. Place the ceramic input capacitor close to
IN and GND. Keep the connection between
the input capacitor and IN as short and
wide as possible. Bottom Layer
4. Route SW and BST away from sensitive Figure 9. Recommended PCB Layout
analog areas (such as FB). Design Example
5. Place the T-type feedback resistor R6 very Table 2 shows a design example following the
close to the chip to ensure the trace application guidelines for the specifications:
connected to FB is as short as possible. Table 2. Design Example
Notes:
9) The recommended layout is based on Figure 10 in the “Typical
VIN 12V
Application Circuits” section on page 17. VOUT 3.3V
IOUT 3A
The detailed application schematic is shown in
Figure 11. The typical performance and circuit
waveforms have been shown in the “Typical
Performance Characteristics” section. For more
device applications, please refer to the related
evaluation board datasheets.

Top Layer

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TYPICAL APPLICATION CIRCUITS

R3
20
VIN 2 5
IN BST
C1 C1A
0.1uF C4
22uF
25V 25V MP1475S 0.1uF
L1
GND GND 4.7uH VOUT
7 3
5V/3A
VCC VCC SW
C5 C2 C2A
0.1uF 22uF 22uF
R5
100k
GND
GND GND
1
PG PG C3
15pF
R4
100k
R6
16k
6 8
EN/SYNC EN/SYNC FB
R1
GND 40.2k
R2

4
7.68k

GND
GND

Figure 10. 12VIN, 5V/3A Output

R3
20
VIN 2 5
IN BST
C1 C1A
0.1uF C4
22uF
25V 25V MP1475S 0.1uF
L1
GND GND 4.7uH VOUT
7 3
3.3V/3A
VCC VCC SW
C5 C2 C2A
0.1uF 22uF 22uF
R5
100k
GND
GND GND
1
PG PG C3
15pF
R4
100k
R6
16k
6 8
EN/SYNC EN/SYNC FB
R1
GND 40.2k
R2
4

13k

GND
GND

Figure 11. 12VIN, 3.3V/3A Output

R3
20
VIN 2 5
IN BST
C1 C1A
0.1uF C4
22uF
25V 25V MP1475S 0.1uF
L1
GND GND 3.3uH VOUT
7 3
2.5V/3A
VCC VCC SW
C5 C2 C2A
0.1uF 22uF 22uF
R5
100k
GND
GND GND
1
PG PG C3
15pF
R4
100k
R6
33k
6 8
EN/SYNC EN/SYNC FB
R1
GND
40.2k
R2
4

19.1k

GND
GND

Figure 12. 12VIN, 2.5V/3A Output

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R3
20
VIN 2 5
IN BST
C1 C1A
0.1uF C4
22uF
25V 25V MP1475S 0.1uF
L1
GND GND 3.3uH VOUT
7 3
1.8V/3A
VCC VCC SW
C5 C2 C2A
0.1uF 22uF 22uF
R5
100k
GND
GND GND
1
PG PG C3
15pF
R4
100k
R6
33k
6 8
EN/SYNC EN/SYNC FB
R1
GND
40.2k
R2

4
32.4k

GND
GND

Figure 13. 12VIN, 1.8V/3A Output

R3
20
VIN 2 5
IN BST
C1 C1A
0.1uF C4
22uF
25V 25V MP1475S 0.1uF
L1
GND GND 2.2uH VOUT
7 3
1.2V/3A
VCC VCC SW
C5 C2 C2A
0.1uF 22uF 22uF
R5
100k
GND
GND GND
1
PG PG C3
15pF
R4
100k
R6
82k
6 8
EN/SYNC EN/SYNC FB
R1
GND 30.1k
R2
4

61.9k

GND
GND

Figure 14. 12VIN, 1.2V/3A Output

R3
20
VIN 2 5
IN BST
C1 C1A
0.1uF C4
22uF
25V 25V MP1475S 0.1uF
L1
GND GND 2.2uH VOUT
7 3
1V/3A
VCC VCC SW
C5 C2 C2A
0.1uF 22uF 22uF
R5
100k
GND
GND GND
1
PG PG C3
15pF
R4
100k
R6
82k
6 8
EN/SYNC EN/SYNC FB
R1
GND 20.5k
R2
4

84.5k

GND
GND

Figure 15. 12VIN, 1V/3A Output

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PACKAGE INFORMATION
TSOT23-8

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.

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