lOMoARcPSD|43633637

Analog and Digital Electronics Lab Manual 2023-24

Analog design (Smt Kamala And Sri Venkappa M. Agadi College of Engineering &
Technology)

Scan to open on Studocu

Studocu is not sponsored or endorsed by any college or university

Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

ANALOG AND DIGITAL SYSTEMS

rd
3 SEMESTER
DESIGN (21ECL35)
LABORATORY
MANUAL 3 SEMESTER B.E RD

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Smt. Kamala and Sri. Venkappa M Agadi College of Engineering and Technology,
Lakshmeshwar

Downloaded by Ananya C (ananyac0413@[Link])

 lOMoARcPSD|43633637

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ANALOG AND DIGITAL SYSTEMS DESIGN

LABORATORY MANUAL
BECL305
SEMESTER – III (EC) CBCS scheme

Prepared By: 1)[Link] P K

2)Mr. Amarappa Pagi

2023-24

Downloaded by Ananya C (ananyac0413@[Link])

 lOMoARcPSD|43633637

SKSVMA Charitable Trust (Regd.)

Smt. Kamala & Sri Venkappa M Agadi College of Engineering & Technology
Lakshmeshwar 582116 Dist: Gadag
(Approved by AICTE, New Delhi & Affiliated to VTU Belagavi, ISO 9001:2015 Certified)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Laboratory Name: ANALOG & DIGITAL SYSTEMS DESIGN LABORATORY

Subject Code: BECL305

Branch : ELECTRONICS AND COMMUNICATION ENGINEERING

Semester: 3

Downloaded by Ananya C (ananyac0413@[Link])

 lOMoARcPSD|43633637

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

SEMESTER – III (EC)
[As per NEP, OBE & CBCS scheme]

CONTENTS

Sl. PARTICULARS Page

No. No.
i Laboratory Safety Information 02
ii Circuit Trouble Shooting Hints 03
iii Component Symbol and Description 04
iv Bread Board Connection Diagram and Standard Resistor Values - Color Coding 06
v CIE Marks Scheme of Evaluation 07
v General Procedure to be followed by the student 08
vi VTU Syllabus 09
PART A : Analog Electronics Experiments using Discrete components
1. Design and set up the BJT common emitter voltage amplifier with and without feedback and
02
determine the gain- bandwidth product, input and output impedances.
2. Design and set-up BJT/FET i) Colpitt’s Oscillator, and ii) Crystal Oscillator 06

3. Design and setup the circuits using Op-Amp i) Adder, ii) Integrator, iii) Differentiator and iv) 11
Comparator

4. Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input from 20
toggle switches and (ii) by generating digital inputs using mod-16 counter.
5. Design and implement: (a) Half Adder & Full Adder using basic gates and NAND gates, 23
(b) Half subtractor & Full subtractor using NAND gates,
4-variable function using IC74151(8:1MUX).
6. Realize: (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-3 code
conversion and vice versa
7. a) Realize using NAND Gates: (i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop
b) Realize the shift registers using IC7474/7495:
SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter.

8. Realize: (a) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-
flop, (b) Mod-N Counter using IC7490 / 7476 & (c) Synchronous counter using IC74192

1
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Demonstration Experiments (For CIE)

9. Design and test the second order active filters and plot the frequency response,
i) Low pass and High pass filter
ii) Bandpass and Band stop filter

10. Design and test the following using 555 Timer

i) Monostable Vibrator
ii) Astable Multivibrator

11. Design and Test a regulated power supply

12. Design and Test an audio amplifier by connecting a microphone input and observe the
output using a loud speaker.

2
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Laboratory Safety Information

----------------------------------------------------------------------------------------------------

To work safely, it is important that you understand the prudent practices necessary to
minimize the risks and what to do if there is an accident.

-----------------------------------------------------------------------------------------------------------------------
Electrical Shock
-------------------------------------------------------------------------------------------------

Avoid contact with conductors in energized electrical circuits.

Electrocution has been reported at de voltages as low as 42 volts. Just 100 mA of

current passing through the chest is usually fatal.

Muscle contractions can prevent the person from moving away while being
electrocuted.

Do not touch someone who is being shocked while still in contact with the electrical
conductor or you may also be electrocuted.

Make sure your hands are dry.

The resistance of dry, unbroken skin is relatively high and thus reduces the risk of
shock. Skin that is broken, wet or damp with sweat has a low resistance.

When working with an energized circuit, work with only your right hand, keeping your
left hand away from all conductive material. This reduces the likelihood of an accident
that results in current passing through your heart.

Be cautious of rings, watches, and necklaces. Skin beneath a ring or watch is damp,
lowering the skin resistance.

Shoes covering the feet are much safer than sandals.

3
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Circuit Trouble Shooting Hints

----------------------------------------------------------------------------

✓ Be sure that the power is turned on.

✓ Be sure the ground connections are common.

✓ Be sure the circuit you built is identical to that in the diagram. (Do a node-by-node
check)

✓ Be sure that the supply voltages are correct.

✓ Be sure you plug in cable to the right terminal in the multimeter to measure the
voltage/resistance (upper terminal) or the current (lower terminal).

✓ Be sure that the equipment is set up correctly and you are measuring the correct
parameter.

✓ Be sure the BJT’s collector and emitter terminals are in correct orientation.

✓ If steps 1 through 5 are correct, then you probably have used a component with the
wrong value or one that doesn't work.

✓ It is also possible that the equipment does not work (although this is not probable) or
the bread-board you are using may have some unwanted paths between nodes.

✓ To find your problem you must trace through the voltages in your circuit node by
node and compare the signal you have to the signal you expect to have.

✓ Finally, ask your lab assistant.

4
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Component Symbol and Description

Component Circuit Symbol Function of Component

Wire To pass current from one part of a circuit to another.

Wires connected at junctions should be staggered slightly

Wires joined
to form two T-junctions, as shown.

Wires crossing even though they are not

Wires not joined
connected.
The Fuse reacts as safety element to protect circuit
Fuse
against large current and sudden urges of current.

Switch
SPST = Single Pole, Single Throw. An on-off switch allows
(SPST) current to flow only when it is in the closed (on) position.

Cell Supplies electrical energy. The larger terminal is

Cell
positive (+). A single cell is often called a battery, but
strictly a battery is two or more cells joined together.
Supplies electrical energy. A battery is more than one cell.
Battery
The larger terminal is positive (+).

AC Supply This represents AC supply in the circuit.

DC Supply This represents the DC power supply. It applies DC supply

to the circuit.

It is equivalent to theoretical 0 V and is used as zero

Ground potential reference. It is the potential of perfectly
conducting earth.
Fixed Resistor OR It is a device that opposes the flow of current in a circuit.
These two symbols are used to represent fixed resistor.
It is a two terminal variable resistor. They are generally
OR used to control the current in the circuit. Generally used in
Rheostat
tuning circuits and power control applications like heaters,
ovens etc
Capacitor stores the charge in the form of electrical
Capacitor
energy. It can be used in both AC and DC circuits.
Almost all electrolytic capacitors are polarized and hence
Electrolytic
used in DC circuits. It can also be used as a filter, to block
Capacitor
DC signals but pass AC signals.

5
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Component Circuit Symbol Function of Component

A coil of wire which creates a magnetic field when current

Iron Core Inductor
passes through it.
Two coils of wire linked by an iron core. Transformers are
used to step up (increase) and step down (decrease) AC
Transformer
voltages. Energy is transferred between the coils by the
magnetic field in the core. There is no electrical
connection between the coils.
A device which only allows current to flow in one
Diode
direction.

LED A transducer which converts electrical energy to light.

LDRs or photo-resistors are often used in circuits where it

LDR is necessary to detect the presence or the intensity level
of light.
A special diode which is used to maintain a fixed voltage
Zener Diode
across its terminals.
Transistor
A transistor amplifies current. It can be used with other
(NPN)
components to make an amplifier or switching circuit.

A voltmeter is used to measure voltage. The proper name

Voltmeter
for voltage is 'potential difference', but most people
prefer to say voltage!

Ammeter An ammeter is used to measure current.

N-channel JFET is made by n-type silicon bars which form

JFET
two PN junctions at the side. Majority charge carriers here
N- Channel
are electrons.

MOSFET
The enhancement MOSFET structure has no channel
P-Channel
formed during its construction. Voltage is applied to the
gate, so as to develop a channel.

An operational amplifier (op-amp) is a DC-coupled high-

OPAMP gain electronic voltage amplifier with a differential input
and, usually, a single-ended output.

6
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Bread Board Connection Diagram

Internal Wire Connection

External Pin Connection

Standard Resistor Values and Color Coding

7
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

LAB Class Internal Examination (CIE) Marks: 50

1 Lab wise Assessment Marks

a. Record 10M
Aim & apparatus -1 M
Circuit diagram and procedure -3 M
Theory -2 M
Design/Calculations and tables -3M
Result -1 M
b. Write-up / Design for every
experiment 05M
c. Observation /conduction/result 10M
d. Viva-voce 05M 30M
2 Lab Test Assessment
Test 20M 20M

Total: 50M

Semester End Examination (SEE) Marks: 50

8
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

GENERAL PROCEDURE TO BE FOLLOWED BY THE STUDENT

Minimum of 85% to be maintained. [Attendance at your regularly

scheduled lab period is required. An unexpected absence will result in loss
Attendance
of credit for your lab. If for valid reason a student misses a lab, or makes a
reasonable request in advance].
Punctuality Late entry to the lab NOT permitted.
Dress Code Should wear formal dress and shoe, No slippers.
No eating or drinking is allowed. Unnecessary roaming around the lab to
Conduct
be avoided. Noise level is to be kept to the absolute minimum.
Safety Students are to observe safety regulations at all times.
Equipment All mains and electrical equipment are to be switched off when not in use
Usage or when the lab session ends. Equipments need to handle smooth.
House Keeping Students should keep their work station neat and clean.
Record will be written individually. Please complete the cover Page and
certificate page: Include your name, USN, Subject Code, subject Code,
Lab records
Semester, Academic year. Fill Inside pages with Experiment No., Date and
Page No.
Each laboratory station is equipped with a Power supply, CRO, Function
Hardware
generator, Digital Multi-meter, components and PCBs. Students work in
Laboratory
groups of two, but maintain individual lab Observation books and submit
Usage
individual records.

VTU SYLLABUS
ANALOG & DIGITAL SYSTEMS DESIGN
LABORATORY (BECL305)

CIE Marks 50 SEE Marks 50

Teaching Hours/Week (L:T:P: S) [Link]

Course objectives:
This laboratory course enables students to
• Understand the electronic circuit schematic and its working
• Realize and test amplifier and oscillator circuits for the given specifications
• Realize the opamp circuits for the applications such as DAC, implement mathematical functions and
precision rectifiers.
• Study the static characteristics of SCR and test the RC triggering circuit.
• Design and test the combinational and sequential logic circuits for their functionalities.
Use the suitable ICs based on the specifications and functions.
9
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

PART A : Analog Electronics Experiments using Discrete components

1. Design and set up the BJT common emitter voltage amplifier with and without feedback
anddetermine the gain- bandwidth product, input and output impedances.
2. Design and set-up BJT/FET i) Colpitt’s Oscillator, and ii) Crystal Oscillator

3. Design and setup the circuits using Op-Amp i) Adder, ii) Integrator, iii) Differentiator and
iv)Comparator

4. Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input from
toggle switches and (ii) by generating digital inputs using mod-16 counter.
5. Design and implement: (a) Half Adder & Full Adder using basic gates and NAND gates,
(c) Half subtractor & Full subtractor using NAND gates,
-variable function using IC74151(8:1MUX).
6. Realize: (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-3
code conversion and vice versa
7. Realize using NAND Gates: (i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop
Realize the shift registers using IC7474/7495:
SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter.

8. Realize: (a) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-
flop, (b) Mod-N Counter using IC7490 / 7476 & (c) Synchronous counter using IC74192

Demonstration Experiments (For CIE)

9. Design and test the second order active filters and plot the frequency response,
iii) Low pass and High pass filter
iv) Bandpass and Band stop filter

10. Design and test the following using 555 Timer

iii) Monostable Vibrator
iv) Astable Multivibrator

11. Design and Test a regulated power supply

12. Design and Test an audio amplifier by connecting a microphone input and observe the
output using a loud speaker.

10
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Course outcomes (Course Skill Set):

At the end of the course the student will be able to:
1. Design and analyze the BJT/FET amplifier and oscillator circuits.
2. Design and test Opamp circuits to realize the mathematical computations, DAC and precision
rectifiers.
3. Design and test the combinational logic circuits for the given specifications.
4. Test the sequential logic circuits for the given functionality.
Demonstrate the basic electronic circuit experiments using SCR and 555 timer.

Conduct of Practical Examination:

• All laboratory experiments are to be included for practical examination.
• Students are allowed to pick one experiment from the lot.
• Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.
• Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero.

Suggested Learning Resources:

1. Fundamentals of Electronic Devices and Circuits Lab Manual, David A Bell, 5th Edition, 2009, Oxford
University Press.
2. Op-Amps and Linear Integrated Circuits, Ramakant A Gayakwad, 4th Edition, Pearson Education,
2018. ISBN: 978-93-325-4991-3.
3. Fundamentals of Logic Design, Charles H Roth Jr., Larry L Kinney, Cengage Learning, 7th Edition.

11
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

PART - A

ANALOG ELECTRONICS
EXPERIMENTS
1. Design and set up the BJT common emitter voltage amplifier with and without feedback and
determine the gain- bandwidth product, input and output impedances.

2. Design and set-up BJT/FET i) Colpitt’s Oscillator, and ii) Crystal Oscillator

3. Design and setup the circuits using Op-Amp i) Adder, ii) Integrator, iii) Differentiator and iv)
Comparator

4. Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input from toggle
switches and (ii) by generating digital inputs using mod-16 counter.

5. Design and implement: (a) Half Adder & Full Adder using basic gates and NAND gates,
(d) Half subtractor & Full subtractor using NAND gates,
-variable function using IC74151(8:1MUX).
6. Realize: (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-3 code
conversion and vice versa
7. Realize using NAND Gates: (i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop
Realize the shift registers using IC7474/7495:
SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter.

8. Realize: (a) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop, (b)
Mod-N Counter using IC7490 / 7476 & (c) Synchronous counter using IC74192

1
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
EXPERIMENT: 01:
Design and set up the BJT common emitter voltage amplifier with and without
feedback and determine the gain- bandwidth product, input and output impedances

AIM: To obtain the frequency response characteristics of a Current Series amplifier with and without
feedback and Obtain the bandwidth.

COMPONENTS REQUIRED :
Power supply 0-30V
CRO 20MHz 1No.
Signal generator 1-1MHz
Resistors 1kΩ, 4.7k, 8.2k, 2.2k, 33k,10K
Capacitors 10µF
Transistors SL100
Bread board CRO Probes

CIRCUIT DIAGRAM: BJT amplifier without feedback

DESIGN

Let Vcc = 12V ; IC = 4mA ; VE = 2V ; VCEQ = 6V ; hfe (βDC) = 100.

To find RE :
Given VE = 2V. Therefore, RE = VE / IE  VE / IC = 500Ω Let RE = 470 ( standard)

To find RC :
From the collector loop writing KVL we get

VCC = ICRC + VCE + VE

 RC = (VCC – VCE – VE) / IC

RC = 1k RC = 1k ( standard)

2
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
To find R1 and R2 :
The base current IB = IC / hfe = 4mA / 100 = 0.04mA

Let I1 be current through R1 and I1 be 10 times of IB

Writing the base loop KVL we get VB = VE + VBE = 2 + 0.7= 2.7V VB = 2.7V

Now, R1 = (VCC – VB) / I1

R1 = (12 - 2.7)/0.4m = 23.25 k R1 = 33 k (standard)

Also R2 = VB / (I1 – IB)

R2 = 2.7/0.36m =7.5 k R2 = 8.2 k (standard)

Input impedance ( Zin) :

In order to calculate the input impedance first calculate the value of Zin (base).

Zin (base) = re  where r e is the resistance of emitter diode.

re  25mV / IC = 25mV / 4mA = 6.25
Zin(base) = re = 100 * 6.25 = 625

The input impedance of an amplifier is the input impedance seen by the A.C. source driving the amplifier.

Therefore the biasing resistor R1 and R2 are included as follows Zin = (1+re)  R1  R2 Zin = 558 k

Output impedance (Zo) :

The output impedance is given by Zo = RC  RL
Let RL = 10 k. Therefore, Zo = 909 

To find CC1 , CC2 and CE :

Let FL = 100Hz (Lower cut-off frequency)

Input coupling capacitor: CC1 = 1 / ( 2**Zin*FL) = 1/( 2**558*100) =2.85 F CC1 = 4.7 F ( standard)
Output coupling capacitor: CC2 = 1 / ( 2**(RC + RL)*Fin) =1/(2**(1k + 10k)*100)= 0.144F
CC2 = 0.1F ( standard)

Design of bypass capacitors: CE

Emitter bypass capacitor CE = 1 / ( 2** re * FL) = 1/(2** 6.25 * 100)=254.6µF

CE =100F ( standard)

PROCEDURE

1. Rig up the circuit as per the given circuit diagram.

2. Switch on the D.C. power supply = 12V is given to the circuit.
3. Check the D.C. conditions without any input signal and record in table 1.
4. Select sine wave input and set the input signal amplitude to 20mV frequency at 1kHz
constant, and observe the input / output waves on the CRO and adjust the input amplitude
such that the output is undistorted waveform. Calculate mid-band gain using AV =
Vo(p-p) / Vin(p-p).
5. Keeping the input amplitude constant, vary the frequency from 100Hz to 2MHz and note
down the corresponding output voltage (p-p) in the table 2.
3
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
6. Calculate gain in dB and plot the frequency response curve and find the bandwidth.

4
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
[NOTE: The circuit with feedback = without bypass capacitor (C E)
The circuit without feedback = with bypass capacitor]

OBSERVATIONS: Table 1 : D.C. Conditions :

Parameter VRC VCE VE VBE VB

Theoretical 4 6 2 0.7 2.7

Practical

[NOTE: Use the tabular column separately for with and without feedback circuit]

Table 2: Frequency response with feedback Vin (P-P) = 20mV

Frequ Frequ
AV (dB) = AV (dB) =
ency Vo(p-p) AV = Vo(p-p) ency Vo(p-p) AV = Vo(p-p)
/ Vin(p-p) 20*log AV / Vin(p-p) 20*log AV
Hz Hz

100 50K

200 100K

300 300K

500 500K

700 600K

1K 700K

3K 800K

5K 900K

10K 1M

20K 2M

Measurement of Input Impedance

5
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
PROCEDURE

1) Connect the circuit of Fig(1).

2) Set the following: i) DRB to zero. ii) Input (Vin) sine wave amplitude of 20mV. iii) Input sine wave
frequency to any mid band frequency (say,100 KHz).
3) Measure Vo(p-p).
4) Increase DRB till VO = Vo(p-p)/2. The corresponding DRB value gives the input impedance Zi.

Measurement of Output Impedance

PROCEDURE

1) Connect as in Fig(2).
2) Set the following: i) DRB to maximum value ii) Input (Vin) sine wave amplitude to 20mV. iii)
Input sine wave frequency to any mid band frequency (say, 100 KHz)
3) Measure Vo(p-p).
4) Decrease DRB till Vo = Vo(p-p)/2. The corresponding DRB value gives the output impedance Zo.

Bandwidth= fl-fh

Results:

With CE (Without feedback): Without CE: (With feedback):

Av (Mid-band) =. . . . . . Av (Mid-band) = . . . . . .
Bandwidth = ..................... Hz Bandwidth = ..................... Hz
Input impedance = ........Ω Input impedance = ........ Ω
Output impedance = ...........Ω Output impedance = .......... Ω
The RC-coupled amplifier was designed and rigged up and the parameters were found.

PRECAUTIONS: 1. Connections must be made with proper polarity.

2. Avoid loose and wrong connections.

6
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

EXPERIMENT: 02
Design and set-up of Colpitt’s, Crystal Oscillator using BJT

COLPITT’S OSCILLATOR

Aim: Design and set-up the Colpitt’s oscillator to determine the frequency of oscillation fo=100KHz
Using BJT

Components and equipments required:

Transistor SL 100,
Resistors 470Ω, 1KΩ 10KΩ and 33 KΩ;
Capacitors 0.1µf - 3nos,
Discrete inductances 100 µH – 2 nos,
Capacitor 470 pF – 2nos, Power supply, CRO,
Connecting wires

CIRCUIT DIAGRAM: Colpitt’s Oscillator

DESIGN:

Let Vcc = 12V ; IC = 4mA ; VE = 2V ; VCEQ = 6V ; hfe (βDC) = 100.

To find RE :
Given VE = 2V. Therefore, RE = VE / IE  VE / IC = 500Ω Let RE = 470 ( standard)
To find RC :
From the collector loop writing KVL we get
VCC = ICRC + VCE + VE
 RC = (VCC – VCE – VE) / IC

RC = 1k RC = 1k ( standard)

7
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
To find R1 and R2 :
The base current IB = IC / hfe = 4mA / 100 = 0.04mA

Let I1 be current through R1 and I1 be 10 times of IB

Writing the base loop KVL we get VB = VE + VBE = 2 + 0.7= 2.7V VB = 2.7V
Now, R1 = (VCC – VB) / I1
R1 = (12 - 2.7)/0.4m = 23.25 k R1 = 33 k (standard)
Also R2 = VB / (I1 – IB)
R2 = 2.7/0.36m =7.5 k R2 = 8.2 k (standard)
To find CC1 , CC2 and CE :

Let FL = 100Hz (Lower cut-off frequency)

Input coupling capacitor: CC1 = 1 / ( 2**Zin*FL) = 1/( 2**558*100) =2.85 F CC1 = 4.7 F ( standard)
Output coupling capacitor: CC2 = 1 / ( 2**(RC + RL)*Fin) =1/(2**(1k + 10k)*100)= 0.144F
CC2 = 0.1F ( standard)
Design of bypass capacitors: CE
Emitter bypass capacitor CE = 1 / ( 2** re * FL) = 1/(2** 6.25 * 100)=254.6µF

CE =100F ( standard)

PROCEDURE

1. Switch on the Power Supply and check the D.C conditions.

2. Check for the sinusoidal waveform at output. If the output is distorted adjust 1KΩ Potentiometer
to get perfect SINE wave.
3. Measure the period (T) of oscillation and calculate the frequency (fo) of oscillation.
4. Compare the measured frequency with re-computed theoretical value for the component values
connected.

8
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

9
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
TABULATION
CAPACITANCE Theoretical
Inductance µF T fo=1/T Amplitude
[Link].
(L) Henry sec Hz Volts
C1 C2 Ceq
1

2
3

Model graph

CRYSTAL OSCILLATOR

Aim: Design and set-up the crystal oscillator and determine the frequency of oscillation.
Components and equipments required:
Transistor SL 100,
Crystal – 2MHz,
Resistors 470Ω, 1KΩ 10KΩ and 33 KΩ;
Capacitors 0.1µf - 2nos,
Power supply, CRO, Connecting wires
Theory: Crystal oscillators are used in order to get stable sinusoidal signals despite of variations in temperature,
humidity, transistor and circuit parameters. A piezo electric crystal is used in this oscillator as resonant tank
circuit. Crystal works under the principal of piezo-electric effect. i.e., when an AC signal applied across the crystal,
it vibrates at the frequency of the applied voltage. Conversely if the crystal is forced to vibrate it will generate
an AC signal. Commonly used crystals are Quartz, Rochelle salt etc.

(Design of amplifier using BJT is same as Colpitt’s oscillator excluding feedback circuit)

PROCEDURE
1. Switch on the Power Supply and check the D.C conditions.
2. Check for the sinusoidal waveform at output. If the output is distorted adjust 1KΩ Potentiometer
to get perfect SINE wave.
3. Measure the period (T) of oscillation and calculate the frequency (fo) of oscillation.
4. Compare the measured frequency with re-computed theoretical value for the component values
connected.

10
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

CIRCUIT DIAGRAM : Crystal Oscillator

11
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

EXPERIMENT: 03:
Design Adder, Integrator, Differentiator and comparator circuits using Op-Amp

PIN DIGRAM of OPAMP:

Aim: i) Design an adder circuit using opamp and verify

i) Design a differentiator circuit using opamp and verify
ii) Design an integrator circuit using opamp and verify
iii) Design an comparator circuit using opamp and verify

Components Rquired:
1. IC 741
2. Resistors as per design
3. Function generator
4. Regulated power supply
5. IC bread board trainer
6. CRO / Patch cards / CRO probes

THEORY:

ADDER: Op-amp can be used to design a circuit whose output is the sum of several input signals. Such a
circuit is called a summing amplifier or an adder. Summing amplifier can be classified as inverting & non-
inverting summer depending on the input applied to inverting & non-inverting terminals respectively. Circuit
Diagram shows an inverting summing amplifier with 2 inputs. Here the output will be amplified version of the
sum of the two input voltages with 1800 phase reversal.
Differentiator: It is an opamp circuit which performs the mathematical operation of differentiation. That is
the output waveform is the derivative or differentia l of the input voltage. That is Vo= - RfC d(Vin)/dt. The
differentiator circuit is constructed from basic inverting amplifier by replacing the input resistance Ri with
capacitor C. This circuit also works as high pass filter.
Integrator: It is a closed loop op-amp circuit which performs the mathematical operation of integration. That
is the output waveform is the integral of the input voltage and is given by Vo = ( -1/RfC) ∫ Vindt. The integrator
circuit is constructed from basic inverting amplifier by replacing the feedback resistance Rf with capacitor C.
This circuit also works as low pass filter.
Comparator: A voltage comparator is a two-input circuit that compares the voltage at one input to the voltage
at the other input. Usually one input is a reference voltage and the other input a time varying signal. If the time
varying input is below or above the reference voltage, then the comparator provides a low or high output
accordingly (usually the plus or minus power supply voltages, since the op-amp is used in the open loop
configuration, a small difference ( − ) makes the output to saturate).

12
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
Design an adder circuit using opamp and verify

Design: Vo = - if R1 = R2 = RF = R

Vo = - (V1+V2 ) ≡ output voltage is proportional to the algebraic sum of the input voltages, V1, V2

CIRCUIT DIGRAM: ADDER

PROCEDURE

Summing/Adder Amplifier:
1. Connections are made as per the circuit diagram.
2. Input DC voltages V1 and V2 are given and the corresponding output voltage Vo is measured
from Multi-meter or CRO.
3. Output varies as Vo = - (V1 + V2), since RF = R.

TABULATION
R1 R2 RF V1 V2 Vo (practical)
[Link] Vo = - volts
Ω Ω Ω volts volts volts
1 1K 1K 1K 1 2

2 1K 3.3K 2.2K 1 2

Differentiator Integrator

Vout = - Rf C {dVin / dt}

The output Vout is Rf C times the differentiation of The output Vout is CRin times the integration of the input
the input voltage. voltage Vin.
The product Rf C is called as the RC time constant The product CRin is called as the RC time constant

Design: Design:

Given f = 1 KHz, sothat, T = 1/f = 1ms Given f =1 KHz So T = 1/f = 1ms

Design equation is T = 2πRfC Design equation is T = 2πRiC
Let C = 0.01µF Let C = 0.01µF
Then, Rf = 15KΩ Then Ri = 10KΩ Take Rf = 10Ri = 100KΩ
Let Ri = Rf/10 = 1.5KΩ

13
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
EX: Given Vp = 1 V and f = 1K Hz, CIRCIUT DIAGRAM
input voltage is Vi = Vp sin ωt
We know ω = 2πf
Hence Vo = - Rf C (dVi /dt ) = - 0.94 cosωt

CIRCIUT DIAGRAM

Tabulation

Type of circuit Input Square wave Output Wave

Amplitude Time period Amplitude Time period
Differentiator
Integrator

Expected Waveforms (Differentiator) (Integrator)

PROCEDURE

Differentiator/ Integrator:

1. Connections are made as per the circuit diagram.

2. A square wave/ triangle wave of 4V (p-p) and frequency of 1KHZ from function generator is
applied to the inverting terminal (2) as input.
3. Using both channels of CRO, observe and record the corresponding amplitude and time period
for input/output for the frequencies of 500 Hz and 1kHz.
4. With the above data plot the output graphs with time on X-axis and voltage on Y-axis. Compare
this with the Equations given above.

14
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
COMPARATOR

Circuit diagram

Transfer characteristics

Expected Waveforms

PROCEDURE

1. Set up the circuit as shown in the diagram.

2. Set the input voltage 10 V peak to peak, 1 kHz in function generator, and apply this as input
signal to the circuit. Observe the output waveform in CRO.
3. Obtain the response for different Vr (say, Vr = 0V,±2V). Also, obtain the transfer characteristics.

RESULT: Theoretical and practical output values for adder and input/output waveforms/values of integrator,
differentiator and comparator are observed using opamp.

Viva questions 4. Define slew rate.

5. What are the applications of differentiator?
1. What are the ideal characteristics of an OP-AMP? 6. What are the applications of integrator?
2. Define OP-AMP. 7. What is a difference between inverting and non-
3. What do you mean by CMRR? inverting amplifier?

15
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

EXPERIMENT: 04
4-Bit R-2R Digital to Analog Converter

(i) Using 4 bit binary input from toggle switches

Aim : To design 4 bit R-2R ladder DAC using Op-Amp for an output & reference voltage of 5 V.

Apparatus :
1. IC μA741
2. Resistors As per design
3. Multimeter -
4. Base board + connecting wires -

Theory:
What is DAC? Digital to analog converter (DAC) is used to get analog voltage corresponding to an input digital
data. Data in binary digital form can be converted to corresponding analog form by using a R-2R ladder (binary
weighted resistor) network and a summing amplifier. It is more common and practical. Below is the circuit and
output simulated waveform of R-2R ladder network DAC. This circuit also uses an op amp (741) summing
amplifier circuit.
The resolution of the converter will be equal to the value of the least significant bit (LSB) which is given as:

Then the smallest step change of the analogue output voltage, V OUT for a 1-bit LSB change of the digital input
of this 4-bit R-2R digital-to-analogue converter example is: 0.3125 volts. That is the output voltage changes in
steps or increments of 0.3125 volts and not as a straight linear value.

DESIGN

To design a 4 bit R-2R DAC for an output voltage, Vo = 5V, let Ri = input equivalent resistance of the ladder
network, RF = feedback resistance.
From the circuit diagram, Iout = I0+I1+I2+I3 (using KCL), then finding each current terms from Ohm’s law

16
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

R= input equivalent resistance

Therefore, above equation becomes,

If Ω

For example, (1010)2 =(10)10 is applied from toggle switches then,

D3 = 1 (MSB), D2 = 0, D1 = 1, D0 = 0 (LSB) and Vref =5V, Vout = -3.125V

CIRCUIT DIAGRAM

PROCEDURE

1. Connections are made as shown in the circuit diagram.

2. Digital input data is given at D3, D2, D1, D0 and corresponding analog output voltage V0 is
measured using millimeter.
3. Compare practical and theoretical values of analog output voltage corresponding to binary input
combination and find the error value.
3. Tabulate the readings & plot the graph between Vo on y-axis Vin on X-axis.

NOTE :

1. D0, D1, D2 & D3 are binary inputs (digital) applied from toggle switches.
2. Vo is the analog output.
3. Binary inputs Do, D1, D2 & D3 can take either the value ‘0’ or ‘1’ (Logic 0 → 0 Logic 1 → +5V).
4. Binary input Di (i = 0 to 3) can be made ‘0’ by connecting the i/p to ground. It can be made ‘1’ by
connecting to +5 V.

17
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)
TABULATION

Decimal Binary inputs (switches) Analog Analog Error

Value D3 D2 D1 D0 V(Practical) volts (X) V(Theoretical)volts (Y) X-Y
0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

Ideal 4-bit R-2R DAC Transfer Characteristics

18
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL SYSTEMS DESIGN LAB (BECL305)

(ii) by generating digital inputs using mod-16 counter

Components Required:
1. Resistors (1KΩx4, 2KΩx5)
2. 741 Op Amp
3. 7493 Counter IC
In this circuit the IC 7493 is a counter simply it provides digital binary inputs (0000 to 1111) to OPAMP inputs
D3D2D1D0 and observe & note down the display on CRO screen.

CIRCUIT DIAGRAM

Model Graph

RESULT: 4 bit R-2R DAC is verified using toggle switches and counter IC 7493.
19
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

EXPERIMENT: 05
Design and Implementation of Half/Full Adder and Subtractor Using Logic Gates /
Universal Gates

AIM: To design and verify

i. Half adder and Full adder
ii. Half subtractor and Full subtractor using basic and NAND gates.

COMPONENTS REQUIRED:

IC 7400,
IC 7408,
IC 7486, and
IC 7432,
Patch cards and IC Trainer Kit

THEORY:

Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called a half-
adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the carry bit, C. The
Boolean functions describing the half-adder are:
S =A ⊕ B C=AB
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit from
its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a
carry-in bit, Cin, is called a full-adder. The Boolean functions describing the full-adder are:S
= (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A –B) produces a difference bit D
and a borrow out bit B-out. This operation is called half subtraction and the circuit to realize it is called a half
subtractor. The Boolean functions describing the half Subtractor are:
D =A ⊕ B Br = A’ B

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a difference
bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing the full-subtracter
are: D = (x ⊕ y) ⊕ Cin Br = A’B + A’ (Cin) + B (Cin)

HALF ADDER USING BASIC GATES TRUTH TABLE

Inputs Outputs
A B Sum(S) Carry©

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

20
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
HALF ADDER USING ONLY NAND GATES

FULL ADDER CIRCUIT USING BASIC GATES

TRUTH TABLE

Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

21
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
HALF SUBTRACTOR USING BASIC GATES TRUTH TABLE

Inputs Outputs
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

PROCEDURE
1. Verify the all gates according to respective truth tables.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to the truth table.
4. Note down the output readings for half and full adder sum and the carry bit for different
combinations of inputs.

RESULT: Half adder, Full adder, Half subtractor and Full subtractor using basic/NAND gates are
verified.

4 VARIABLE FUNCTION USING IC 74151

AIM: To Realize the 4 variable function using IC 74151 (8:1 Multiplexer).

COMPONENTS REQUIRED:

Digital Trainer Kit

NOT Gate IC 7404
8x1 MUX IC 74151
Patch chords / Connecting wires

THEORY
The TTL/MSI SN54/74LS151 is a high speed 8:1 digital multiplexer. It provides, in one DIP package, the
ability to select one bit of data from 8 data inputs. The LS151 can be used as a universal function generator to
generate any logic function of 4 variables.
Basic multiplexer has several data inputs and a single output line. The selection of a particular input line
is controlled by a set of selection line. There are 2n input lines & n is the number of selection line whosebit
combinations determines which input is selected.
Example: S2 S1 S0 = 010 code which corresponds to D2 input data line. Now apply D2 =0/1, this data 0/1 is
transmitted to Y.
The given function is in terms of min-terms and is to be implemented using a 8:1 MUX. An 8:1 MUX has
three select lines, whereas the given function is a 4 variable function. Hence, a logic is needed to give
combination of A as inputs while only B, C and D as select line inputs. The method for the same is described
below.

22
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

Design Example: To implement the following function: F(A,B,C,D) = Σ (0,1,3,4,8,9,15).

Step-1: Using K-map Boolean terms are determined for the variable A as shown below.

Step-2: Construct digital circuit for the given 4 variable function F(A,B,C,D) = Σ (0,1,3,4,8,9,15), such that a logic
is needed to give combination of A as inputs (1, 1, 0, Ā, Ā, 0, 0, A) while only B, C and D as select line inputs.

Fig.(a) Basic pin Description of IC 74151 Fig. (b) IC74151 designed for F(A,B,C,D) = Σ (0,1,3,4,8,9,15)

Step-3: Connect the circuit as shown in the fig. (b) and verify the following truth table.

23
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
A B C D Enable Decimal Y = F(A,B,C,D)
0 0 0 0 0 0 1
0 0 0 1 0 1 1
0 0 1 0 0 2 0
0 0 1 1 0 3 1
0 1 0 0 0 4 1
0 1 0 1 0 5 0
0 1 1 0 0 6 0
0 1 1 1 0 7 0
1 0 0 0 0 8 1
1 0 0 1 0 9 1
1 0 1 0 0 10 0
1 0 1 1 0 11 0
1 1 0 0 0 12 0
1 1 0 1 0 13 0
1 1 1 0 0 14 0
1 1 1 1 0 15 1

Result: 4 variable function F(A,B,C,D) = Σ (0,1,3,4,8,9,15) using IC 74151 (8:1 Multiplexer) is realized.

24
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

EXPERIMENT: 06
Binary to Gray code conversion & vice versa (IC 74139)

Aim: To realize binary to gray code conversion and vice versa using IC74139 (2-4 Decoder).
COMPONENTS REQUIRED:

Digital Trainer Kit

NOT Gate IC 7404
DeMux IC 74139
NAND Gage (4 inputs) IC 7420
Patch chords / Connecting wires

THEORY:
The logical circuit which converts binary code to equivalent gray code is known as binary to gray codeconverter.
The gray code is a non-weighted code. The successive gray code differs in one bit position only that means it is a
unit distance code. It is also referred as cyclic code. It is not suitable for arithmetic operations. It is the most
popular of the unit distance codes. It is also a reflective code. An n-bit Gray code can be obtained by reflecting
an n-1 bit code about an axis after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1 below the
axis.
Binary to gray code conversion
Following steps are required in this conversion:
(1) The MSB of the gray code is equal to MSB of binary number.
(2) Second bit of the gray code will be exclusive-or of the first and second bit of the given binary number.
(3) The third bit of gray code will be equal to the exclusive -or of the second and third bit of the given binary
number.
Thus the Binary to gray code conversion goes on.
One example given below can make your idea clear on this type of conversion.

PIN DIAGRAMS

25
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
Truth Table: Binary to Gray conversion
Binary Gray Conversion
Decimal (Input) (Output) operation Min-terms
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0 0
G0 = Σ (1,2,5,6)
1 0 0 1 0 0 1 G2 = B2
2 0 1 0 0 1 1
3 0 1 1 0 1 0
G1 = Σ (2,3,4,5)
4 1 0 0 1 1 0
5 1 0 1 1 1 1
6 1 1 0 1 0 1
G2 = Σ (4,5,6,7)
7 1 1 1 1 0 0

CIRCUIT DIAGRAM

Gray code to binary conversion

Following steps are required in this conversion:
1) The MSB of the binary number will be equal to the MSB of the given gray code.
2) Start with MSB of Binary number and EXOR it to the second bit of gray number to get next bit of binary.
3) This step is continued for all the bits to do Gray code to binary conversion.

One example given below can make your idea clear on this type of conversion

ECE,SKSVMACET 26
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

Truth Table: Binary to Gray conversion

Gray Binary Conversion
Decimal (Input) (Output) Min-terms
operation
G2 G1 G0 B2 B1 B0

0 0 0 0 0 0 0
B0 = Σ (1,2,4,7)
1 0 0 1 0 0 1

2 0 1 1 0 1 0

3 0 1 0 0 1 1
B1 = Σ (2,3,4,5)
4 1 1 0 1 0 0

5 1 1 1 1 0 1

6 1 0 1 1 1 0
B2 = Σ (4,5,6,7)
7 1 0 0 1 1 1

CIRCUIT DIAGRAM

PROCEDURE

1) Check all the components for their working.

2) Insert the appropriate IC into the IC base.
3) Make connections as shown in the circuit diagram.
4) Verify the Truth Table and observe the outputs.

ECE,SKSVMACET 27
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

CODE CONVERSION

AIM: To realize BCD to Excess-3 code conversion and vise versa using IC 7483

COMPONENTS REQUIRED:

Digital Trainer Kit

EXOR Gate IC 7486
4-bit binary full adder IC 7483
Patch chords / Connecting wires

THEORY

Code converter is a combinational circuit that translates the input code word into a new corresponding word. In
this code each decimal digit is represented by a 4 -bit binary number. BCD is a way to express each of
the decimal digits with a binary code. In the BCD, with four bits we can represent sixteen numbers
(0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The remaining six code
combinations i.e. 1010 to 1111 are invalid in BCD.
To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD code to the 4- bit adder as the first
operand and then feed constant 3 (0011) as the second operand. The output is the corresponding excess-3 code.
To make it work as a excess-3 to BCD converter, we feed excess-3 code as the first operand and then feed 2's
complement of 3 as the second operand. The output is the BCD code.

Excess-3 Code - It is non-weighted code used to express decimal numbers. The Excess -3 code words
are derived from the 8421 BCD code words adding (0011) 2 or (3) 10 to each code word in 8421.

CIRCUIT DIAGRAM: BCD to EXCESS -3 / EXCESS -3 to BCD Conversion

NOTE: Neglect Cout in the circuit

ECE,SKSVMACET 28
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

TRUTH TABLES

PROCEDURE

1) Check all the components for their working.

2) Insert the appropriate IC into the IC base.
3) Make connections as shown in the circuit diagram.
4) Verify the Truth Table and observe the outputs.

RESULT: BCD to Excess-3 code conversion and vise versa using IC 7483 are realized.

ECE,SKSVMACET 29
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

EXPERIMENT: 07
Realize Master Slave JK Flipflop, D-Flipflop & T-Flipflop Using NAND Gates

AIM: To realize Master Slave JK flip-flop, D-flip-flop & T-flip-flop using NAND gates

COMPONENTS REQUIRED:

Digital Trainer Kit

2 input NAND Gates IC 7400
3 input NAND Gates IC 7410
Patch chords / Connecting wires

THEORY
Flip-Flops are binary cells capable of storing one bit of information. A Flip Flop has two outputs, one for the normal
value and one for complement value of the bit stored in it.

JK FLIP-FLOP is basically an SR flip flop with feedback which enables only one of its two input terminals, either
SET or RESET to be active at any one time under normal switching thereby eliminating the invalid condition of
SR flip flop. However, if J = K = 1 and clock input is applied the circuit will “toggle” as its outputs switch and
change state complementing each other. This timing problem called “race”. The master-slave flip- flop eliminates
all the timing problems by using two SR flip-flops connected together in a series configuration. One flip-flop
acts as the “Master” circuit, which triggers on the leading edge of the clock pulse while the other acts as the
“Slave” circuit, which triggers on the falling edge of the clock pulse. This results in the two sections, the master
section and the slave section being enabled during opposite half-cycles of the clock signal.

D FLIP-FLOP: It has only one data input (D) and clock input (CP). The outputs are labeled Q and Q’. The data (0
or 1) at the input 0 is delayed one clock pulse from getting to output Q. SD and CD are active low input (Negative
edge trigger) to set and reset the Flip-Flop i.e. these inputs will be effective when logic 0 is applied. A D Flip-flop
is a bi-stable circuit whose 0 input is transferred to the output after a clock pulse is received.

T FLIP-FLOP This T Flip-Flop is obtained from a JK type if both inputs are tied together. The designation T
shows ability of Flip-Flop to toggle. Regardless of the present state of the Flip-Flop, it assumes the complement
state when the clock pulse occurs while input T is logic1. When T=0, both AND gates are disabled and hence there
is no change in the previous output. When T=1, (J=K=1) output toggles.

CIRCUIT DIAGRAM FOR MASTER SLAVE JK FF

ECE,SKSVMACET 30
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

FUNCTION TABLE

T FLIP-FLOP:
The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is obtained from the JK type if both
inputs are tied together.

CIRCUIT DIAGRAM: Same as Master-Slave JK flip-flop with J = K = 1

Till CLK = 0, the output is in hold state (three input AND gate principle).
When CLK = 1, for T=0, previous output is memorized by the circuit.
When T = 1 along with the clock pulse, the output toggles from the previous value as given in the characteristic
table below.
Truth Table
Clock T Output
Q Ǭ
0 →1 0 Q Ǭ
0 →1 1 Ǭ Q
1 →0 X Q Ǭ

D FLIP-FLOP

D flip-flop is a controlled Bi-stable latch where the clock signal is the control signal. when D = 1 and CLOCK =
HIGH, Output : Q = 1, Ǭ = 0. Working is correct.

CIRCUIT DIAGRAM

Truth Table
Clock D Output
Q Ǭ
0 →1 0 0 1
0 →1 1 1 0
1 →0 X Q Ǭ

ECE,SKSVMACET 31
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

PROCEDURE

1) Turn on power to the circuit.

2) For each input combination, note the logic state of the normal (Q) and complementary (Ǭ) outputs
as indicated by the LEDs (ON = 1; OFF = 0), and record the results in a table.
3) Compare your results with the truth tables.

RESULT: Master Slave JK flip-flop, D-flip-flop & T-flip-flop using NAND gates are verified.

SHIFT REGISTERS

AIM: To realize different types of shift registers Serial In Serial Out [SISO], Serial In Parallel Out [SIPO],
Parallel In Parallel Out [PIPO] and Parallel In Serial Out [PISO] using IC 7495 and to verify function
table.

COMPONENTS REQUIRED
Trainer Kit
IC 7495 01
Ic 7404 01
Patch chord 20

THEORY

The binary information (data) in a register can be moved within or into or out of the register upon application
of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations
used in microprocessors. This gives rise to group of registers called shift registers. They are very important in
applications involving the storage and transfer of data in a digital system.
Types of shift registers:
Serial In Serial Out [SISO]:
In this type of register, the output of one flip-flop is connected to the input of the next flip-flop. Output of the
register is obtained from the last flip-flop. Depending on the direction of the input given shifting takes place
in this. Bit by bit loading and shifting takes place with every clock pulse.
Serial In Parallel Out [SIPO]:
This is similar to SISO except that the output is taken from each flip-flop. Thereby the shifted value is shown at
once.
Parallel In Parallel Out [PIPO]:
Upon giving clock pulse, data is loaded in parallel in all flip-flops. Output is taken from each of the flip-flop.
Parallel In Serial Out [PISO]:
Here we use a control input Load/ (Shift) such that if Load/ (Shift) = 1, data is loaded in all flip-flops in parallel
and when the Load/ (Shift) = 0, data is shifted with every clock pulse. Output is obtained from the last flip-flop.

3 Modes of Operation of IC 7495: Parallel, Shift right and Shift Left

Parallel Shift right Shift Left

Mode control = 1 Mode control = 0 Mode control = 1
Clock-2 = HIGH to LOW Clock-1 = HIGH to LOW Clock-2 = HIGH to LOW

ECE,SKSVMACET 32
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

Pin Diagram of IC 7495

PROCEDURE

1. Connections are made as per circuit diagram.

2. Apply the data at serial i/p (pin-1)
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new data
applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register.

ECE,SKSVMACET 33
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

PROCEDURE

1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply 5th clock pulse; the second data ‘d1’ appears at QD.
5. Apply 6th clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD.
Thus the data applied serially at the input comes out serially at QD.

PROCEDURE

1. Connections are made as per circuit diagram.

2. Apply the desired 4-bit data at A, B, C and D.
3. Keeping the mode control =1 apply one clock pulse. The data applied at A, B, C and D will
appear at QA, QB, QC and QD respectively.
4. Now mode control = 0. Apply clock pulses one by one and observe the data coming out serially
at QD.

ECE,SKSVMACET 34
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

PROCEDURE

1. Connections are made as per circuit diagram.

2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control =1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

RESULT: shift registers using IC 7495 for SIPO/SISO, PISO/PIPO are verified.

RING COUNTER

AIM: To realize Ring counter and Johnson counter using IC 7495

COMPONENTS REQUIRED
Trainer Kit
IC 7495
Ic 7404
Patch chord

THEORY

A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the state one while
others are in their zero states. A ring counter is a Shift Register with the output of the last one connected to the
input of the first, that is, in a ring. Typically, a pattern consisting of a single bit is circulated so the state repeats
every n clock cycles if n flip-flops are used. It can be used as a cycle counter of n states.

RING COUNTER:

Function Table

JOHNSON COUNTER
THEORY:
A Johnson counter (or switch tail ring counter, twisted-ring counter) is a modified ring counter, where the
output from the last stage is inverted and fed back as input to the first stage. The register cycles through a
ECE,SKSVMACET 35
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
sequence of bit-patterns, whose length is equal to twice the length of the shift register, continuing indefinitely.
These counters find specialist applications, including those similar to the decade counter, digital-to-analog
conversion, etc. They can be implemented easily using D- or JK-type flip-flops.

JOHNSON COUNTER:
Function Table

PROCEDURE:

1. Make the connections as shown in the respective circuit diagram.

2. Initial condition is set by setting up the circuit as shown in the figure.
3. Apply clock and observe the output after each clock pulse, record the observations and verify that
they match the expected outputs from the truth table.
4. Verify the operation of ring counter/Johnson counter circuit as per the function tables

RESULT: Ring counter and Johnson counter using IC 7495 are verified

ECE,SKSVMACET 36
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

EXPERIMENT: 08
REALIZE: i) Design MOD-N synchronous up counter & down counter using IC 7476 (JK
FF) ii) MOD-N counter using IC 7490/7476 iii) Synchronous counter using IC 74192

MOD-N synchronous up counter & down counter using IC 7476 (JK FF)

AIM: i) Design and study (MOD-7) 3 bit synchronous counter (Up counter & Down counter) using
JKflip flops.

COMPONENTS

IC 74LS76A (-Ve edge triggered Dual J-K Flip-Flops),

IC 7408 (Dual I/P Quad AND gates)
Trainer kit
Patch cards

THEORY

Counters : counters are logical device or registers capable of counting the no. of states or no. of clock pulses
arriving at its clock input where clock is a timing parameter arriving at regular intervals of time, so counters can
be also used to measure time & frequencies. They are made up of flip flops. Where the pulse are counted to be
made of it goes up step by step & the o/p of counter in the flip flop is decoded to read the count to its starting
step after counting n pulse incase of module counters.
Counter are of two types:
1) Asynchronous counter 2) Synchronous counter.
Asynchronous counter commonly called ripple counter, the first flip-flop is clocked by the external clock pulse &
then each successive flip-flop is clocked by the Q or Q’ output of the previous flip-flop. Therefore in an
asynchronous counter the flip-flop’s are not clocked simultaneously.
When counter is clocked such that each flip flop in the counter is triggered external clock at the same time, the
counter is called as synchronous counter. Ex:- Ring counter & Johnson counter
Types of synchronous counter:
1) Up counter 2) Down counter.

Decision for number of flip-flops

Example : If we are designing mod N counter and m number of flip-flops are required then m can be found
out by this equation.
N <= 2m
Here we are designing Mod-7 counter Therefore, N= 7 and number of Flip flops or bits (m) required is, for
m =3, 7<=8, which is TRUE.

3 bit Synchronous up counter:

The up counter counts from 0 to7 (000 - 111) for this MS JK flip flop IC 74LS76 is used, 2 MS J-K flip flops are
available. It is observed that the AND gate inputs are fed by the non-complement outputs of FFA and FFB. The
clock pulse is given at pin 1 & 6 of the 1st IC & pin 1 of 2nd IC, respectively to apply clock to all flip flop at a time.
3 bit Synchronous down counter:
This is used to count from 7 to 0 (111-000) for this also 2 IC’s of 74LS76 are required & hence we use 3 MS JK
flip flops. It is observed that the AND gate inputs are fed by the complement outputs of FF A and FFB. The clock
pulse is given at pin 1 & 6 of the 1st IC & pin 1 of 2nd IC, respectively to apply clock to all flip flop at a time.

ECE,SKSVMACET 37
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

UP COUNTER CIRCUIT DIAGRAM

PROCEDURE
1. Connect the circuit as shown in the diagram.
2. Connect 𝑃𝑅𝐸 ¯¯¯¯¯¯ input to the logic 1 (+5V).
3. Connect 𝐶𝐿𝑅 ¯¯¯¯¯¯ input to the logic 0 (0V) or ground to reset counter.
4. Connect 𝐶𝐿𝑅 ¯¯¯¯¯¯ input to the logic 1.
5. Apply the clock pulse to CLK input.
6. Observe the output and verify the observation table.

ECE,SKSVMACET 38
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

DOWN COUNTER CIRCUIT DIAGRAM

ii) MOD – N COUNTER USING IC 7490

AIM: ii) Realization of (MOD-10) counter using IC7490

THEORY

If N=10, it is said to be a decade counter (MOD-10 counter). Its operation is as follows:

1. The output of MOD-2 is externally connected to the input B which is the clock input of the internal
MOD-5 counter.
2. Hence QA toggles on every falling edge of clock input whereas the output QD,QC,QB of the MOD-5 counter
will increment from 000 to 100 on low going change of QA output.
3. Due to cascading of MOD-2 and MOD-5 counter, the overall configuration becomes a MOD-10.
4. The reset inputs Ro(1), Ro(2) and preset inputs R9(1), R9(2) are connected to ground so as to make
it inactive.
ECE,SKSVMACET 39
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

Mod-10 Counter Circuit

OBSERVATION TABLE

iii) SYNCHRONOUS COUNTER USING IC 74192

AIM: iii) Realization of synchronous counter using IC74192

THEORY:

A 74192 IC is a pre-settable synchronous 4-bit Up/Down decimal counter, capable of reset to zero, preloading
with a specified value, as well as generating carry and borrow signals that allow one to construct multi-digit
counters. The result of the synchronization is that all the individual output bits of each FF changing state at
exactly the same time in response to the common clock signal with no ripple effect and therefore, no
propagation delay.

ECE,SKSVMACET 40
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
PROCEDURE

1. Check all the components for their working.

2. Make connections as shown in the circuit diagram.
3. Clock pulses are applied one by one at the clock input and output is observed at QA, QB, QC & QD
4. Verify the Truth Table from the outputs.

CIRCUIT DIAGRAM: COUNT UP FROM 3 TO 8

OBSERVATION TABLE PIN DIAGRAM

RESULT: The functioning of MOD-7using JK FF, MOD-10 using IC 7490 & Synchronous counter
using IC74192 are verified.

ECE,SKSVMACET 41
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

EXPERIMENT: 09

Design active second order Butterworth low pass and high pass filters
AIM: Design a second order active Butterworth low pass filter having upper cut off frequency 1 KHz, also determine
its frequency response using IC 741.

APPARATUS REQUIRED:
1. OP-AMP IC741
2. Resistor 10KΩ, 1.6KΩ (2nos), 5.6 KΩ
3. Capacitor 0.1 µF (2nos)
4. CRO, RPS DUAL (0-30) V, bread board , connecting wires,…

THEORY: A filter is a frequency selective circuit that allows only a certain band of frequency component of an input
signal to pass through and blocks other frequency components. An active filter network is obtained by interconnecting
passive elements and active element. Op-amps are used in active filters to provide amplification and gain control. A
low pass filter allows only low frequency signals and suppresses high frequency signals. The range of frequency
varies from dc to cut off frequency fL. The frequency range below cut off frequency is called pass band and frequency
range beyond fL is called stop band. A high pass filter allows only high frequency signals and suppresses low
frequency signals. The range of frequency beyond cut off frequency fH is called pass band and range of frequency
from dc to fH is called stop band.
Butterworth filter is the best compromise between attenuation and phase response. It has no ripple in the pass band
or the stop band, and because of this is sometimes called a maximally flat filter. The Butterworth filter achieves its
flatness at the expense of a relatively wide transition region from pass band to stop band, with average transient
characteristics.
The Butterworth filter is normalized for a –3 dB response at ωo = 1. The values of the elements of the Butterworth
filter are more practical and less critical than many other filter types.
An improved filter response can be obtained by using a second order active filter. A second order filter consists of
two RC pairs and has a roll-off rate of -40 dB/decade. A general second order filter (Sallen Kay filter) is used to
analyze different LP, HP, BP and BS filters.

DESIGN:

Second order active Low Pass filter (see fig.1)

1) Choose high cut-off frequency fH, say 1KHz
2) The design can be simplified by selecting R2 = R3 = R and C2 = C3 = C and choose a value of C = 0.1μF. 3) Calculate the
value of R from the equation, FH = 1/ (2πRC)
R = 1.6 KΩ
4) To guarantee Butterworth response gain must be equal to 1.586.
For n = 2, α (damping factor) = 1.414,
Passband gain = AF = 3 - α =3 – 1.414 = 1.586.

0.586 Ri = RF
5) Let Ri = 10K Ω, then RF = 5.8KΩ
-------------------------------------------------------------------------------------------------------------------------------
42
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Second order active High Pass filter: (see fig.2)

Similarly for HPF select lower cut-off frequency, fL=1KHz and design using the same values of R and C.
[NOTE: i) Decade is a tenfold increase (multiply by 10) or tenfold decrease (divide by 10).
For example, 2 to 20Hz represents one decade.
ii) Octave is a doubling (multiply by 2) or halving (divide by 2) of the frequency scale.
For example, 10 to 20Hz represents one octave, while 2 to 16Hz is three octaves]

PIN DIGRAM of OPAMP:

CIRCUIT DIAGRAM: Second order LPF

Fig.1

CIRCUIT DIAGRAM: Second order HPF

-------------------------------------------------------------------------------------------------------------------------------
43
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Fig.2

EXPECTED WAVEFORM

LOW PASS FILTER HIGH PASS FILTER

Frequency response of 2nd order LPF and HPF

PROCEDURE:

1. The connections are made as shown in the circuit diagram.

2. The input signal 1 V peak-peak (sine wave) is applied to the second order RC filter circuit with the non-
inverting terminal.
3. The supply voltage to OPAMP is switched ON and the o/p voltages are recorded through CRO by
varying different frequencies from 10 Hz to 100 KHz and tabulate the readings for the input/output
amplitudes corresponding to different frequencies.
4. Calculating Gain using the formula and plotting the frequency response characteristics using Semi-log
graph sheet with gain in dB on y-axis and frequency in Hz on x-axis and find out 3dB line for fc.

-------------------------------------------------------------------------------------------------------------------------------
44
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

ii. BAND PASS FILTER

AIM: To design band pass filter for cut-off frequency fH=5 kHz & fL=16 kHz. Assume gain of filter is 1.586.
COMPONENTS REQUIRED:
SL NAME OF DESIGNED USED
NO. COMPONENTS VALUE VALUE QUANTITY
1 Op-amp(IC- 741) 2
2 Resistors(R1, R2) 0.9KΩ 1KΩ 2
Rf 5.8kΩ 5.6kΩ 2
R3 10kΩ 10kΩ 2
3kΩ 3.3kΩ 2
3 Capacitors 0.01µF 0.01µF 4
4 Bread board, power supply, CRO, probes, Connecting wires, etc.

DESIGN CONSIDERATION:
fH=5kHz, fL=16kHz
For HPF, assume C=0.01µF, R3=10kΩ For LPF, assume C=0.01µF, R3=10kΩ
fH=1/2πRC fL=1/2πRC
R=R1=R2=1/2π*fH*C R=R1=R2=1/2π*fL*C
Af=1+Rf/R3 Af=1+Rf/R3

CIRCUIT DIAGRAM:

-------------------------------------------------------------------------------------------------------------------------------
45
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

PROCEDURE:
1. Circuit connections are made as shown in fig.
2. Set the input to 1 Vpp in signal generator, Observe the output.
3. Input frequency varied & output voltage is noted down.
4. The gain in dB is calculated by using formula Af=20log(vo/vi).
5. The graph of gain v/s frequency is plotted on graph sheet.

TABULAR COLUMN:
SL No. Input frequency (in Hz) O/p voltage Vo/Vi Gain

-------------------------------------------------------------------------------------------------------------------------------
46
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

Nature of graph:

Result: The designed circuit for band pass filter is verified for given value of fH and fL frequency.

-------------------------------------------------------------------------------------------------------------------------------
47
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

EXPERIMENT: 10
Design Monostable and Astable Multivibrator Using 555 Timer

MONOSTABLE MULTIVIBRATOR

AIM: To construct and study the operation of a monostable multivibrator using 555IC timer.

APPARATUS:

1. 555 IC timer
2. Capacitors (0.1μF, 0.01μF)
3. Resistors 1KΩ

THEORY
Monostable multivibrator is also known as triangular wave generator. It has one stable and one quasi stable
state. The circuit is useful for generating single output pulse of time duration in response to a triggering signal.
The width of the output pulse depends only on external components connected to the op-amp. Timer IC 555
is also used as one shot or monostable operation. Since there are many real life application wheremany
applications needs to operate for only specific time interval for such application one shot or monostable
operation is suitable. When negative going pulse is applied to pin 2 which leads to output pin 3 goes to high.
The negative edge of the trigger pulse causes the internal comparator 2 trigger the flip flops leads to output
high at pin 3. The voltage across capacitor rises to 2VCC/3 through supply and resistor R1. When the voltage
across capacitor reaches to 2VCC/3 the internal comparator 1 triggers the flip flop from and which send the
output from high to low. Figure shows the waveforms associated with the operation of the IC 555 as a
monostable. The output waveform shows that the wide range from microsecond to many seconds can be
possible with appropriate values of R and C. This flexibility of time period makes IC 555 versatile for many real
life applications. The time period is given by Tp = 1.1 RC.

DESIGN: Waveforms

Output pulse width (T) = Delay time is given by

T = 1.1 R C ……(1)

Let T = 1ms ; C = 0.1µF

R = 10KΩ (std)

Apply input square-wave signal from the signal

generator of f = 1KHz (T = 1ms) and Vpp =5V

-------------------------------------------------------------------------------------------------------------------------------
48
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
MONOSTABLE MULTIVIBRATOR CIRCUIT DIAGRAM

PROCEDURE

1. Connections are made as per the circuit diagram.

2. Setup negative triggering using triggering circuit & it is applied at the terminal 2 of IC 555.
3. Observe the output waveforms and measure the output voltage (VO) and voltage across capacitor
(Vc). Calculate the theoretical values of above measured parameters.
4. Theoretically the time period (T) is calculated by T=1.1R1C1 where R1 =10KΩ C1=0.1μF.
5. Practical and theoretical charging and discharging timers are measured.
6. Plot the wave forms as per the scale.
TABULATION

Parameter Theoretical Practical

T (ms) 1 m sec
t (ms) 6 m sec

RESULT: Monostable multivibrator using timer IC 555 is designed, setup and the waveforms are obtained.

ASTABLE MULTIVIBRATOR

AIM: To construct and study the operation of Astable multivibrator using 555 timer
APPARATUS:
1. IC 555 Timer
2. Resistors as per design
3. Capacitors (0.1μF, 0.01μF)
4. CRO
THEORY: The capacitor charges through resistors RA and RB the voltages across capacitor rises to 2VCC/3. This
voltage acts as a threshold voltage at pin 6 which is input to internal comparator which finally trigger the internal
flip flop so that output pin 3 goes low. Also flip flop drives the internal discharge transistor to ON allowing
capacitor to get discharge from RB this lead to decrease in capacitor voltage to VCC/3 and the flip flopget trigger
and discharge transistors gets off and output set to high. This leads to charging of capacitor through RA and RB
to VCC. A diode D1 is connected between the discharge and threshold terminals (as also across RB). Thus the
capacitor now charges only through RA (since RB is shorted by diode conduction during charging) and
discharges through RB. Another optional diode D2 is also connected in series with RB in reverse direction for

49
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
better shorting of RB.

Design:
The time for charging C from 1/3 to 2/3 Vcc = ON Time = 0.693 (RA + RB) C
The time for discharging C from 2/3 to 1/3 Vcc = OFF Time = 0.693 RB C

fosc = 1/ Tosc = 1.44/(RA + RB)C

Duty Cycle = RA/ (RA + RB)

Min. Duty Cycle = R1/(R1 + RX + R2) Max. Duty Cycle = (R1 + RX)/(R1 + RX + R2)

To vary the duty cycle from about 0 to 100%, a potentiometer, RX, is used. Thus a variable duty cycle is
achieved.

ASTABLE MULTIVIBRATOR CIRCUIT DIGRAM and WAVEFORMS

PROCEDURE

2. Connections are made as per the circuit diagram.

3. Set the DC power supply to provide VCC=5V .
4. Connect output pin (3) of 555 to channel 1 of CRO and pin (2/6) to channel 2 of CRO.
5. Observe the output waveforms and measure the output voltage (VO) and voltage across capacitor
(Vc). Calculate the theoretical values of above measured parameters.
6. Plot the output voltage waveforms for output voltage and voltage across capacitor.
Frequency, f= 1.45/ (RA+2RB)C and % of Duty cycle = (TH/ (TH+TL))*100
7. Practically TL and TH are measured and theoretical values are verified with practical values.

TABULATION

TH (ms) TL (ms) T (ms) F (Hz) Duty

Theoretical Practical Theoretical Practical Theoretical Practical Theoretical Practical Cycle
60%
50%
40%
RESULT: Astable multivibrator using timer IC 555 is designed, setup and the waveforms are obtained.

50
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
EXPERIMENT NO: 11

Design and simulation of Regulated power supply

AIM: Conduct experiment to design and simulation of regulated power supply.

COMPONENTS REQUIRED:

1) Regulator- LM7805C
2) Diode- 1N4500
3) Capacitor-470pF
-0.1pF
4) Variable power supply - (0-30v)
5) Voltmeter (0-30v)
THEORY:
Regulator: A voltage regulator provides a constant dc output voltage that is essentially independent of the input voltage,
output load current, and temperature. The voltage regulator is one part of a power supply. Its input voltage comes from the
filtered output of a rectifier derived from an ac voltage.

Although many types of IC regulators are available, the 78XX series of IC regulators is representative of three-terminal devices
that provide a fixed positive output voltage. The three terminals are input, output, and ground as indicated in the standard
fixed voltage configuration in Figure. The last two digits in the part number designate the output voltage. For example, the
7805 is a +5.0v regulator. The output capacitor acts basically as a line filter to improve transient response. The input capacitor
filters the input and preventsunwanted oscillations when the regulator is some distance from the power supply filter such that
the line has a significant inductance.

Circuit Diagram:

51
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

DESIGN:

PROCEDURE:
1. Rig up the circuit in Multisim as shown in figure.
2. Observe variation of voltage in multimeter
3. Also note down shape of waveform at different part of RPS

Result: Regulated power supply circuit is constructed and its performance is studied.

52
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

IC 74139

Dual 2-to-4 line separate Decoder /

Demultiplexer in DIP-16 Package. The
active-low enable input can be used as
a data line in demultiplexing
applications. Decoder can be used as
Code a converter.

IC 74151

It is an 8: 1 multiplexer which provides

two complementary outputs Y & Ȳ. The
LS151 can be used as a universal
function generator to generate any
logic function of four variables.

IC 74192

The SN54/74LS192 is an UP/DOWN

BCD Decade (8421) Counter and the.
SN54/74LS193 is an UP/DOWN
MODULO-16 Binary Counter. These
chips also have parallel data input
leads that can be used to preset the
counter. Two clock inputs are available;
one for an UP count and the other for
a DOWN count.

53
ECE, SKSVMACET Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)

IC µA 741 (OPAMP)

The 741 Operational Amplifier IC is a

monolithic integrated circuit,
comprising of a general purpose
Operational Amplifier. It was first
manufactured by Fairchild
semiconductors in the year 1963. The
number 741 indicates that this
operational amplifier IC has 7
functional pins, 4 pins capable oftaking
input and 1 output pin.

IC 555 TIMER

It is an integrated circuit used in a

variety of timer, delay, pulse
generation, and oscillator applications.
The 555 Timer IC got its name fromthe
three 5KΩ resistors that are used inits
voltage divider network. It is first
introduced in early 1970.

ECE,SKSVMACET 54
Downloaded by Ananya C (ananyac0413@[Link])
 lOMoARcPSD|43633637

SEMESTER – III (CBCS) and (OBE)

ANALOG AND DIGITAL ELECTRONICS LABORATORY (21ECL35)
PIN CONFIGURATION OF DIGITAL ICs

ECE,SKSVMACET 55
Downloaded by Ananya C (ananyac0413@[Link])