HCMS-29xx Series

High Performance CMOS 5×7 Alphanumeric Displays

Data Sheet

Description Features
The HCMS-29xx series are high performance, easy • Easy to use
to use dot matrix displays driven by on-board CMOS • Interfaces directly with microprocessors
ICs. Each display can be directly inter­ faced with a
• 0.15” character height in 4, 8, and 16 (2×8) character
microproces­sor, thus eliminat­ing the need for cum­ber­ packages
some interface compo­nents. The serial IC interface al-
lows higher char­ac­ter count information displays with a • 0.20” character height in 4 and 8 character packages
minimum of data lines. A variety of colors, font heights, • Rugged X- and Y-stackable package
and character counts gives designers a wide range of • Serial input
prod­uct choices for their specific appli­cations and the • Convenient brightness controls
easy to read 5×7 pixel format allows the display of up-
percase, lower case, Kata­kana, and custom user-defined • Wave solderable
characters. These dis­plays are stackable in the x- and y- • Offered in five colors
directions, making them ideal for high character count • Low power CMOS technology
displays. • TTL compatible

Applications
• Telecommunications equipment
• Portable data entry devices
• Computer peripherals
• Medical equipment
• Test equipment
• Business machines
• Avionics
• Industrial controls
Device Selection Guide
Package
Description Deep Red HER Orange Yellow Green Drawing
1 × 4 0.15” Character HCMS-2905 HCMS-2902 HCMS-2904 HCMS-2901 HCMS-2903 A
1 × 8 0.15” Character HCMS-2915 HCMS-2912 HCMS-2914 HCMS-2911 HCMS-2913 B
2 × 8 0.15” Character HCMS-2925 HCMS-2922 HCMS-2924 HCMS-2921 HCMS-2923 C
1 × 4 0.20” Character HCMS-2965 HCMS-2962 HCMS-2964 HCMS-2961 HCMS-2963 D
1 × 8 0.20” Character HCMS-2975 HCMS-2972 HCMS-2974 HCMS-2971 HCMS-2973 E

ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO AVOID STATIC DISCHARGE.
HCMS-290x
17.78 (0.700) MAX. PIN FUNCTION
ASSIGNMENT TABLE
4.45 (0.175) TYP. PIN # FUNCTION
1 DATA OUT
2.22 (0.087) SYM. 2 OSC
3 V LED
4 DATA IN
5 RS
12 6 CLK
3.71 (0.146) TYP. 1 2 3 4 10.16 (0.400) MAX. 7 CE
8 BLANK
1 9 GND
10 SEL
11 V LOGIC
2.11 (0.083) TYP. 12 RESET
PIN # 1 IDENTIFIER DATE CODE
LIGHT INTENSITY CATEGORY
0.25
PART NUMBER COLOR BIN (0.010)
COUNTRY OF ORIGIN

5.08 HCMS-290X X Z
(0.200) YYWW COO
4.32 TYP.
0.51 (0.020) (0.170)

PIN # 1 2.54 SYM. 1.27 SYM.

(0.100) (0.050)
2.54 ± 0.13
(0.100 ± 0.005) TYP. 7.62
(NON ACCUM.) (0.300)
0.51 ± 0.13 TYP.
(0.020 ± 0.005)

NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

HCMS-291x
35.56 (1.400) MAX.

2.22 (0.087) SYM.

4.45 TYP.
(0.175)
PIN FUNCTION
ASSIGNMENT TABLE
26
3.71 TYP. 10.16 (0.400) MAX. PIN # FUNCTION
0 1 2 3 4 5 6 7
(0.146) 1 NO PIN
3 2 NO PIN
3 V LED
2.11 (0.083) TYP. 4 NO PIN
5 NO PIN
6 NO PIN
PIN # 1 IDENTIFIER DATE CODE (YEAR, WEEK) 7 GND LED
INTENSITY CATEGORY 8 NO PIN
9 NO PIN
PART NUMBER COLOR BIN 10 V LED
COUNTRY OF ORIGIN 0.25 11 NO PIN
(0.010) 12 NO PIN
13 NO PIN
14 DATA IN
HCMS-291X X Z 15 RS
YYWW COO 5.08 (0.200) 16 NO PIN
0.51 17 CLOCK
(0.020) 4.32 18 CE
(0.170) TYP. 19 BLANK
20 GND LOGIC
2.54 SYM. 21 SEL
(0.100) 22 V LOGIC
0.51 ± 0.13 TYP. 1.27 SYM. 23 NO PIN
(0.020 ± 0.005) (0.050) 24 RESET
2.54 ± 0.13 TYP. 7.62 25 OSC
(0.100 ± 0.005) (0.300) 26 DATA OUT
(NON ACCUM.)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

2
HCMS-292x
PIN FUNCTION ASSIGNMENT TABLE
PIN # FUNCTION PIN # FUNCTION
1A NO PIN 1B NO PIN
2A NO PIN 2B NO PIN
35.56 (1.400) MAX. 3A V LED 3B V LED
4A NO PIN 4B NO PIN
5A NO PIN 5B NO PIN
2.22 (0.088) SYM. 6A NO PIN 6B NO PIN
4.45 (0.175) MAX. 7A GND LED 7B GND LED
8A NO PIN 8B NO PIN
9A NO PIN 9B NO PIN
26B 10A V LED 10B V LED
ROW B 11A NO PIN 11B NO PIN
0 1 2 3 4 5 6 7 12A NO PIN 12B NO PIN
4.83 13A NO PIN
(0.190) 13B NO PIN
3B 19.81 (0.780) MAX. 14A DATA IN 14B DATA IN
9.65 (0.380)
26A 15A RS 15B RS
16A NO PIN 16B NO PIN
8 9 10 11 12 13 14 15 3.71 (0.146) TYP. 17A CLOCK 17B CLOCK
ROW A
3A 18A CE 18B CE
19A BLANK 19B BLANK
20A GND LOGIC 20B GND LOGIC
2.11 (0.083) TYP. 21A SEL 21B SEL
DATE CODE (YEAR, WEEK) 22A V LOGIC 22B V LOGIC
PIN # 1 IDENTIFIER 23A NO PIN 23B NO PIN
INTENSITY CATEGORY 24A RESET 24B RESET
PART NUMBER COLOR BIN 25A OSC 25B OSC
26A DATA OUT 26B DATA OUT
COUNTRY OF ORIGIN

0.25
HCMS-292X X Z (0.010)
YYWW COO 5.08 (0.200)
0.51
(0.020)

2.54 SYM. 1.27

0.51 ± 0.13 TYP. (0.100) (0.050)
(0.020 ± 0.005) 2.03
2.54 ± 0.13 TYP. (0.080)
(0.100 ± 0.005) 7.62
(NON ACCUM.) (0.300)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

HCMS-296x
21.46 (0.845) MAX. PIN FUNCTION
ASSIGNMENT TABLE
2.67 (0.105) SYM. PIN # FUNCTION
2.54 (0.100) TYP. 1 DATA OUT
2 OSC
3 V LED
4 DATA IN
5 RS
4.57 TYP. 0 1 2 3 6 CLK
(0.180) 11.43 (0.450) MAX.
7 CE
8 BLANK
9 GND
10 SEL
11 V LOGIC
5.36 (0.211) TYP. 12 RESET
PIN # 1 IDENTIFIER
DATE CODE (YEAR, WEEK)
PART NUMBER INTENSITY CATEGORY
COLOR BIN 0.25
COUNTRY OF ORIGIN (0.010)

HCMS-296X X Z 5.31
YYWW COO (0.209)

3.71 TYP.
4.28 SYM. 0.50 (0.146)
(0.169) (0.020)

0.51 ± 0.13 TYP.

(0.020 ± 0.005) 1.83 SYM.
2.54 ± 0.13 TYP. (0.072)
(0.100 ± 0.005) 7.62
NOTES: (0.300)
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

3
HCMS-297x
42.93 (1.690) MAX.
2.67 (0.105) SYM.
5.36 (0.211) TYP.
PIN FUNCTION
26
ASSIGNMENT TABLE
4.57 TYP. 1 2 3 4 5 6 7 8 PIN # FUNCTION
(0.180) 11.43 (0.450) MAX.
1 NO PIN
3 2 NO PIN
3 V LED
4 NO PIN
5 NO PIN
2.54 (0.100) TYP. 6 NO PIN
PIN # 1 IDENTIFIER 7 GND LED
8 NO PIN
DATE CODE (YEAR, WEEK) 9 NO PIN
INTENSITY CATEGORY 10 V LED
COLOR BIN 0.25
PART NUMBER (0.010) 11 NO PIN
COUNTRY OF ORIGIN 12 NO PIN
13 NO PIN
14 DATA IN
HCMS-297X X Z 5.31 15 RS
YYWW COO (0.209) 16 NO PIN
0.51
(0.020) 17 CLOCK
3.71 TYP. 18 CE
(0.146) 19 BLANK
6.22 SYM. 20 GND LOGIC
0.51 ± 0.13 TYP. (0.245) 21 SEL
(0.020 ± 0.005) 22 V LOGIC
1.90 SYM. 23 NO PIN
2.54 ± 0.13 TYP.
(0.100 ± 0.005) (0.075) 24 RESET
(NON ACCUM.) 7.62 25 OSC
(0.300) 26 DATA OUT
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

Absolute Maximum Ratings

Logic Supply Voltage, VLOGIC to GNDLOGIC ‑0.3 V to 7.0 V
LED Supply Voltage, VLED to GNDLED ‑0.3 V to 5.5 V
Input Voltage, Any Pin to GND ‑0.3 V to VLOGIC +0.3 V
Free Air Operating Temperature Range TA [1] ‑40 °C to +85 °C
Relative Humidity (noncondensing) 85%
Storage Temperature, TS ‑55 °C to 100 °C
Soldering Temperature [1.59 mm (0.063 in.) Below Body]
Solder Dipping 260 °C for 5 secs
Wave Soldering 250 °C for 3 secs
ESD Protection @ 1.5 kΩ, 100 pF (each pin) Class 1, 0-1999 V
TOTAL Package Power Dissipation at TA = 25 °C [2]
4 Character 1.2 W
8 Character 2.4 W
16 Character 4.8 W

Note:
1. For operation in high ambient temperatures, see Appendix A, Thermal Considerations.

Recommended Operating Conditions Over Temperature Range (-40 °C to +85 °C)

Parameter Symbol Min. Typ. Max. Units
Logic Supply Voltage VLOGIC 3.0 5.0 5.5 V
LED Supply Voltage VLED 4.0 5.0 5.5 V
GNDLED to GNDLOGIC -0.3 0 +0.3 V

4
Electrical Characteristics Over Operating Temperature Range (-40 °C to +85 °C)
TA = 25 °C -40 °C < TA < 85 °C
VLOGIC = 5.0 V 3.0 V < VLOGIC < 5.5 V
Parameter Symbol Typ. Max. Min. Max. Units Test Conditions
Input Leakage Current II µA VIN = 0 V to VLOGIC
HCMS-290x/296x (4 char) +7.5 -2.5 +50
HCMS-291x/297x (8 char) +15 -5.0 +100
HCMS-292x (16 char) +15 -5.0 +100
ILOGIC OPERATING ILOGIC(OPT) mA VIN = VLOGIC
HCMS-290x/296x (4 char) 0.4 2.5 5
HCMS-291x/297x (8 char) 0.8 5 10
HCMS-292x (16 char) 0.8 5 10
ILOGIC SLEEP [1] ILOGIC(SLP) µA VIN = VLOGIC
HCMS-290x/296x (4 char) 5 15 25
HCMS-291x/297x (8 char) 10 30 50
HCMS-292x (16 char) 10 30 50
ILED BLANK ILED(BL) mA BL = 0 V
HMCS-290x/296x (4 char) 2.0 4 4.0
HCMS-291x/297x (8 char) 4.0 8 8
HCMS-292x (16 char) 4.0 8 8
ILED SLEEP [1] ILED(SLP) µA
HCMS-290x/296x (4 char) 1 3 50
HCMS 291x/297x (8 char) 2 6 100
HCMS-292x (16 char) 2 6 100
Peak Pixel Current [2] IPIXEL VLED = 5.5 V
HCMS-29x5 (Deep Red) 15.4 17.1 18.7 mA All pixels ON,
HCMS-29xx (Other Colors) 14.0 15.9 17.1 mA Average value per pixel
HIGH Level Input Voltage Vih 2.0 V 4.5 V < VLOGIC < 5.5 V
0.8 VLOGIC V 3.0 V < VLOGIC < 4.5 V
LOW Level Input Voltage Vil 0.8 V 4.5 V < VLOGIC < 5.5 V
0.2 VLOGIC V 3.0 V < VLOGIC < 4.5 V
HIGH Level Output Voltage Voh 2.0 V VLOGIC = 4.5 V,
Ioh = -40 µA
0.8 VLOGIC V 3.0 V < VLOGIC < 4.5 V
LOW Level Output Voltage Vol 0.4 V VLOGIC = 5.5 V,
Iol = 1.6 mA [3]
0.2 VLOGIC V 3.0 V < VLOGIC < 4.5 V
Thermal Resistance RqJ-P 70 °C/W IC junction to pin

Notes:
1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off.
2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed this value.
3. For the Oscillator Output, Iol = 40 µA.

5
Optical Characteristics at 25 °C[1]
VLED = 5.0 V, 50% Peak Current, 100% Pulse Width
       Peak Dominant
      Luminous Intensity per LED [2] Wavelength Wavelength
      Character Average (µcd) lPeak (nm) ld [3] (nm)
Display Color Part Number Min. Typ. Typ. Typ.
Deep Red HCMS-29x5 95 770 645 637
High Efficiency Red HCMS-29x2 64 270 635 626
Orange HCMS-29x4 64 180 600 602
Yellow HCMS-29x1 64 180 583 585
Green HCMS-29x3 64 270 568 574

Notes:
1. Refers to the initial case temperature of the device immediately before measurement.
2. Measured with all LEDs illuminated.
3. Dominant wavelength, ld, is derived from the CIE chromaticity diagram and represents the single wavelength, which defines the perceived
LED color.

Electrical Description
Pin Function Description
RESET (RST) Sets Control Register bits to logic low. The Dot Register contents are unaffected by the Reset pin.
(logic low = reset; logic high = normal operation).
DATA IN (DIN) Serial Data input for Dot or Control Register data. Data is entered on the rising edge of the Clock
input.
DATA OUT (DOUT ) Serial Data output for Dot or Control Register data. This pin is used for cascading multiple dis-
plays.
CLOCK (CLK) Clock input for writing Dot or Control Register data. When Chip Enable is logic low, data is en-
tered on the rising Clock edge.
REGISTER SELECT (RS) Selects Dot Register (RS = logic low) or Control Register (RS = logic high) as the destination for
serial data entry. The logic level of RS is latched on the falling edge of the Chip Enable input.
CHIP ENABLE (CE) This input must be a logic low to write data to the display. When CE returns to logic high and CLK
is logic low, data is latched to either the LED output drivers or a Control Register.
OSCILLATOR SELECT (SEL) Selects either an internal or external display oscillator source. (logic low = External Display Oscil-
lator; logic high = Internal Display Oscillator).
OSCILLATOR (OSC) Output for the Internal Display Oscillator (SEL = logic high) or input for an External Display Oscil-
lator (SEL = logic low).
BLANK (BL) Blanks the display when logic high. May be modulated for brightness control.
GNDLED Ground for LED drivers.
GNDLOGIC Ground for logic.
VLED Positive supply for LED drivers.
VLOGIC Positive supply for logic.

6
AC Timing Characteristics Over Temperature Range (-40 °C to +85 °C)
Timing
Diagram Ref. 4.5 V < VLOGIC <5.5 V VLOGIC = 3 V
Number Description  Symbol Min. Max. Min. Max. Units
1 Register Select Setup Time to Chip Enable   trss 10 10 ns
2 Register Select Hold Time to Chip Enable   trsh 10 10 ns
3 Rising Clock Edge to Falling   tclkce 20 20 ns
Chip Enable Edge
4 Chip Enable Setup Time to Rising Clock Edge   tces 35 55 ns
5 Chip Enable Hold Time to Rising Clock Edge   tceh 20 20 ns
6 Data Setup Time to Rising Clock Edge   tds 10 10 ns
7 Data Hold Time after Rising Clock Edge   tdh 10 10 ns
8 Rising Clock Edge to DOUT [1]  tdout 10 40 10 65 ns
9 Propagation Delay DIN to DOUT   tdoutp 18 30 ns
Simultaneous Mode for One IC [1,2]
10 CE Falling Edge to DOUT Valid   tcedo 25 45 ns
11 Clock High Time   tclkh 80 100 ns
12 Clock Low Time   tclkl 80 100 ns
Reset Low Time   trstl 50 50 ns
Clock Frequency   Fcyc 5 4 MHz
Internal Display Oscillator Frequency   Finosc 80 210 80 210 kHz
Internal Refresh Frequency   Frf 150 410 150 400 Hz
External Display Oscillator Frequency   Fexosc
  Prescaler = 1 51.2 1000 51.2 1000 kHz
  Prescaler = 8 410 8000 410 8000 kHz

Notes:
1. Timing specifications increase 0.3 ns per pF of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.

7
Display Overview Dot Register
The HCMS‑29xx series is a family of LED displays driven The Dot Register holds the pattern to be displayed by
by on‑board CMOS ICs. The LEDs are configured as 5 x 7 the LEDs. Data is loaded into the Dot Register according
font characters and are driven in groups of 4 characters to the procedure shown in Table 1 and the Write Cycle
per IC. Each IC consists of a 160‑bit shift register (the Dot Timing Diagram.
Register), two 7‑bit Control Words, and refresh circuitry.
First RS is brought low, then CE is brought low. Next,
The Dot Regis­ter contents are mapped on a one‑to‑one
each successive rising CLK edge will shift in the data
basis to the display. Thus, an individual Dot Register bit
at the DIN pin. Loading a logic high will turn the cor-
uniquely controls a single LED.
responding LED on; a logic low turns the LED off. When
8‑character displays have two ICs that are cascaded. The all 160 bits have been loaded (or 320 bits in an 8‑digit
Data Out line of the first IC is internally connected to display), CE is brought to logic high.
the Data In line of the second IC forming a 320‑bit Dot
When CLK is next brought to logic low, new data is
Register. The dis­play’s other control and power lines are
latched into the display dot drivers. Loading data into
connected directly to both ICs. In 16‑character displays,
the Dot Register takes place while the previous data is
each row functions as an independent 8‑character dis-
displayed and eliminates the need to blank the display
play with its own 320‑bit Dot Register.
while loading data.
Reset Pixel Map
Reset initializes the Control Registers (sets all Control
In a 4‑character display, the 160‑bits are arranged as 20
Register bits to logic low) and places the display in the
columns by 8 rows. This array can be conceptualized as
sleep mode. The Reset pin should be con­nected to the
four 5 x 8 dot matrix character loca­tions, but only 7 of
system power‑on reset circuit. The Dot Registers are not
the 8 rows have LEDs (see Figures 1 & 2). The bottom
cleared upon power‑on or by Reset. After power‑on, the
row (row 0) is not used. Thus, latch location 0 is never
Dot Register contents are random; however, Reset will
displayed. Column 0 controls the left‑most column.
put the display in sleep mode, there­by blanking the
Data from Dot Latch locations 0‑7 determine whether
LEDs. The Control Register and the Control Words are
or not pixels in Column 0 are turned‑on or turned‑off.
cleared to all zeros by Reset.
Therefore, the lower left pixel is turned‑on when a logic
To operate the display after being Reset, load the Dot high is stored in Dot Latch location 1. Characters are
Register with logic lows. Then load Control Word 0 with loaded in serially, with the left‑most character being
the desired bright­ness level and set the sleep mode bit loaded first and the right‑most character being loaded
to logic high. last. By loading one character at a time and latching the
data before loading the next character, the figures will
appear to scroll from right to left.

Table 1. Register Truth Table

Function CLK CE RS
Select Dot Register Not Rising ↑↓ L
Load Dot Register
  DIN = HIGH LED = “ON” ↑ ↓ L X
  DIN = LOW LED = “OFF”
Copy Data from Dot Register to Dot Latch L H X
Select Control Register Not Rising ↑↓ H
Load Control Register [1,3]
↑↓ L X
Latch Data to Control Word [2] L X
↑↓

Notes:
1. BIT D0 of Control Word 1 must have been previously set to Low for serial mode or High for simultaneous mode.
2. Selection of Control Word 1 or Control Word 0 is set by D7 of the Control Shift Register. The unselected control
word retains its previous value.
3. Control Word data is loaded Most Significant Bit (D7) first.

8
HCMS-29xx Write Cycle Diagram
RS
TRSS TRSH
1 2

CE

T CLKCE T CES TCLKH TCLKL TCEH

3 4 11 12 5

CLK

TDS TDH NEW DATA LATCHED HERE [1]

6 7
DIN
T CEDO TDOUT
10 8

D OUT (SERIAL)
TDOUTP
9
D OUT
(SIMULTANEOUS)

LED OUTPUTS,
CONTROL PREVIOUS DATA NEW DATA
REGISTERS

NOTE:
1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.

Control Register Control Word 0

The Control Register allows software modification of the Loading the Control Register with D7 = Logic low se-
IC’s opera­tion and consists of two independent 7‑bit lects Control Word 0 (see Table 2). Bits D0‑D3 adjust the
control words. Bit D7 in the shift register selects one of display brightness by pulse width modulating the LED
the two 7‑bit control words. Control Word 0 performs on-time, while Bits D4‑D5 adjust the display brightness
pulse width modula­tion brightness control, peak pixel by changing the peak pixel current. Bit D6 selects normal
current brightness control, and sleep mode. Control operation or sleep mode.
Word 1 sets serial/simultaneous data out mode, and
external oscilla­tor prescaler. Each function is indepen- Sleep mode (Control Word 0, bit D6 = Low) turns off the
dent of the others. Internal Display Oscillator and the LED pixel drivers. This
mode is used when the IC needs to be powered up, but
does not need to be active. Current draw in sleep mode
Control Register Data Loading is nearly zero. Data in the Dot Register and Control Words
Data is loaded into the Control Register, MSB first, ac- are retained during sleep mode.
cording to the proce­dure shown in Table 1 and the
Write Cycle Timing Diagram. First, RS is brought to logic
high and then CE is brought to logic low. Next, each
successive rising CLK edge will shift in the data on the
DIN pin. Finally, when 8 bits have been loaded, the CE
line is brought to logic high. When CLK goes to logic
low, new data is copied into the selected control word.
Loading data into the Control Register takes place while
the previous control word configures the display.

9
 DATA OUT
RS (LATCHED)
H L
DATA IN
L
CLK
H
H L
SER/PAR
CHIP MODE DI DI DI DI DOT
ENABLE 40 BIT 40 BIT 40 BIT 40 BIT REGISTERS
DATA IN CONTROL DATA S.R. S.R. S.R. S.R. AND
REGISTER CLR REGISTER OUT DO DO DO DO LATCHES
D Q
SELECT RS
(LATCHED) V LED +

REFRESH CURRENT
CONTROL REFERENCE ANODE CURRENT SOURCES
RESET RST
PWM BRIGHTNESS DOT
PRESCALE CONTROL REGISTER
VALUE BIT # 159
ROW 7

FIELD DRIVERS
3:8 DECODER

CATHODE
H
÷8
OSC ROW 1
L
0xxxx xxxxx xxxxx x x x x x ROW 0 (NO LEDS)
H OSCILLATOR L
COLUMN 0 COLUMN 19
L H CHAR 0 CHAR 1 CHAR 2 CHAR 3
OSC
SELECT
GND (LED)

BLANK

Figure 1.

DATA FROM
PIXEL PREVIOUS
CHARACTER
DATA TO
NEXT ROW 7
CHARACTER

ROW 6

ROW 5

ROW 4

ROW 3

ROW 2

ROW 1

ROW 0
(NOT USED)

Figure 2.

10
Control Word 1 Bits D2‑D6
Loading the Control Register with D7 = logic high selects These bits must always be pro­grammed to logic low.
Control Word 1. This Control Word performs two func-
tions: serial/simultaneous data out mode and external Cascaded ICs
oscillator prescale select (see Table 2). Figure 3 shows how two ICs are connected within an
HCMS‑29xx display. The first IC controls the four left‑most
Serial/Simultaneous Data Output D0 characters and the second IC controls the four right‑most
Bit D0 of control word 1 is used to switch the mode of characters. The Dot Registers are connected in series to
DOUT between serial and simul­ta­neous data entry during form a 320‑bit dot shift register. The location of pixel 0
Control Register writes. The default mode (logic low) is has not changed. However, Dot Shift Register bit 0 of
the serial DOUT mode. In serial mode, DOUT is connected IC2 becomes bit 160 of the 320‑bit dot shift register.
to the last bit (D7) of the Control Shift Register.
The Control Registers of the two ICs are independent
Storing a logic high to bit D0 changes DOUT to simul- of each other. This means that to adjust the display
taneous mode which affects the Control Register only. brightness the same control word must be entered
In simul­taneous mode, DOUT is logically con­nected to into both ICs, unless the Control Registers are set to
DIN. This arrange­ment allows multiple ICs to have their simultaneous mode.
Control Registers written to simul­taneously. For example,
Longer character string systems can be built by cascad-
for N ICs in the serial mode, N*8 clock pulses are needed
ing multi­ple displays together. This is accomplished by
to load the same data in all Control Registers. In the si-
creating a five line bus. This bus consists of CE, RS, BL,
multaneous mode, N ICs only need 8 clock pulses to load
Reset, and CLK. The display pins are connected to the
the same data in all Control Registers. The propaga­tion
corresponding bus line. Thus, all CE pins are connected
delay from the first IC to the last is N * tDOUTP.
to the CE bus line. Similarly, bus lines for RS, BL, Reset,
External Oscillator Prescaler Bit D1 and CLK are created. Then DIN is connected to the
right‑most display. DOUT from this display is connected
Bit D1 of Control Word 1 is used to scale the frequency to the next display. The left‑most display receives its DIN
of an external Display Oscillator. When this bit is logic from the DOUT of the display to its right. DOUT from the
low, the external Display Oscil­la­tor directly sets the inter- left‑most display is not used.
nal display clock rate. When this bit is a logic high, the
external oscilla­tor is divided by 8. This scaled frequency Each display may be set to use its internal oscillator, or
then sets the internal display clock rate. It takes 512 the displays may be synchronized by setting up one
cycles of the display clock (or 8 x 512 = 4096 cycles of display as the master and the others as slaves. The slaves
an external clock with the divide by 8 pre­scaler) to com­ are set to receive their oscillator input from the master’s
pletely refresh the display once. Using the pre­scaler bit oscillator output.
allows the designer to use a higher external oscillator
fre­quency without extra circuitry.
This bit has no affect on the internal Display Oscillator
Frequency.

11
Table 2. Control Shift Register

CONTROL WORD 0

L D6 D5 D4 D3 D2 D1 D0

Bit D7 On-Time Duty Relative

Set Low PWM Brightness Oscillator Factor Brightness
to Select Control Cycles (%) (%)
Control
Word 0 L L L L 0 0 0
L L L H 1 0.2 1.7
L L H L 2 0.4 3.3
L L H H 3 0.6 5.0
L H L L 4 0.8 6.7
L H L H 5 1.0 8.3
L H H L 7 1.4 11.7
L H H H 9 1.8 15
H L L L 11 2.1 18
H L L H 14 2.7 23
H L H L 18 3.5 30
H L H H 22 4.3 37
H H L L 28 5.5 47
H H L H 36 7.0 60
H H H L 48 9.4 80
H H H H 60 11.7 100

Peak Current Typical Peak Relative Full

Brightness Pixel Current Scale Current
Control (mA) (Relative Brightness, %)
H L 4.0 31
L H 6.4 50
L L 9.3 73 (Default at Power Up)
H H 12.8 100

SLEEP MODE L − DISABLES INTERNAL OSCILLATOR-DISPLAY BLANK

H − NORMAL OPERATION

CONTROL WORD 1

H L L L L L D1 D0

Serial/Simultaneous Data Out

Bit D7 L − Dout holds contents of Bit D7
Set High Reserved for Future H − Dout is functionally tied to Din
to Select Use (Bits D2-D6
Control
Word 1 must be set Low) External Display Oscillator Prescaler
L − Oscillator Freq 1
H − Oscillator Freq 8

12
 CE
RS

BL
RESET
CLK

CE CE
RS RS
BL BL
RESET IC1 RESET IC2
CLK BITS 0 – 159 CLK BITS 160 – 319
CHARACTERS 0 – 3 CHARACTERS 4 – 7
DOUT DOUT D IN D OUT DIN
SEL SEL OSC
OSC OSC SEL

DIN

Figure 3. Cascaded ICs

13
Appendix A. Thermal Considerations 1.3
1.2 R θ J-A= 100 °C/W
The display IC has a maximum junction temperature of 1.1
150°C. The IC junction temperature can be calculated 1.0

PD MAX – MAXIMUM POWER

with Equation 1.

DISSIPATION PER IC – W
0.9
0.8
A typical value for RqJ-A is 100 °C/W. This value is typical 0.7
for a display mounted in a socket and covered with a 0.6
plastic filter. The socket is soldered to a .062 in. thick PCB 0.5
with .020 inch wide, one ounce copper traces. 0.4
0.3
PD can be calculated as in Equa­tion 2. 0.2
0.1
Figure 4 shows how to derate the power of one IC versus
0
ambient temperature. Opera­tion at high ambient tem- 25 30 35 40 45 50 55 60 65 70 75 80 85 90
peratures may require the power per IC to be reduced. TA – AMBIENT TEMPERATURE – °C
The power con­sump­tion can be reduced by changing
either the N, IPIXEL, Osc cyc or VLED. Changing VLOGIC has Figure 4.
very little impact on the power consumption.

Appendix B. Electrical Considerations

Equation 1:
TJMAX = TA + PD * RqJA
Where:
TJMAX = maximum IC junction temperature
TA = ambient temperature surrounding the display
RqJA = thermal resistance from the IC junction to ambient
PD = power dissipated by the IC

Equation 2:
PD = (N * IPIXEL * Duty Factor * VLED) + ILOGIC * VLOGIC
Where:
PD = total power dissipation
N = number of pixels on (maximum 4 char * 5 * 7 = 140)
IPIXEL = peak pixel current.
Duty Factor = 1/8 * Osc cyc/64
Osc cyc = number of ON oscillator cycles per row
ILOGIC = IC logic current
VLOGIC = logic supply voltage

Equation 3:
IPEAK = M * 20 * IPIXEL
Where:
IPEAK = maximum instantaneous peak current for the display
M = number of ICs in the system
20 = maximum number of LEDs on per IC
IPIXEL = peak current for one LED

Equation 4:
ILED(AVG) = N * IPIXEL * 1/8 * (oscillator cycles)/64
(see Variable Definitions above)

14
Appendix B. Electrical Considerations (Continued...)
Current Calculations
The peak and average display current requirements have a significant impact on power supply selection. The
maximum peak current is calculated with Equation 3.
The average current required by the display can be calculated with Equation 4.
The power supply has to be able to supply IPEAK transients and supply ILED(AVG) continuously. The range on VLED
allows noise on this supply without sig­nifi­cantly changing the display brightness.

VLOGIC and VLED Considerations

The display uses two indepen­dent electrical systems. One system is used to power the display’s logic and the
other to power the display’s LEDs. These two systems keep the logic supply clean.
Separate electrical systems allow the voltage applied to VLED and VLOGIC to be varied independently. Thus, VLED can
vary from 0 to 5.5 V without affecting either the Dot or the Control Registers. VLED can be varied between 4.0 to
5.5 V with­out any noticeable variation in light output. However, oper­at­ing VLED below 4.0 V may cause objection-
able mismatch between the pixels and is not recommended. Dimming the display by pulse width modulat­ing
VLED is also not recommended.
VLOGIC can vary from 3.0 V to 5.5 V without affecting either the displayed message or the display intensity. How-
ever, operation below 4.5 V will change the timing and logic levels and operation below 3 V may cause the Dot
and Control Registers to be altered.
The logic ground is internally connected to the LED ground by a substrate diode. This diode becomes forward
biased and conducts when the logic ground is 0.4 V greater than the LED ground. The LED ground and the logic
ground should be connected to a common ground which can withstand the current introduced by the switching
LED drivers. When separate ground connections are used, the LED ground can vary from ‑0.3 V to +0.3 V with
respect to the logic ground. Voltages below ‑0.3 V can cause all the dots to be ON. Voltage above +0.3 V can
cause dimming and dot mismatch. The LED ground for the LED drivers can be routed separately from the logic
ground until an appropri­ate ground plane is available. On long interconnections between the display and the
host system, voltage drops on the analog ground can be kept from affecting the display logic levels by isolating
the two grounds.

Electrostatic Discharge
The inputs to the ICs are pro­tected against static discharge and input current latchup. How­ever, for best results,
standard CMOS handling precautions should be used. Before use, the HCMS‑29xx should be stored in antistatic
tubes or in conductive material. During assembly, a grounded conductive work area should be used and assem-
bly personnel should wear conduc­tive wrist straps. Lab coats made of synthetic material should be avoided since
they are prone to static buildup. Input current latchup is caused when the CMOS inputs are subjected to either a
voltage below ground (VIN < ground) or to a voltage higher than VLOGIC (VIN > VLOGIC) and when a high current is
forced into the input. To prevent input current latchup and ESD damage, unused inputs should be con­nected to
either ground or VLOGIC. Voltages should not be applied to the inputs until VLOGIC has been applied to the display.

Appendix C. Oscillator
The oscillator provides the internal refresh circuitry with a signal that is used to synchron­ize the columns and
rows. This ensures that the right data is in the dot drivers for that row. This signal can be supplied from either an
external source or the internal source.
A display refresh rate of 100 Hz or faster ensures flicker‑free operation. Thus for an external oscillator the frequency
should be greater than or equal to 512 x 100 Hz = 51.2 kHz. Operation above 1 MHz without the prescaler or 8
MHz with the prescaler may cause noticeable pixel to pixel mismatch.

15
Appendix D. Refresh Circuitry
This display driver consists of 20 one‑of‑eight column decoders and 20 constant current sources, 1 one‑of‑eight
row decoder and eight row sinks, a pulse width modulation control block, a peak current control block, and the
circuit to refresh the LEDs. The refresh counters and oscillator are used to synchronize the columns and rows.
The 160 bits are organized as 20 columns by 8 rows. The IC illuminates the display by sequentially turning ON
each of the 8 row‑drivers. To refresh the display once takes 512 oscillator cycles. Because there are eight row driv-
ers, each row driver is selected for 64 (512/8) oscillator cycles. Four cycles are used to briefly blank the display
before the following row is switched on. Thus, each row is ON for 60 oscillator cycles out of a possible 64. This
corresponds to the maximum LED on time.

Appendix E. Display Brightness

Two ways have been shown to control the brightness of this LED display: setting the peak current and setting the
duty factor. Both values are set in Control Word 0. To compute the resulting display brightness when both PWM
and peak current control are used, simply multiply the two relative bright­ness factors. For example, if Control
Register 0 holds the word 1001101, the peak current is 73% of full scale (BIT D5 = L, BIT D4 = L) and the PWM is
set to 60% duty factor (BIT D3 = H, BIT D2 = H, BIT D1 = L, BIT D0 = H). The resulting brightness is 44% (.73 x .60
= .44) of full scale.
The temperature of the display will also affect the LED bright­ness as shown in Figure 5.

Intensity Bin Limits for HCMS-29xx (except for HCMS-29x5) 3.0

Intensity Range (mcd) 2.6
RELATIVE LUMINOUS INTENSITY

BIN Min. Max. HER/ORANGE

(NORMALIZED TO 1 AT 25 °C)

2.2
D 1.18 2.07 YELLOW
E 1.78 3.13 1.8
GREEN
F 2.70 4.64 1.4
G 4.00 7.00 DEEP RED
1.0
H 6.00 10.50
I 9.00 15.75 0.6
J 13.58 23.88 0.2
K 20.59 36.03 -55 -35 -15 5 25 45 65 85
TA – AMBIENT TEMPERATURE – °C
L 31.06 54.35
Note: Figure 5.
Test conditions as specified in Optical Characteristic table.

Intensity Bin Limits for HCMS-29x5

Intensity Range (mcd)
BIN Min. Max.
H 6.00 10.50
I 9.00 15.75
J 13.58 23.88
K 20.59 36.03
L 31.06 54.35
M 46.45 80.41
Note:
Test conditions as specified in Optical Characteristic table.

16
Appendix F. Reference Material
Application Note 1027: Soldering LED Components
Applica­tion Note 1015: Contrast Enhancement Techniques for LED Displays

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