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Teaching Computer Organization Using Field Programmable Gate Array: An

Incremental Approach

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 Asian J. Adv. Basic Sci.: 2015, 4(1), 5-11
ISSN (Online): 2347 - 4114
www.ajabs.org

Teaching Computer Organization Using Field Programmable Gate Ar-

ray: An Incremental Approach
Mohammad Awedh* and Ahmed Mueen
King Abdulaziz University, Jeddah, SAUDI ARABIA
*
Correspondance: E-mail: mhawedh,@au.edu.sa and [email protected]

(Received 31 July, 2015; Accepted 03 Aug, 2015; Published 08 Aug, 2015)

ABSTRACT: This paper describes a novel approach to teach computer organization using an incremental ap-
proach of working models on FPGA. It presents the design concepts and realization of MIPS-based architecture into
the teaching tool. Our new approach has improved the student learning and understanding of the major concepts in
computer organization. Our main goal of this study is to compare our method (model) of teaching to the one that
was used prior to this study in our institute.

Keywords: FPGA; MIPS processor; RTL; Verilog; Hardware Description Language; Synthesis; CAD tools; Computer
Organization; Assembly Language; Incremental approach and working models.

INTRODUCTION: The course “computer organiza- lating important features of a processor, students can
tion and architecture” is a common course for com- obtain a better understanding of the internal operation
puter engineering students, which plays a central role of a processor (Yurcik and Wolffe, 2001). Different
in the computer engineering curriculum offered at simulators oriented to help in teaching specific con-
universities throughout the world (Holland & Hauck, cepts in modern computer architectures, such as cache
2003). Teaching this course to computer engineering memory, pipelining, and superscalar organizations
and computer science students solely on textbook (Grnbacher, 1998). In another works, researcher (Li &
materials is inadequate (Hatfield & Rieker, 2005) and Chu, 1932). and (Sugawara & Hiraki, 2006) use ac-
(Kasim et al., 2005). Students have to depend on their tive tool for teaching computer organization and ar-
imaginations to understand the fundamental hard- chitecture by taking benefit of simulation and Field
ware-related concepts. Traditionally, most courses in Programmable Gate Array (FPGA) technology. FPGA
computer architecture and organization include prac- technology helps designing high performance systems
tical work in the laboratory. It is not possible to build at low cost(Sugawara & Hiraki, 2006). This paper
a laboratory that can offer several computer architec- presents novel approach to teach computer organiza-
tures for teaching computer organization and architec- tion using an incremental approach of working mod-
ture. Furthermore, having up-to-date information els on FPGA. Our methodology of teaching digital
needs to be in touch with the rapid evolution of the computer organization course differs from the previ-
computer technology and industry. Therefore, search- ous (traditional) one in two aspects. The first aspect is
ing for an effective way of teaching computer organi- the use of the incremental approaches of working
zation and architecture is a continuing task (Hatfield models. This teaching tool helps computer engineer-
& Rieker, 2005). ing students to be familiarized practically with com-
puter organization through development, design, and
Literature Review: There are some modern teaching
implement of a functional and synthesizable proces-
approaches that combined effective hardware design
sor. The second aspect is the use of Field programma-
and hardware implementation to help students under-
ble gate arrays to implement a real processor. Hence,
standing computer architecture concepts and encour-
the students feel the joy of designing and running a
age students to further work on the field (Hala, 2012).
functional processor in real hardware. The students
One of these approaches is teaching with software
also have the chance of adding more instructions and
simulators, which have several advantages over real
improve the performance. The previous teaching
microcomputer platforms; they are not costly and
method for the course was based on theory of com-
more flexible. In addition, graphical presentation and
puter construction. This method teaches students how
animation support students to better understand vari-
computers work by studying their inner details (e.g.,
ous design issues (Rodriguez et al., 1998). By simu-

5
 [(Asian J. Adv. Basic Sci.: 4(1), 2015, 5-11) Teaching Computer Organization Using Field Programmable Gate Array: An Incre…]

pipelining and cache control) through assembly pro-

gramming of real life processors and organization
simulators. However, this method lacks teaching the
students computer organization through the process of
building a real functional processor from scratch.
Recent technological advances in FPGA and its avail-
ability in low cost allow our approach to become a
reality. FPGA is a powerful hardware prototyping
platforms based on reconfigurable hardware. FPGAs
have been efficiently used by engineers for develop- Figure 1: Block diagram.
ing digital systems, prototyping, design exploration,
and experiments (Aws et al., 2011). Designers use an
HDL to describe the behavior and structure of system
and circuit designs (Hana et al., 2013). FPGAs have
shorten the design time significantly. Potential appli-
cations using FPGAs are extremely wide (Jong et al.,
2012). Examples are application-oriented soft proces-
sors, embedded systems, and systems on programma-
ble chip, programmable network chips, and many
others. One of the early uses of FPGA to implement a
processor is presented in (Li & Chu, 1996). In this
Figure 2: Digilent Basys2 FPGA Board.
paper, a hardware design and implementation of pipe-
lined RISC processor in FPGA chip is presented.
Table 1: Memory-mapped I/O addresses.
Some recent results in teaching reconfigurable sys-
tems are discussed in (Sklyarov & Skliarova, 2005)
I/O Address
(Jean et al., 2015). Where models, methods and ped-
agogical innovations (such as using the developed 7 Seg 0xD000
student-oriented design templates and evaluation Leds 0xE000
through mini-projects) are considered. Our teaching is Switches 0xF000
based on the textbook by Patterson and Hennessy
(Patterson & Hennessy, 2014). This paper is struc-
MATERIAL AND METHODS: This paper de-
tured as follows. We first briefly introduce the pro-
scribes an incremental approach of teaching computer
posed methodology.
organization based on the idea of “working models”
Designers use an HDL to describe the behavior and (Hermie, 2010). These “working models” are based
structure of system and circuit designs. Understanding on pedagogical designs presented in Patterson &
FPGA architecture allows you to create HDL code Hennessy’s text Computer Organization and Design
that effectively uses FPGA system features. (Patterson & Hennessy, 2014).
Hardware Platform: Our hardware platform is based In our approach, we present to the students fully-
on a simple RISC-based MIPS architecture (Patterson functional processor in different levels of design ab-
& Hennessy, 2014) implemented in Digilent Basys2 straction. In each level of design abstraction, students
Spartan3E FPGA Board (Digilent, 2015). The FPGA modify and extend these designs to enhance their
board, Figure 2, contains I/O devices (peripherals) understanding of digital computer design; instruction
among which, 8 LEDs, 4-digit seven-segment display, set design, performance optimization as well as de-
4 pushbuttons, and 8 slide switches are used, Figure 1. veloping design validation skills. Two level of design
For MIPS processor to access the I/O devices on the abstraction are used: Behavioral modeling and regis-
FPGA board, we use memory mapped I/O technique. ter transfer level (RTL) modeling. Behavioral model-
Three special memory addresses are used to access ing is often used to explore high-level features and
these I/O devices. Table 1 lists these I/O devices and functions; RTL modeling is often used to describe
their addresses. We use the least significant byte (8 block diagram view of a circuit at the level of regis-
bits) of an internal register for switches and LEDs; we ters, flip-flops and functional blocks that constitute
use the least significant half word (16 bits) of an inter- the design.
nal registers for the 4-digit seven-segment display.

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 [(Asian J. Adv. Basic Sci.: 4(1), 2015, 5-11) Teaching Computer Organization Using Field Programmable Gate Array: An Incre…]

Behavioral Description of a Simple MIPS Proces- porting Procedures in Computer Hardware) talks
sor: The first phase in our teaching methodology is to about supporting procedures in MIPS. This section
help our students understand and realize the detailed was explained in detail prior to the assignment. To
operation (function) of processors. A behavioral de- support such function, students have to implement two
scription (in Verilog) of a simple single-cycle MIPS new instructions: jal and jr. The students first have to
processor was presented to the students. This Verilog modify the single-cycle design of MIPS (Figure 3) and
module of the single-cycle MIPS processor is fully show how the basic data path and control unit can be
synthesizable and implementable in FPGA. The pro- extended to handle these new instructions. This re-
cessor implements the following subset of MIPS in- quired an addition of the proper control signals and
structions: or, ori, and, andi, beq, sub, add, slt, lw, sw, hardware (e.g., multiplexers). Then, they implement
j. their modifications into the provided Verilog code.
Figure 4 shows the complete top-level system design
The students were asked to modify the Verilog behav-
using Xilinix ISE CAD tool the amount of FPGA
ioral description of the MIPS machine to run the fol-
resources used.
lowing MIPS code. The code has some MIPS instruc-
tions that are not implemented in the given Verilog Pipelined MIPS Processor: The third phase of our
behavioral description. teaching is to implement the piplined MIPS. The goal
.text is for our students to gain a deeper understanding of
# Address of
pipelined processor implementation.
ori $s0 , $0 , 0xD000
7−segment
ori $s1 , $0 , 0xE000 # Address of LEDs

ori $s2 , $0 , 0xF000 # Address of SWs

lw $s6 , 0( $s2 ) # read switches

loop sr l $s7 , $s 6 ,2

xor $s7 , $s6 , $s7

sw $s7 , 0( $s1 ) # Display onto LEDs

# Display result in
sw $s6 , 0( $s0 )
7−Seg
addi $s6 , $s6 , −1

bne $s6 , $0 ,loop Figure 3: Single Cycle MIPS Processor.

here j here

RTL Description of a Simple MIPS Processor: The

goal of this phase is to teach the students the design of
a processor on a structural level. We use the principles
and techniques to design and implement a single-cycle
processor as explained in Chapter 4 of (Hermie,
2010). Figure 3 depicts the simple single-cycle MIPS
processor as described in (Hermie, 2010). The design
implements a subset of the core MIPS instruction set:
– The memory-reference instructions load word (lw)
and store word (sw)
– The arithmetic-logical instructions add, sub, and,
or, and slt Figure 4: Top-level Design of Single-Cycle MIPS
– The instructions branch equal (beq) and jump (j) processor.
A complete functional and synthesizable Verilog de- A fully synthesizable Verilog module of the data
scription of a single-cycle processor (Figure 4) was path of the pipelined MIPS (Hermie, 2010), Figure
presented to the students and they were asked to modi- 5, is given to the students. The students were
fy the Verilog code to implement procedures (Call and asked to implement the pipelined control unit on
Return) in MIPS. Section 2.8 of (Hermie, 2010) (Sup- the datapath implementation.
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 [(Asian J. Adv. Basic Sci.: 4(1), 2015, 5-11) Teaching Computer Organization Using Field Programmable Gate Array: An Incre…]

some of the questions in the survey for the three se-

mesters.
Table 2: Students Background in Using HDL.
Which HDL do Verilog VHDL Others None
you know
(choose one)? 85% 10% 0% 5%

Which design Behavioral RTL Logic Physical

abstraction
level do you
use HDL? 100% 40% 30% 0%

Have you ever Yes No

used HDL to
design FPGA
devices? 5% 95%

Figure 5: The pipelined datapath with the con- Only Simulation Simulation and
trol signals identified. I used HDL for Synthesis
95% 5%
Final Projects: The final project is to extend the pipe-
lined implementation to perform data forwarding and To evaluate our teaching approach, two surveys were
data hazard detection. After the students have success- conducted; one was after the second phase and the
fully implemented their pipelined processors, they second at the end of the semester. The goal of the first
were given real programs that failed to run because of survey is to evaluate the students’ progress as well as
the data hazard. These programs are control-hazard their feedback to improve the course. Among the
free. questions of this survey were a set that evaluates our
Even though, data forwarding and data hazard are method so far and gains students feedback. The five-
well explained in (Hermie, 2010), some students point Likert scale items (Likert, 1932) were used in
struggled to have their processors correctly imple- these surveys and the average students’ responses for
mented in FPGA. Hence, we decided to make the final the three semesters are presented.
project a group project of two students. Table 3 shows the average students responses on our
teaching methodology for the three semesters. The
RESULTS AND DISCUSSION: Our new approach results show the success of our new approach. How-
had been applied for three consecutive semesters. The ever, pipelined processor design had not been includ-
number of students in each semester is 10 on the av- ed yet. We believe, complex design (like pipelined
erage. Therefore, we decide to evaluate our method- process design) will be a major and better factor to
ology after the third semester. Any new enhancement evaluate the success of our teaching methodology.
and improvement to the new approach will be applied Hence, we decide to include the same set of questions
for a future teaching of the course. However, surveys in the final survey (at the end of the semester).
are conducted in each semester. To prepare for apply- We also include in this survey the evaluation of the
ing our teaching approach, a survey was conducted at tools that we used in our teaching: Verilog as a hard-
the first day of the class. The goal is to evaluate stu- ware description language and FGPA as an imple-
dents’ background and readiness. This survey helped menting hardware. Table 4 shows students’ feedback
in preparing labs, extra materials and tutorials. A set on using these teaching tools. Another set of ques-
of questions are related to the profile data of the stu- tions are related to the course contents and students
dents attending the courses. Information collected concern. Table 5 shows the students feedback.
includes the background materials in Digital Design – The final survey was conducted at the end of each
related to combinational and sequential design of semester. The first set of questions is dedicated to
digital systems. Another set of questions are related to evaluate the overall quality of the course and com-
using Hardware Description Language (HDL) for pared to other courses in the Computer Engineering
design, debugging and functional simulation of digital curriculum. Table 6 shows students feedback. Table 7
systems; and the implementation of digital circuits shows the overall quality of the teaching tools.
using FPGAs. Table 2 shows the average results of We also included in the final survey the two questions
that were asked in the second survey. The goal is to
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 [(Asian J. Adv. Basic Sci.: 4(1), 2015, 5-11) Teaching Computer Organization Using Field Programmable Gate Array: An Incre…]

evaluate our methodology after students finish their Table 4: Student Evaluation of Using HDL and
implementation of pipelined design and final projects. FPGA.
In addition, a couple of questions were added to eval-
uate the overall methodology. Table 8 depicts the Too Extremely
Easy Fair Hard
average students’ responses for the three semesters. Easy Hard
Using Verilog
Table 3: Evaluation of Our Teaching Method- to describe 5% 60% 20% 10% 5%
ology: First Feedback. digital design
Using Verilog
Question: Modifying working models and
for Functional 82% 13% 3% 2% 0%
adding new instructions helped me realized Simulation
and understand computer design Using FPGA to
implement 0% 10% 45% 30% 15%
digital design
Strongly Strongly
Agree Undecided Disagree
Agree Disagree
Table 5: Course Contents and Students Con-
cern.
77% 16% 7% 0% 0%
Too Extremely
Easy Fair Hard
Question: Incrementally increase the complexity Easy Hard
of a design helped me understand process design Using Verilog
to describe 5% 60% 20% 10% 5%
Strongly Strongly digital design
Agree Undecided Disagree Using Verilog
Agree Disagree for Functional 82% 13% 3% 2% 0%
Simulation
81% 18% 1% 0% 0% Using FPGA
to implement 0% 10% 45% 30% 15%
digital design

Table 6: Overall Quality of the Course.

Overall importance of the courses for Computer Engineering students
Slightly im- Fairly im-
Not important Important Very important
portant portant
0% 2% 11% 24% 63%
Classification among all courses in Computer Engineering
Too Easy Easy Fair Hard Extremely Hard
5% 12% 23% 29% 31%
Degree of motivation to pursue hardware studies
Too Low Low Moderate High Too High
3% 4% 13% 37% 43%
Overall quality of the contents presented in the course
Too Easy Easy Fair Hard Extremely Hard
0% 10% 45% 30% 15%

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[(Asian J. Adv. Basic Sci.: 4(1), 2015, 5-11) Teaching Computer Organization Using Field Programmable Gate Array: An Incre…]

Table 7: Overall Quality of the Teaching Tools. CONCLUSION: This paper has described the use of
FPGA to reinforce the concepts of Computer Organi-
The availability of resources zation design using an incremental approach in which
Extremely students extend and modify existing models. It high-
Too Easy Easy Fair Hard
Hard lights the importance of design process abstraction
94% 6% 0% 0% 0% levels for teaching hardware design to students in a
The complexity of the tools hands-on manner.
Extremely A positive feedback we got is from the senior project
Too Easy Easy Fair Hard committee. The committee has stated that a small,
Hard
however increasing, number of senior projects use
23% 52% 12% 7% 6%
soft processor in their senior projects has been no-
Using Verilog to describe and simulate digital ticed. Some students have modified the original de-
design sign of the processor and include it in their design of
Strongly Strongly Dis- embedded systems.
Agree Undecided Disagree
Agree agree Students’ responses to our new teaching methodology
74% 21% 4% 1% 0% have been enthusiastic; they indicate in comments of
Using FPGA to implement digital design the final survey that the method has greatly enhanced
Strongly Strongly Dis- their understanding of processor design. However,
Agree Undecided Disagree some students suggested to use simpler processor;
Agree agree
mostly suggested 8-bit version of the MIPS structure
63% 26% 7% 1% 3%
as presented in (Hermie, 2010). In addition, almost all
students suggested working in fixed number of
Table 8: Evaluation of Our Teaching Method- groups (two or three) from the beginning of the
ology: Second Feedback. course.
In future courses, it would be beneficial to include the
Modifying working models and adding new in- design of a cache memory in our design methodolo-
structions helped me realized and understand gy; students may implement and improve some
computer design cache-related design issues. For instance, improving
Strongly Strongly cache performance, applying different methods of
Agree Undecided Disagree
Agree Disagree handling cache misses and writes. Furthermore, final
79% 13% 7% 0% 1% projects can be more beneficial by including more
Incrementally increase the complexity of a design issues. For instance, the implementation of
design helped me understand process design control hazard (specifically, the static and dynamic
Strongly Strongly branch prediction) and improving cache performance.
Agree Undecided Disagree To reach to the above mentioned steps of processor
Agree Disagree
and cache design, we are working, as also suggested
78% 19% 1% 0% 2% by the students, in using simpler MIPS processor.
The Overall teaching method used is useful Simple processor design helps to expedite and debug
and helpful in understanding complex digi- design without scarifying in understanding the major
tal design concepts of computer organization design.
Strongly Strongly
Agree Undecided Disagree
Agree Disagree REFERENCES:
76% 24% 0% 0% 0% 1. Aws Yousif, Fida El-Din and Hasan Krad (2011)
The teaching technique used is adequate for Teaching Computer Architecture and Organization
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Agree Undecided Disagree 2. Digilent (2015) Digilent Basys 2 Spartan-3E
Agree Disagree
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