BUF20800

SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

18-Channel GAMMA VOLTAGE GENERATOR

with Two Programmable VCOM Channels
FEATURES APPLICATIONS
D 18-CHANNEL GAMMA CORRECTION D REPLACES RESISTOR-BASED GAMMA
D 2-CHANNEL PROGRAMMABLE VCOM: SOLUTIONS
100mA IOUT D TFT-LCD REFERENCE DRIVERS
D 10-BIT RESOLUTION
D DYNAMIC GAMMA CONTROL
D RAIL-TO-RAIL OUTPUT
D LOW SUPPLY CURRENT: 900µA/ch
D SUPPLY VOLTAGE: 7V to 18V DESCRIPTION
D DIGITAL SUPPLY: 2.0V to 5.5V
D INDUSTRY-STANDARD, TWO-WIRE The BUF20800 is a programmable voltage reference
INTERFACE: generator designed for gamma correction in TFT-LCD
panels. It provides 18 programmable outputs for gamma
3.4MHz High-Speed Mode
correction and two channels for VCOM adjustment, each
D HIGH ESD RATING: with 10-bit resolution.
4kV HBM, 1kV CDM, 200V MM
This programmability replaces the traditional, time-
D DEMO BOARD AND SOFTWARE AVAILABLE
consuming process of changing resistor values to optimize
Analog Digital
(7V to 18V) (2.0V to 5.5V) REFH the various gamma voltages and allows designers to
determine the correct gamma voltages for a panel very
BUF20800 quickly. Required changes can also be easily implemented
without hardware changes.
REFH OUT The BUF20800 uses TI’s latest, small-geometry analog
CMOS process, which makes it a very competitive choice
VCO M OUT1
for full production, not just evaluation.

VCO M OUT2
Programming of each output occurs through an industry-
standard, two-wire serial interface. Unlike existing
programmable buffers, the BUF20800 offers a high-speed
mode that allows clock speeds up to 3.4MHz.
DAC Registers

DAC Registers

OUT 1

For lower channel count, please contact your local sales

OUT 2
or marketing representative.
The BUF20800 is available in an HTSSOP-38
…

18 Output Channels plus

Two VCOM Channels PowerPAD package. It is specified from −40°C to +85°C.

OUT 17 BUF20800 RELATED PRODUCTS

FEATURES PRODUCT
OUT 18 18-Channel Programmable, Two VCOM + OTP Memory BUF20820
12-Channel Programmable Buffer, 10-Bit BUF12800
REFL OUT Programmable VCOM BUF01900
SDA 11-, 6-, 4-Channel Gamma Correction Buffer, 18V Supply BUFxx704
Control IF High-Speed VCOM, 1 and 2 Channels SN10501
SCL
Complete LCD DC/DC Solution TPS65100

LD AO REFL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

             
 Copyright  2005−2007, Texas Instruments Incorporated
                  

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS(1)

Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +19V
Supply Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Signal Input Terminals, SCL, SDA, AO, LD:
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Output Short Circuit(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
ESD Rating:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is
not supported.
(2) Short-circuit to ground, one amplifier per package.

ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
BUF20800 HTSSOP-38 BUF20800 DCP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at [Link].

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ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = −40°C to +85°C.
At TA = +25°C, VS = 18V, VSD = 5V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
BUF20800
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG
Gamma Output Swing—High OUT 1−9, Sourcing 10mA, VREFH = 17.8V, Code 1023 17.7 17.8 V
OUT 10−18, Sourcing 10mA, VREFH = 17.8V, Code 1023 17.0 17.2 V
Gamma Output Swing—Low OUT 1−9, Sinking 10mA, VREFL = 0.2V, Code 00 0.6 1.0 V
OUT 10−18, Sinking 10mA, VREFL = 0.2V, Code 00 0.2 0.3 V
VCOM Buffer Output Swing—High VCOM, Sourcing 100mA, VREFH = 17.8V 13 15.5 V
VCOM Buffer Output Swing—Low VCOM, Sinking 100mA, VREFL = 0.2V 1 2.0 V
Output Current(1) IO All Channels, Code 512, Sinking/Sourcing 40 45 mA
REFH Input Range(2) 4 VS V
REFL Input Range(2) GND VS − 4 V
Integral Nonlinearity INL No Load, VREFH = 17V, VREFL = 1V 0.3 1.5 Bits
Differential Nonlinearity DNL No Load, VREFH = 17V, VREFL = 1V 0.3 1 Bits
Gain Error 0.12 %
Program to Out Delay tD 5 µs
Output Accuracy No Load, VREFH = 17V, VREFL = 1V ±20 ±50 mV
Over Temperature ±25 mV
Input Resistance at VREFH and VREFL RINH 100 MΩ
Load Regulation, All References REG VOUT = VS/2, IOUT = +5mA to −5mA Step 0.5 1.5 mV/mA
40mA, All Channels VOUT = VS/2, ISINKING = 40mA, ISOURCING = 40mA 0.5 1.5 mV/mA
ANALOG POWER SUPPLY
Operating Range VS 7 18 V
Total Analog Supply Current IS No Load 18 28 mA
over Temperature 28 mA
DIGITAL
Logic 1 Input Voltage VIH 0.7 × VSD V
Logic 0 Input Voltage VIL 0.3 × VSD V
Logic 0 Output Voltage VOL ISINK = 3mA 0.15 0.4 V
Input Leakage ±0.01 ±10 µA
Clock Frequency fCLK Standard/Fast Mode 400 kHz
High-Speed Mode 3.4 MHz
DIGITAL POWER SUPPLY
Operating Voltage Range VSD 2.0 5.5 V
Digital Supply Current(3) ISD Outputs at Reset Values, No-Load, Two-Wire Bus Inactive 25 50 µA
over Temperature 100 µA
TEMPERATURE
Specified Temperature Range −40 +85 °C
Operating Temperature Range Junction Temperature < +125°C −40 +95 °C
Storage Temperature Range −65 +150 °C
Thermal Resistance, HTSSOP-38
Junction-to-Ambient qJA 30 °C/W
Junction-to-Case qJC 15 °C/W
(1) See typical characteristic Output Voltage vs Output Current.
(2) See applications information section REFH and REFL Input Range.
(3) See typical characteristic Digital Supply Current vs Temperature.

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PIN CONFIGURATIONS
Top View HTSSOP

VCOM OUT 2 1 38 VCOM OUT 1

REFH 2 37 REFL

NC(1) 3 36 NC (1)

NC(1) 4 35 NC (1)

OUT 1 5 34 REFL OUT

OUT 2 6 33 OUT 18

OUT 3 7 32 OUT 17

OUT 4 8 31 OUT 16

OUT 5 9 PowerPAD 30 OUT 15

Lead−Frame
OUT 6 10 Die Pad 29 OUT 14
Exposed on
GNDA (2) 11 28 GNDA(2)
Underside

VS 12 27 VS

OUT 7 13 26 OUT 13

OUT 8 14 25 OUT 12

OUT 9 15 24 OUT 11

REFH OUT 16 23 OUT 10

VSD 17 22 GNDD(2)

SCL 18 21 LD

SDA 19 20 AO

(1) NC denotes no connection.

(2) GNDD and GNDA are internally connected and must be at the same voltage potential.

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TYPICAL CHARACTERISTICS
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.

ANALOG SUPPLY CURRENT vs TEMPERATURE DIGITAL SUPPLY CURRENT vs TEMPERATURE

16 30
VS = 18V VS = 5V
14
25
12
VS = 10V
20
Analog I Q (mA)

Digital IQ (µA)
10 VS = 3.3V

8 15

6
10
4
5
2

0 0
−40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100
Temperature (_ C) Temperature (_ C)

Figure 1 Figure 2

FULL−SCALE OUTPUT SWING OUTPUT VOLTAGE vs OUTPUT CURRENT

18
REFH = 17V
REFL = 1V 17
Output Voltage (5V/div)

16 OUT10−18 (sourcing), Code = 3FFh

Output Voltage (V)

Code 3FF →000 VREFL = 0.2V, VREFH = 17V OUT1−9, V COM

1−2 (sourcing)
15 RLOAD Connected to GND Code = 3FFh
VREFL = 1V, VREFH = 17.8V
RLOAD Connected to GND
OUT1−9, VCOM1−2 (sinking)
3 OUT10−18 (sinking), Code = 000h
Code = 000h
Code 000 →3FF VREFL = 1V, VREFH = 17.8V
VREFL = 0.2V, VREFH = 17V
2 RLOAD Connected to 18V
RLOAD Connected to 18V
1

0
Time (1µs/div) 0 10 20 30 40 50 60 70 80 90 100
Output Current (mA)

Figure 3 Figure 4

INTEGRAL NONLINEARITY ERROR vs INPUT CODE DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
0.6 0.6

0.4 0.4
DNL Error (LSB)

0.2
INL Error (LSB)

0.2

0 0

−0.2 −0.2

−0.4 −0.4

−0.6 −0.6
0 200 400 600 800 1000 0 200 400 600 800 1000
Input Code Input Code

Figure 5 Figure 6

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the serial clock on the clock signal line (SCL), controls the
APPLICATIONS INFORMATION bus access, and generates the START and STOP
The BUF20800 programmable voltage reference allows conditions.
fast, easy adjustment of 18 programmable reference
outputs and two channels for VCOM adjustment, each with To address a specific device, the master initiates a START
10-bit resolution. It offers very simple, time-efficient condition by pulling the data signal line (SDA) from a HIGH
adjustment of the gamma reference and VCOM voltages. to a LOW logic level while SCL is HIGH. All slaves on the
The BUF20800 is programmed through a high-speed, bus shift in the slave address byte, with the last bit
standard, two-wire interface. The BUF20800 features a indicating whether a read or write operation is intended.
double-register structure for each DAC channel to simplify During the 9th clock pulse, the slave being addressed
the implementation of dynamic gamma control. This responds to the master by generating an Acknowledge
structure allows pre-loading of register data and rapid and pulling SDA LOW.
updating of all channels simultaneously.
Data transfer is then initiated and eight bits of data are sent
Buffers 1−9 are able to swing to within 200mV of the followed by an Acknowledge Bit. During data transfer,
positive supply rail, and to within 0.6V of the negative SDA must remain stable while SCL is HIGH. Any change
supply rail. Buffers 10−18 are able to swing to within 0.8V in SDA while SCL is HIGH will be interpreted as a START
of the positive supply rail and to within 200mV of the or STOP condition.
negative supply rail.
Once all data has been transferred, the master generates
The BUF20800 can be powered using an analog supply a STOP condition indicated by pulling SDA from LOW to
voltage from 7V to 18V, and a digital supply from 2V to HIGH while SCL is HIGH.
5.5V. The digital supply must be applied prior to or
simultaneously with the analog supply to avoid excessive The BUF20800 can act only as a slave device; therefore,
current and power consumption; damage to the device it never drives SCL. SCL is only an input for the BUF20800.
may occur if it is left connected only to the analog supply Table 1 and Table 2 summarize the address and
for extended periods of time. Figure 7 shows the power command codes, respectively, for the BUF20800.
supply timing requirements.

ADDRESSING THE BUF20800

VSD The address of the BUF20800 is 111010x, where x is the
Digital Supply: GND D state of the A0 pin. When the A0 pin is LOW, the device will
acknowledge on address 74h (1110100). If the A0 pin is
VS HIGH, the device will acknowledge on address 75h
(1110101).
Analog Supply: GND
t1
Other valid addresses are possible through a simple mask
t1: 0s minimum delay between Digital Supply and Analog Supply. change. Contact your TI representative for information.

Figure 7. Power Supply Timing Requirements Table 1. Quick-Reference Table of BUF20800

Addresses
Figure 8 shows the BUF20800 in a typical configuration. DEVICE/COMPONENT ADDRESS
In this configuration, the BUF20800 device address is 74h. BUF20800 Address:
The output of each digital-to-analog converter (DAC) is A0 pin is LOW
1110100
immediately updated as soon as data are received in the (device will acknowledge on address 74h)
corresponding register (LD = 0). For maximum dynamic A0 pin is HIGH
1110101
range, set VREFH = VS − 0.2V and VREFL = GND + 0.2V. (device will acknowledge on address 75h)

TWO-WIRE BUS OVERVIEW Table 2. Quick-Reference Table of Command

The BUF20800 communicates through an industry- Codes
standard, two-wire interface to receive data in slave mode. COMMAND CODE
This standard uses a two-wire, open-drain interface that Address byte of 00h followed by a data byte
General Call Reset
supports multiple devices on a single bus. Bus lines are of 06h.
driven to a logic low level only. The device that initiates the 00001xxx, with SCL ≤ 400kHz; where xxx
communication is called a master, and the devices High-Speed Mode are bits unique to the Hs-capable master.
controlled by the master are slaves. The master generates This byte is called the Hs master code.

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(1)
BUF20800 (1)
VCOM1 1 VCOM OUT2 VCOM OUT1 38 VCOM2

VS 2 REFH(3) REFL(3) 37 VS

3 NC NC 36

4 NC NC 35

(1)
5 OUT1 REFL OUT 34

(1) (1)
6 OUT2 OUT18 33

(1) (1)
7 OUT3 OUT17 32
Source
Driver
(1) (1) Source
8 OUT4 OUT16 31
Driver

(1) (1)
9 OUT5 OUT15 30

(1) (1)
10 OUT6 OUT14 29

11 GNDA(2) GNDA(2) 28

VS 12 VS VS 27 VS
100nF 10µF 100nF 10µF

(1) (1)
13 OUT7 OUT13 26

Source (1) (1)

14 OUT8 OUT12 25
Driver
Source
Driver
(1) (1)
15 OUT9 OUT11 24

(1)
16 REFH OUT OUT10 23

3.3V 17 VSD GNDD(2) 22

1µF 100nF

18 SCL LD 21
Timing
Controller
19 SDA AO 20

(1) RC combination optional.

(2) GNDA and GNDD must be connected together.
(3) Connecting a capacitor to this node is not recommended.

Figure 8. Typical Application Configuration

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DATA RATES OUTPUT VOLTAGE

The two-wire bus operates in one of three speed modes: Buffer output values are determined by the reference
D Standard: allows a clock frequency of up to 100kHz; voltages (VREFH and VREFL) and the decimal value of the
D Fast: allows a clock frequency of up to 400kHz; and binary input code used to program that buffer. The value is
D High-speed mode (or Hs mode): allows a clock calculated using Equation 1:
frequency of up to 3.4MHz.
VOUT + ƪ
VREFH * VREFL
1024
ƫ
Decimal Value of Code ) VREFL
(1)
The BUF20800 is fully compatible with all three modes. No
special action is required to use the device in Standard or
The valid voltage ranges for the reference voltages are:
Fast modes, but High-speed mode must be activated. To
activate High-speed mode, send a special address byte of 4V v V REFH v VS * 0.2V and 0.2V v VREFL v VS * 4V (2)
00001xxx, with SCL = 400kHz, following the START
condition; xxx are bits unique to the Hs-capable master, The BUF20800 outputs are capable of a full-scale voltage
which can be any value. This byte is called the Hs master output change in typically 5µs—no intermediate steps are
code. (Note that this is different from normal address required.
bytes—the low bit does not indicate read/write status.) The
BUF20800 will respond to the High-speed command OUTPUT LATCH
regardless of the value of these last three bits. The
Updating the DAC register is not the same as updating the
BUF20800 will not acknowledge this byte; the
DAC output voltage, because the BUF20800 features a
communication protocol prohibits acknowledgement of
double-buffered register structure. There are three
the Hs master code. On receiving a master code, the
methods for latching transferred data from the storage
BUF20800 will switch on its Hs mode filters, and
registers into the DACs to update the DAC output
communicate at up to 3.4MHz. Additional high-speed
voltages.
transfers may be initiated without resending the Hs mode
byte by generating a repeat START without a STOP. The Method 1 requires externally setting the latch pin (LD)
BUF20800 will switch out of Hs mode with the next STOP LOW, LD = LOW, which will update each DAC output
condition. voltage whenever its corresponding register is updated.
GENERAL CALL RESET AND POWER-UP Method 2 externally sets LD = HIGH to allow all DAC
The BUF20800 responds to a General Call Reset, which output voltages to retain their values during data transfer
is an address byte of 00h (0000 0000) followed by a data and until LD = LOW, which will then simultaneously update
byte of 06h (0000 0110). The BUF20800 acknowledges the output voltages of all DACs to the new register values.
both bytes. Upon receiving a General Call Reset, the Use this method to transfer a future data set in advance to
BUF20800 performs a full internal reset, as though it had prepare for a very fast output voltage update.
been powered off and then on. It always acknowledges the Method 3 uses software control. LD is maintained HIGH,
General Call address byte of 00h (0000 0000), but does and all DACs are updated when the master writes a 1 in bit
not acknowledge any General Call data bytes other than 15 of any DAC register. The update will occur after
06h (0000 0110). receiving the 16-bit data for the currently-written register.
The BUF20800 automatically performs a reset upon The General Call Reset and the power-up reset will update
power up. As part of the reset, all outputs are set to the DAC regardless of the state of the latch pin.
(VREFH − VREFL)/2. Other reset values are available as a
custom modification—contact your TI representative for
details. READ/WRITE OPERATIONS
The BUF20800 is able to read from a single DAC, or
The BUF20800 resets all outputs to (VREFH − VREFL)/2
multiple DACs, or write to the register of a single DAC, or
after sending the device address, if a valid DAC address
multiple DACs in a single communication transaction.
is sent with bits D7 to D5 set to ‘100’. If these bits are set
DAC addresses begin with 0000 0000, which corresponds
to ‘010’, only the DAC being addressed in this most
to DAC_1, through 0001 0011, which corresponds to
significant byte (MSB) and the following least significant
VCOM OUT2.
byte (LSB) will be reset.
Write commands are performed by setting the read/write
bit LOW. Setting the read/write bit HIGH will perform a read
transaction.

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Writing: To write to multiple DAC registers:

To write to a single DAC register: 1. Send a START condition on the bus.
1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW.
2. Send the device address and read/write bit = LOW. The BUF20800 will acknowledge this byte.
The BUF20800 will acknowledge this byte. 3. Send either the DAC_1 address byte to start at the first
3. Send a DAC address byte. Bits D7−D5 must be set to DAC, or send the address byte for whichever DAC will
0. Bits D4−D0 are the DAC address. Only DAC be the first in the sequence of DACs to be updated.
addresses 00000 to 10011 are valid and will be The BUF20800 will begin with this DAC and step
acknowledged. Table 3 shows the DAC addresses. through subsequent DACs in sequential order.
4. Send the bytes of data; begin by sending the most
4. Send two bytes of data for the specified DAC register.
Begin by sending the most significant byte first (bits significant byte (bits D15−D8, of which only bits D9
and D8 have meaning), followed by the least
D15−D8, of which only bits D9 and D8 are used, and
significant byte (bits D7−D0). The first two bytes are
bits D15−D14 must not be 01), followed by the least
for the DAC addressed in step 3 above. Its register is
significant byte (bits D7−D0). The register is updated
after receiving the second byte. automatically updated after receiving the second byte.
The next two bytes are for the following DAC. That
5. Send a STOP condition on the bus. DAC register is updated after receiving the fourth byte.
This process continues until the registers of all
Table 3. DAC Addresses following DACs have been updated.
DAC ADDRESS 5. Send a STOP condition on the bus.
DAC_1 0000 0000 The BUF20800 will acknowledge each byte. To terminate
DAC_2 0000 0001 communication, send a STOP or START condition on the
DAC_3 0000 0010
bus. Only DAC registers that have received both bytes of
DAC_4 0000 0011
data will be updated.
DAC_5 0000 0100
DAC_6 0000 0101 Reading:
DAC_7 0000 0110
DAC_8 0000 0111
Reading a DAC register will return the data stored in the
DAC_9 0000 1000 DAC. This data can differ from the data stored in the DAC
DAC_10 0000 1001 register. See the Output Latch section.
DAC_11 0000 1010
To read the DAC value:
DAC_12 0000 1011
DAC_13 0000 1100 1. Send a START condition on the bus.
DAC_14 0000 1101 2. Send the device address and read/write bit = LOW.
DAC_15 0000 1110 The BUF20800 will acknowledge this byte.
DAC_16 0000 1111
DAC_17 0001 0000 3. Send the DAC address byte. Bits D7−D5 must be set
DAC_18 0001 0001 to 0; Bits D4−D0 are the DAC address. Only DAC
VCOM OUT1 0001 0010 addresses 00000 to 10011 are valid and will be
VCOM OUT2 0001 0011 acknowledged.
4. Send a START or STOP/START condition on the bus.
The BUF20800 will acknowledge each data byte. If the 5. Send correct device address and read/write
master terminates communication early by sending a bit = HIGH. The BUF20800 will acknowledge this
STOP or START condition on the bus, the specified byte.
register will not be updated. Updating the DAC register is
6. Receive two bytes of data. They are for the specified
not the same as updating the DAC output voltage. See the
DAC. The first received byte is the most significant
Output Latch section.
byte (bits D15−D8; only bits D9 and D8 have
The process of updating multiple DAC registers begins the meaning); the next byte is the least significant byte
same as when updating a single register. However, (bits D7−D0).
instead of sending a STOP condition after writing the 7. Acknowledge after receiving the first byte.
addressed register, the master continues to send data for 8. Do not acknowledge the second byte to end the read
the next register. The BUF20800 automatically and transaction.
sequentially steps through subsequent registers as
additional data is sent. The process continues until all Communication may be terminated by sending a
desired registers have been updated or a STOP condition premature STOP or START condition on the bus, or by not
is sent. sending the acknowledge.

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SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

To Read Multiple DACs: 6. Receive two bytes of data. They are for the specified
1. Send a START condition on the bus. DAC. The first received byte is the most significant
2. Send the device address and read/write bit = LOW. byte (bits D15−D8, only bits D9 and D8 have
The BUF20800 will acknowledge this byte. meaning); the next byte is the least significant byte
(bits D7−D0).
3. Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will 7. Acknowledge after receiving each byte of data except
be the first in the sequence of DACs to be read. The for the last byte. The acknowledge bit of the last byte
BUF20800 will begin with this DAC and step through should be HIGH to end the read operation.
subsequent DACs in sequential order. 8. When all desired DACs have been read, send a STOP
4. Send a START or STOP/START condition on the bus. or repeated START condition on the bus.
5. Send correct device address and read/write Communication may be terminated by sending a
bit = HIGH. The BUF20800 will acknowledge this premature STOP or START condition on the bus, or by not
byte. sending the acknowledge.

10
 Write single DAC register. P4−P0 specify DAC address. Write Operation
[Link]

Start Device Address Write Ackn DAC address pointer. D7−D5 must be 000. Ackn DAC MSbyte. D14 must be 0. Ackn DAC LSbyte Ackn Stop

SCL

SDA_in A6 A5 A4 A3 A2 A1 A0 W A c kn D7 D6 D5 P4 P3 P2 P1 P0 A c kn D15 D14 D13 D12 D11 D10 D9 D8 A c kn D7 D6 D5 D4 D3 D2 D1 D0 A ck n

Device_out A6 A5 A4 A3 A2 A1 A0 W A c kn D7 D6 D5 P4 P3 P2 P1 P0 A c kn D15 D14 D13 D12 D11 D10 D9 D8 A c kn D7 D6 D5 D4 D3 D2 D1 D0 A ck n

If D15 = 0, the DACs are updated on the Latch pin.

If D15 = 1, all DACs are updated when the current DAC register is updated.

The entire DAC register D9−D0

is updated in this moment.

a. Write Single DAC

Write multiple DAC registers. P4−P0 specify start DAC address. Write Operation
Start Device Address Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn DAC (pointer) MSbyte. D14 must be 0. Ackn DAC (pointer) LSbyte Ackn DAC (pointer + 1) MSbyte. D14 must be 0.

SCL

SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn D15 D14 D13

Device_out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn D15 D14 D13

If D15 = 0, the DACs are updated on the Latch pin. The entire DAC register D9−D0
If D15 = 1, all DACs are updated when the current DAC register is updated. is updated in this moment.

Figure 9. Timing Diagram for Write DAC Register

DAC 20 (VCOM OUT2) MSbyte. D14 must be 0. Ackn DAC 20 LSbyte Ackn Stop

D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

b. Write Multiple DACs

D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

If D15 = 0, the DACs are uploaded on the Latch pin.

If D15 = 1, all the DACs are updated when the current DAC register is updated.
The entire DAC register D9−D0
is updated in this moment.

11
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
"#$%&%%
12
"#$%&%%

Read single DAC register. P4−P0 specifyDAC address. Read Operation

Start Device Address Write Ackn DAC address pointer. D7−D5 must be 000. Ackn Start Device Address Read Ackn DAC MSbyte. D15−D10 have no meaning. Ackn DACLSbyte. No Ackn Stop

SCL

SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0

Device_out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

a. Read Single DAC

Read multiple DAC registers. P4−P0 specify start DAC address. Read Operation
Start Device Address Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn Start Device Address Read Ackn DAC (pointer) MSbyte. D15−D10 have no meaning. Ackn

SCL

SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn

Device_out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn

DAC 20 (VCOM OUT2) MSbyte. D15−D10 have no meaning. Ackn DAC 20 LSbyte. No Ackn Stop

Figure 10. Timing Diagram for Read DAC Register

D15 D14 D13 D12 D11 D10 D9 D8 A c kn D7 D6 D5 D4 D3 D2 D1 D0

D15 D14 D13 D12 D11 D10 D9 D8 A c kn D7 D6 D5 D4 D3 D2 D1 D0 A ck n

b. Read Multiple DACs

[Link]
 "#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

REPLACEMENT OF TRADITIONAL GAMMA BUF20800 uses the most advanced high-voltage CMOS
BUFFER process available today, which allows it to be competitive
Traditional gamma buffers rely on a resistor string (often with traditional gamma buffers.
using expensive 0.1% resistors) to set the gamma This technique offers significant advantages:
voltages. During development, the optimization of these
gamma voltages can be time-consuming. Programming D It shortens development time significantly.
these gamma voltages with the BUF20800 can D It allows demonstration of various gamma curves to
significantly reduce the time required for gamma voltage LCD monitor makers by simply uploading a different
optimization. The final gamma values can be written into set of gamma values.
an external EEPROM to replace a traditional gamma D It allows simple adjustment of gamma curves during
buffer solution. During power-up of the LCD panel, the production to accommodate changes in the panel
timing controller reads the EEPROM and loads the values manufacturing process or end-customer require-
into the BUF20800 to generate the desired gamma ments.
voltages. Figure 11a shows the traditional resistor string;
Figure 11b shows the more efficient alternative method
D It decreases cost and space.
using the BUF20800.

a) Traditional b) BUF20800 Solution

BUFxx704
BUF20800
VCOM OUT1
VCOM

VCOM OUT2

Timing
Controller
OUT1
PC
SDA
Register

OUT2
SCL

Gamma
EEPROM References

OUT17

OUT18

SDA
Control Interface
SCL

LCD Panel Electronics

Figure 11. Replacement of the Traditional Gamma Buffer

13
"#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

PROGRAMMABLE VCOM REFH AND REFL INPUT RANGE

The VCOM channels of the BUF20800 can swing to 2V from Best performance and output swing range of the
the positive supply rail while sourcing 100mA and to 1V BUF20800 are achieved by applying REFH and REFL
above the negative rail while sinking 100mA (see Figure 4, voltages that are slightly below the power-supply
typical characteristic Output Voltage vs Output Current). voltages. Most specifications have been tested at
To store the gamma and the VCOM values, an external REFH = VS − 200mV and REFL = GND + 200mV. The
EEPROM is required. During power-up of the LCD panel, REFH internal buffer is designed to swing very closely to
the timing controller can then read the EEPROM and load VS and the REFL internal buffer to GND. However, there
the values into the BUF20800 to generate the desired is a finite limit on how close they can swing before
VCOM voltages, as illustrated in Figure 11 and Figure 12. saturating. To avoid saturation of the internal REFH and
The VCOM channels can be programmed independently REFL buffers, the REFH voltage should not be greater
from the gamma channels. than VS −100mV and REFL voltage should not be lower
than GND + 100mV. Figure 13 shows the swing capability
of the REFH and REFL buffers.
The other consideration when trying to maximize the
output swing capability of the gamma buffers is the
limitation in the swing range of output buffers (OUT1−18,
VCOM1, and VCOM2), which depends on the load current. A
typical load in the LCD application is 5−10mA. For
example, if OUT1 is sourcing 10mA, the swing is typically
limited to about VS − 200mV. The same applies to OUT18,
BUF20800 which typically limits at GND + 200mV when sinking
VCOM OUT1 10mA. An increase in output swing can only be achieved
VCOM for much lighter loads. For example, a 3mA load typically
VCOM OUT2
allows the swing to be increased to approximately VS −
100mV and GND + 100mV.

OUT1
Connecting REFH directly to VS and REFL directly to GND
does not damage the BUF20800. As discussed above
however, the output stages of the REFH and REFL buffers
Register

OUT2 will saturate. This condition is not desirable and can result
in a small error in the measured output voltages of
Gamma OUT1−18, VCOM1, and VCOM2. As described above, this
References method of connecting REFH and REL does not help to
maximize the output swing capability.
OUT17

18
OUT18
17

16
Output Voltage (V)

SDA
REFH OUT (sourcing), Code = 3FFh
Control Interface 15
VREFL = 1V, VREFH = 17.8V
SCL RLOAD Connected to GND

3
REFL OUT (sinking), Code = 000h
2 VREFL = 0.2V, VREFH = 17V
R LOAD Connected to 18V
1

0
0 10 20 30 40 50 60 70 80 90 100
Output Current (mA)

Figure 12. BUF20800 Used for Programmable Figure 13. Reference Buffer Output Voltage vs
VCOM Output Current

14
 "#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

CONFIGURATION FOR 20 GAMMA CHANNELS 15V

The VCOM outputs can be used as additional gamma 2V−5.5V 14.8V

references in order to achieve two additional gamma

channels (20 total). The VCOM outputs will behave the Digital Analog REFH

same as the OUT1−9 outputs when sourcing or sinking BUF20800

smaller currents (see the Typical Characteristics,

REFH OUT
Figure 4). The VCOM outputs are better able to swing to the 14.8V Source
Driver
positive rail than to the negative rail. Therefore, it is better
to use the VCOM outputs for higher reference voltages, as V CO M OUT1
GMA 1
shown in Figure 14.
V CO M OUT2
GMA 2

CONFIGURATION FOR 22 GAMMA

CHANNELS
In addition to the VCOM outputs, the REFH and REFL OUT OUT1
GMA 3
outputs can also be used as fixed gamma references. The
output voltage will be set by the REFH and REFL input
OUT2

DAC Registers

DAC Registers
voltages, respectively. Therefore, REFH OUT should be GMA 4

used for the highest voltage gamma reference, and REFL

OUT for the lowest voltage gamma reference. A
22-channel solution can be created by using all 18 outputs, 18 Gamma Channels

the two VCOM outputs, and both REFH/L OUT outputs for
gamma references—see Figure 15. However, the REFH
and REFL OUT buffers were designed to only drive light OUT17
GMA 19
loads on the order of 5−10mA. Driving capacitive loads is
not recommended with these buffers. In addition, the
REFH and REFL buffers must not be allowed to saturate OUT18
GMA 20
from sourcing/sinking too much current from REFH OUT
REFL OUT
or REFL OUT. Saturation of the REFH and REFL buffers SDA
0.2V

results in errors in the voltages of OUT1−18 and VCOM SCL Control IF

OUT1−2. The BUF01900 can be used to provide a
programmable VCOM output. LD A0 REFL

15V
0.2V

Figure 14. 20 Gamma Channel Solution −

Two VCOM Channels Used as
Additional Gamma Channels

15
"#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

18V
Reference buffer
17.8V and V COM OUT
2V−5.5V
outputs can be used
for extra gamma channels.

(REFH OUT
Digital Analog REFH will be a
fixed voltage.)
BUF20800

Source
REFH OUT Driver
17V
GMA 1

V COM OUT 1
GMA 2

V COM OUT 2
GMA 3

OUT1
GMA 4

OUT2
DAC Registers

DAC Registers

GMA 5

2 VCOM Channels plus

18 Output Channels

OUT17
GMA 20

OUT18
GMA 21

REFL OUT
0.2V
SDA GMA 22

SCL Control IF

Panel

LD A0 REFL
Output of reference
buffer can be used
for an extra fixed
gamma channel

18V
0.2V
V COM

18V
2V−5.5V

Digital Analog BIAS

BUF01900(1)
Voltage Regulato r
Program Command

4 x OTP Switch 10−Bit V COM

ROM Control DAC Buffer
V COM OUT

SDA

SCL Control IF

A0

NOTE: (1) Expected availability is Q4’ 06.

Figure 15. 22-Channel Gamma Solution

16
 "#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

DYNAMIC GAMMA CONTROL a picture is still being displayed. Because the data are only
Dynamic gamma control is a technique used to improve stored into the first register bank, the DAC output values
the picture quality in LCD TV applications. The brightness remain unchanged—the display is unaffected. During the
in each picture frame is analyzed and the gamma curves vertical sync period, the DAC outputs (and therefore, the
are adjusted on a frame-by-frame basis. The gamma gamma voltages) can be quickly updated either by using
curves are typically updated during the short vertical an additional control line connected to the LD pin, or
blanking period in the video signal. Figure 16 shows a through software—writing a ‘1’ in bit 15 of any DAC
block diagram using the BUF20800 for dynamic gamma register. For the details on the operation of the double
control and VCOM output. register input structure, see the Output Latch section.

The BUF20800 is ideally suited for rapidly changing the Example: Update all 18 gamma registers simultaneously
gamma curves because of its unique topology: via software.
D double register input structure to the DAC;
D fast serial interface; Step 1: Check if LD pin is placed in HIGH state.
D simultaneous updating of all DACs by software. See Step 2: Write DAC Registers 1−18 with bit 15 always ‘0’.
the Read/Write Operations to write to all registers and
Step 3: Write any DAC register a second time with identi-
the Output Latch sections.
cal data. Make sure that bit 15 is ‘1’. All DAC channels will
The double register input structure saves programming be updated simultaneously after receiving the last bit of
time by allowing updated DAC values to be pre-loaded into data. (Note: this step may be eliminated by setting bit 15
the first register bank. Storage of this data can occur while of DAC 18 to ‘1’ in the previous step.)

Histogram
SDA
Digital Gamma BUF20800
Picture Adjustment
Data Algorithm Gamma References
SCL
Black White 1 through 18
Timing Controller/µController
Source Driver Source Driver VCOM

Figure 16. Dynamic Gamma Control

17
"#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

TOTAL TI PANEL SOLUTION outputs, and other functions. The BUF20800, with its 20
In addition to the BUF20800 programmable voltage total programmable DAC channels, provides great
reference, TI offers a complete set of ICs for the LCD panel flexibility to the entire system by allowing the designer to
market, including gamma correction buffers, various change all these parameters via software.
power-supply solutions, and audio power solutions. See
Figure 17 for the total IC solution from TI. Figure 18 provides various ideas on how the BUF20800
can be used in applications. A micro-controller with
two-wire serial interface controls the various DACs of the
THE BUF20800 IN INDUSTRIAL BUF20800. The BUF20800 can be used for:
APPLICATIONS
The wide supply range, high output current, and very low D sensor excitation
cost make the BUF20800 attractive for a range of medium D programmable bias/reference voltages
accuracy industrial applications such as programmable
power supplies, multi-channel data-acquisition systems,
D variable power-supplies
data loggers, sensor excitation and linearization, D high-current voltage output
power-supply generation, and other uses. Each DAC D 4-20mA output
channel features 1LSB DNL and INL.
D set-point generators for control loops.
Many systems require different levels of biasing and power
supply for various components as well as sensor NOTE: The output voltages of the BUF20800 DACs will be set
excitation, control-loop set-points, voltage outputs, current to (VREFH − VREFL)/2 at power-up or reset.

Gamma Correction VCOM

BUF20800

TPS651xx 15V
2.7V−5V LCD 26V
Supply −14V

3.3V
TPA3005D2
TPA3008D2
Audio n n
Speaker
Driver Source Driver

Logic and
Timing
Controller
Gate Driver

High−Resolution
TFT−LCS Panel

Figure 17. TI LCD Solution

18
 "#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

+18V +5V

BUF2 0 8 0 0
Voltage 0.3V to 17V +5V
Output

High Current 2V to 16V, 100mA

Voltage Output
Sensor Excitation/Linearization

Control Loop
Set Point

4−20mA

+5V
Bias Voltage
4−20mA Generator
Generator
+2.5V Bias

LED Driver

Offset INA
Adjustment

Ref
+4V
+4.3V

Comparator
Threshold

Supply Voltage
Generator

Ref
Reference +7.5V
SDA SCL
for MDAC
MDAC

µC

Figure 18. Industrial Applications for the BUF20800

19
"#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

EVALUATION BOARD AND SOFTWARE Figure 19). Configurations can be quickly evaluated to
An evaluation board is available for the BUF20800. The determine optimal codes for a given application. Contact
evaluation board features easy-to-use software that your local TI representative for more information regarding
allows individual channel voltages to be set (see the evaluation board.

Figure 19. Evaluation Board

20
 "#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

GENERAL POWERPAD DESIGN 3. Additional vias may be placed anywhere along the
CONSIDERATIONS thermal plane outside of the thermal pad area. This
The BUF20800 is available in a thermally-enhanced helps dissipate the heat generated by the BUF20800
PowerPAD package. This package is constructed using a IC. These additional vias may be larger than the 13-mil
downset leadframe upon which the die is mounted, as diameter vias directly under the thermal pad. They can
shown in Figure 20(a) and Figure 20(b). This arrangement be larger because they are not in the thermal pad area
results in the lead frame being exposed as a thermal pad to be soldered; thus, wicking is not a problem.
on the underside of the package; see Figure 20(c). This 4. Connect all holes to the internal plane that is at the
thermal pad has direct thermal contact with the die; thus, same voltage potential as the GND pins.
excellent thermal performance is achieved by providing a
5. When connecting these holes to the internal plane, do
good thermal path away from the thermal pad.
not use the typical web or spoke via connection
The PowerPAD package allows for both assembly and methodology. Web connections have a high thermal
thermal management in one manufacturing operation. resistance connection that is useful for slowing the
During the surface-mount solder operation (when the heat transfer during soldering operations. This makes
leads are being soldered), the thermal pad must be the soldering of vias that have plane connections
soldered to a copper area underneath the package. easier. In this application, however, low thermal
Through the use of thermal paths within this copper area, resistance is desired for the most efficient heat
heat can be conducted away from the package into either transfer. Therefore, the holes under the BUF20800
a ground plane or other heat-dissipating device. PowerPAD package should make their connection to
Soldering the PowerPAD to the printed circuit board the internal plane with a complete connection around
(PCB) is always required, even with applications that the entire circumference of the plated-through hole.
have low power dissipation. This provides the
6. The top-side solder mask should leave the terminals
necessary thermal and mechanical connection between
of the package and the thermal pad area with its ten
the lead frame die pad and the PCB.
holes exposed. The bottom-side solder mask should
The PowerPAD must be connected to the most negative cover the holes of the thermal pad area. This masking
supply voltage on the device, GNDA and GNDD. prevents solder from being pulled away from the
1. Prepare the PCB with a top-side etch pattern. There thermal pad area during the reflow process.
should be etching for the leads as well as etch for the 7. Apply solder paste to the exposed thermal pad area
thermal pad. and all of the IC terminals.
2. Place recommended holes in the area of the thermal 8. With these preparatory steps in place, the BUF20800
pad. Ideal thermal land size and thermal via patterns IC is simply placed in position and run through the
(2x5) can be seen in the technical brief, PowerPAD solder reflow operation as any standard
Thermally-Enhanced Package (SLMA002), available surface-mount component. This preparation results in
for download at [Link]. These holes should be a properly installed part.
13 mils (0.330mm) in diameter. Keep them small, so
that solder wicking through the holes is not a problem
during reflow.

21
"#$%&%%
[Link]
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

DIE

Side View (a)

DIE

Thermal
End View (b) Pad

Bottom View (c)

The thermal pad is electrically isolated from all terminals in the package.

Figure 20. Views of Thermally-Enhanced DCP Package

For a given qJA, the maximum power dissipation is shown 6

in Figure 21, and is calculated by Equation 3:
Maximum Power Dissipation (W)

ǒ Ǔ
5
T MAX * T A
PD +
q JA (3)
4

3
Where:
2
PD = maximum power dissipation (W)
1
TMAX = absolute maximum junction temperature (125°C)

TA = free-ambient air temperature (°C) 0

−40 −20 0 20 40 60 80 100
qJA = qJC + qCA TA, Free−Air Temperature (_C)

qJC = thermal coefficient from junction-to-case (°C/W) Figure 21. Maximum Power Dissipation vs
Free-Air Temperature
qCA = thermal coefficient from case-to-ambient air (°C/W) (with PowerPAD soldered down)

22
 PACKAGE OPTION ADDENDUM

[Link] 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BUF20800AIDCPR ACTIVE HTSSOP DCP 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 95 BUF20800

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF BUF20800 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 10-Dec-2020

• Automotive: BUF20800-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BUF20800AIDCPR HTSSOP DCP 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 26-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BUF20800AIDCPR HTSSOP DCP 38 2000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DCP 38 PowerPAD TSSOP - 1.2 mm max height
4.4 x 9.7, 0.5 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224560/B

[Link]
 PACKAGE OUTLINE
DCP0038A SCALE 2.000
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C SEATING
AREA 36X 0.5 PLANE
38
1

2X
9.8
9
9.6
NOTE 3

19
20
0.27
38X
4.5 0.17
B
4.3 0.08 C A B

SEE DETAIL A
(0.15) TYP

2X 0.95 MAX
NOTE 5
19 20
2X 0.95 MAX
NOTE 5

0.25
GAGE PLANE 1.2 MAX
4.70 39
3.94
THERMAL
PAD 0.15
0.75
0 -8 0.50 0.05
DETAIL A
A 20

TYPICAL

1 38

2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

[Link]
 EXAMPLE BOARD LAYOUT
DCP0038A TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 9
METAL COVERED
(2.9) BY SOLDER MASK
SYMM
38X (1.5) SEE DETAILS
38X (0.3)
1
38

(R0.05) TYP

36X (0.5)

3X (1.2)

SYMM
39
(4.7) (9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD

( 0.2) TYP
VIA

19 20

(1.2)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4218816/A 10/2018
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 ([Link]/lit/slma002) and SLMA004 ([Link]/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

[Link]
 EXAMPLE STENCIL DESIGN
DCP0038A TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.9)
BASED ON
0.125 THICK
38X (1.5) STENCIL
METAL COVERED
38X (0.3) BY SOLDER MASK
1
38

(R0.05) TYP

36X (0.5)

(4.7)
SYMM 39 BASED ON
0.125 THICK
STENCIL

19 20

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.24 X 5.25
0.125 2.90 X 4.70 (SHOWN)
0.15 2.65 X 4.29
0.175 2.45 X 3.97

4218816/A 10/2018
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

[Link]
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