10 Memory Devices and PLDs

Syllabus
.oation of memories - ROM- ROM organization PROM- EPROM- EEPROM - EAPROM,
RAM- RAM organizatio. Write operation - Read operation-Memory cycle Timing wave-forms-
0ry decoding - Memory expansion- Static RAM cell - Bipolar RÁM cell - MOSFET RAM cell -

mamic RAM cellProgrammable logic devices Programmable Logic Array (PLA)

rammable Array Logic (PLA) - Field Programmable Gate Arrays (FPGA) - Implementation of

combinational logic
circuits using ROM, PLA, PAL

Contents

10.1 Introduction . Dec.-04, 05, 08, May-06, Marks 16

Classification of Memory .. May-06,07,09,12,

10.2
Marks 16
Dec.-05, 06, 12, 13,
10.3 ROM (Read Only Memoy)... May-03, 05, 06, 07, 09, 11,
. Dec.-03, 06, 07, 08 Marks 10

10.4 ROM Organization

. . Dec.-06, May-08 Marks 8
Memories, .. Dec.-03, 05, 06, 07, 08, 09, 12,
10.5 RAM (Random Access
. May-06, 09, 10, 12, Marks 16

. .Dec.-05, Marks 12
10.6 RAM Organization
. . Dec.-11, Markss8
10.7 DRAM Organization
May-08, 09, Dec.-08, 10, Marks 8
10.8 Memory Cycles and Timing Waveforms.... .
.

Dec.-03, 08, 12,

10.9 Memory Decoding
Marks 10
. .May-07, 12,
Marks 8
10.10 Memory Expansion . . May-10, 12, Dec.-12,
T0.11 Programmable Logic Devices (PLDS May-03, 05, 07, 09, 11, 13,
Marks 16
Dec.-03, 06, 09, 12,
12, 13,
10.12 Field Programmable Gate Arrays (FPGA). .
. . .
. May-06, 07, 08, 09, 10,
Marks 8
Dec.-04, 08, 10,

10.13 Two Marks Questions and Answers..

(10 1)
 10-2 Memory Devices and
Digital Electronics
PLDs
10.1 Introduction Dec.-04, 05, 08, May-06
Each register in the memory is on one storage
Memories are made up of registers.
location is identified by aan
location. Each memory
n

location also called memory

from a few in some memories to hund.
address.
The number of storage locations can vary ds of
thousand in others. Each location can
accommodate one or more bits. Generally, the
Ge

number of bits that a memory can store

is its capacity. Most
of the
types the capaci
is
Specified in terms of bytes (group of eight bits)
Each register consists of storage elements (tlip-flops or capacitors in semicondiset.
uctor
each of which stores one hi
memories and magnetic domain in magnetic storage), of
data. A storage element is called a cell.
The data stored in a memory by a process called writing and are retrieved from #h
10.1.1 illustrates in a very simplified way tho
memory by a process called reading. Fig.
for a generalized memory.
concept of write, read, address and storage capacity
Storage cells

Address Address

2 1 00 1000 2 1 0 0 0 Reading data

Writing data
3 3
4 4

n-1 n-1

(a) Write operation (b) Read operation

Fig. 10.1.1
As shown in the Fig. 10.1.1 a memory unit stores binary information in groups ot bits
as
called words. A word in memory is an
entity of bits that moves in and out of storage
a unit. A word having group of 8-bits is called a byte. Most computer memories Se

words that are multiples of eight bits in length. Thus, a 16-bit word contains two Dye
and a 32-bit word is made of 4-bytes.
n-data lines
The communication between a memory and
its environment is achieved through data lines,
address selection lines, and control lines that
the direction of transter. The Fig. 10.1.2 k-address
specify lines Memory
shows the block diagram of memory unit. unit

Then data lines provide the information to be 2 word

Read
stored in memory and the k address lines n-bit per word
Write

Fig. 10.1.2 Block diagram of memory

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10-3
Memory Devices and PLDs
f the particular wora chosen among the
many available. The two control
pecify the direction transfer.
specify fer. inputs
when there are k address lines we can
we can access 2
access 2 memory words. For exampie, "
k 10 =
1024
memory words.
lustrative Examples

le 10.1.1
Example 10.1.1 A bipolar RAM chip is
the chip ?
arranged as 16 words. How
many bits are stored n

Dec.-05, Marks 4
Solution 16 x 8 =128 bits one word =8 bits.
Example 10.1.2 How many address bits are needed to operate a 2K x 8 ROM?
Solution 2K memory locations 2048 1locations =

Since 2 2048, we need 1l address lines.

=

Example 10.1.3 How many locations are addressed using 18 address bits?
Dec.-08, Marks 2
Solution: The number of locations addressed 218 = 262144.

Review Questions

1. Define a memory cell. Give an

example. Dec-04, Marks 2
2. Definea 'memory location' and a 'cell'.
May-06, Marks 2
3 Write a descriptioe note on memories.
May-06, Marks 16
10.2 Classification of Memory May-06, 07, 09, 12, Dec.-05, 06, 12, 13
The Table 10.2.1 shows the classification of semiconductor memory devices. The
semiconductor memory devices can be categorized in several ways according to their
functional and architectural characteristics

Classification of semiconductor memories

Non-volatile memory Volatile memory

Read Only Memory Read/Write Memory Read/Write Memory
(ROM (NVRAM)
(RWM
Mask-Programmable
ROM
EPROM Random Access Non-Random AccesSs

Programmable ROM EEROM SRAM FIFO

FLASHH DRAM LIFO

Shitt Register

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 10-4
Memory Devices and PLDs
Digital Electronics

Note:
Read Only Memory
ROM
Programmable ROM
PROM
Erasable PROM
EPROM Electrically Erasable PROM
EEPROM Memory
Random
Access
SRAM Static
Memory
Access
Random
DRAM Dynamic
First-in First-out
FIFO
Last-in First-out
LIFO semiconductor
memories
Classification of
Table 10.2.1
memories and non-vol..

DOaraly semiconductor memories are

classified as volatile
as power is applied.
olatile
On
retain their state
as long the
a

C n o r i e s . Volatile memories can

hold data even if POwer 1s

turned off.
memories can
Other hand, non-volatile
allows both read and we
which rite
Nead/ Write Memories (RWMs) those memories,
are

where data has

to change continuously. Tho
operations. They are used in applications hey
memories alloW only read operationion.
are also used for temporary storage of data. ROM
the program.
programs and
constants used in
ney are used to store monitor
as power is ON are called
The volatile memories which can hold data as long
static RAMs (SRAMs). Dynamic RAMs (DRAMs) stores the data as a charge on the

the capacitor after every few

capacitor and they need refreshing of charge
on

milliseconds to hold the data even if power is ON.

erasable memories in which the stored
data can be erased
EPROM and EEPROM are

and new data can be stored.

The semiconductor memories are also classified as Bipolar and MOS memories

upon the type of transistors used to construct the individual cell.

depending

Review Questions

1. Given the classification of semiconductor memories. May-09, Dec.-12,13, Marks 16

2. Which memory is called volatile ? Why? Dec.-05, Marks 2
3 What is meant by 'static and 'dynamic' memories? May-06, Marks 2
4 Explain static memory. Dec.-06, May-07, Marks 2
5. Disgasy the classification of ROM and RAM memories. May 12,Marks 8
10.3 ROM (Read Only Memory) May-03/05, 06 07, 09 11, Dec03,06, 07,05
hold
We can't write data in read only memories. It is non-volatile memory i.e. it can
ary codes or
data even if power is urned off. Generally, ROM is used to store the binar
ictions you want the computer to carry out and data Such as loo
the sequence of instruct
this
type of information does not chanee.
up tables. This is because
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E l e c t r o n i c s

- 5
Memory Devices and PLDs
is importan1 tant to note that although we
give the name RAM
static and dynamic
to
ad/write
memory devices, that does not
mean that the ROMs
random access devi
vices. In that we are using are
fact, most ROMs are accessed randomly with ique
unig
also

a d d r e s s e s .

Bit line
The Fig. 10.3.1 shows the Vcc
configuration of a ROM R
cal
b y p i c a l

of a transistor T w-
I t consists
cell.
and witch P. The transistor T is Word line
driven by line. The the word
of cell can be read from
ontent

word line is logic 1.

the cell when T Open Data stored (logic 1)
value 0 is read if the Close Data stored (logic 0)
A ogic
transisto is connected to ground
switch P. If switch P is
through Fig. 10.3.1 ROM cell
a
read. The
logic value 1 is
open,
bit line is connected through a resistor to the power :
Supply. A sense circuit at the end of
hit line generates the proper output value. Data is stored into a ROM when it is
the
manufactured.

There are four types of ROM : Masked ROM, PROM, EPROM and EEPROM or
EPROM.

10.3.1 PROM (Programmable Read Only Memory)

PROMs are programmed by
user. To provide the VpD
programming facility, each
address select and data line Address select line

intersection has its own fused

MOSFET or transistor. When
MOSFET
the fuse is intact, the memory switch
cell is configured as a logic 1 -Data line

and when fuse is blown

(opern
Circuit), the memory cell is
logical 0. Logical 0s are
Fuse
PrOgrammed by selecting the Output bit
appropriate select line and then
Ving the vertical data line
with a
pulse of high current.
he
Fig. 10.3.2 shows a PROM Fig. 10.3.2 Single fused PROM cell
Tused MOSFET memory cel.

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 Memory
Devices and PLDs

Digital Electronics 10-6

therefore, the
bit position;
diodes in every
PROM. It
has in series wi
with it. By
ig. 10.3.3 shows four byte f u s i b l e link
has a
however
output, we can
n
output is initially all Os. Each diode,
at the
correspondin8

current pulse material 1like

addressing bit and applying proper
position.
The fuse uses

out tho
blow out 1 at that bit
20 to
to pasS around
the fuse,storing
storing logica the fuse it is
logic necessary

nichrome and polycrystalline. Forblowing according

to the truth
fuses
f
The blowing
50 mA of current for
period 5 to 20us. PROMs with special PROM
program
1s callod
d l e is
can
to the bit
programming of ROM. The
user
table Ccalled
burns the
fuses according

programmer. The PROM programmer selectively of PROM. Ihe PROMs

known as burning o *
Patem to be stored. This is also
process
the information
stored is permanent.
proerammed,
programmable. Once
o+Vcc

Fuse link-

Ap A

2:4 K
Decoder
A
ÄA
OE
Output enable
Do D D2 D3 D4 D5 De D7
Fig. 10.3.3 Four byte PROM

10.3.2 EPROM ( Erasable Programmable Read Only Memory)

Erasable programmable ROMs use MOOS Quartz window

Ultraviolet light
circuitry. They store ls and 0s as a packet
of charge in a buried layer of the IC chip.
EPROMs
with a
can

special EPROM
be programmed by the
programmer. The
user

the
m
important point is that we can erase

stored data in the EPROMs by exposing

the chip to ultraviolet light through its

15 to 20 minutes,
quartz window for
as
Fig. 10.3.4 EPROM
10.3.4.
shown in the Fig.

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10-7 Memory Devices and PLDs

I+ is not possible to erase selective information, when erased the entire information is

lost.
chip can be reprogrammed. This memory is ideally suitable for product
The
relopment, expermental projects and college laboratories, since this chip can DE
many
tim
mes, over.
reus

EPROM Programming
When erased each cell in the EPROM contains 1. Data is introduced by selectively
ramming 0's into the desired bit locations. Although only 0's will be
hoth 1's and O's can be presented in the data.
programmed
During programming address and data are applied to address and data pins of the
PROM. When the address and data are stable, program pulse is applied to the prOgram
anut of the EPROM. The program
inpu pulse duration is around 50 ms and its amplitude
Hepends on EPROM IC. It is typically 5.5 V to 25 V. In EPROM, it is possible to
location at any time either individually, sequentially, or at random.
program any

10.3.3 EEPROM (Electrically Erasable Programmable Read Only Memory)

Electrically erasable programmable ROMs also use MOS circuitry very similar to that
of EPROM. Data is stored as charge or no charge on an insulated layer or an insulated

floating gate in the device. The insulating layer is made very thin (< 200 A). Therefore, a

voltage as low as 20 to 25V can be used to move charges across the thin barrier in either
direction for programming or erasing. EEPROM allows selective
erasing at the register
level rather than erasing all the information since the information can be
changed by
using electrical signals. The EEPROM memory also has a erase mode special chip by
which entire chip can be erased in 10 This time is
ms.
quite small as compared to time
required to erase EPROM and it can be erased and reprogrammed with device right in
the circuit. However, EEPROMs are most expensive and the least dense ROMs.

Review Questions

1. Write note on ROM technologies.

2. Give the features
of a ROM cell.
.
Briefly explain any four nonvolatile memory in detail.
4. Write a note on ROM.
5. Explain EPROM.
Dec.-03, Marks 4
6. Write a note on EPROM.
May-03, 05, 09, Marks 4
Mention the two types of erasable PROM.
Dec-06, Marks 2
1ow is individual location in EEPROM
programed or erased?
a
May-06, Marks 2
Elaborate the single fused PROM cell with clear sketch.
Dec.-06,Marks 6
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 Memory Devices and
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May-07, Marks 2
0. Write the
adoantages of LPROM 0 OM '

devn Why? May-07, Marks 2

1.Whether
12.
ROM lassifird as nonolalir
s
Dec.-07, Marks
Wnle a note 01 tupe of ROM*
the ues for
cach tye. Dec-08, Marks 10
and gur
.Npuin
14
the l o ROM rgani:atons May-09, Marks
Wil notr o |1PROA1
a

f u rplam he 1PROM and 1LPROM Ie hnos

May-11, Marke
Dec 06, Ma03
10.4 ROM Organization
we will the simple
(ROM. Fix. 10.4.1 shows
a very Simple
tour byte d
st, see
decoder. As
shown in the Fig. t.
ode ROM consists of onl diodes and a

decoder and of the iused to select one

"datesslines
Ag and A, are decoded by 2: 4
the selected row, F
decoder active low, it places
a logic U on
SAs
output is
the output data column to t
Ouput data line goes to logic 0 if a diode connects
Selected row. Data is available on the output data lines only when output enable (
at four locations.
Signal is low. Table 10.4.1 shows the contents of ROM
cc

R R RS R

00

01
2.4

Decoder 10

11

Oulpul enable
Do D D D

Data Output
Fig. 10.4.1 Simple four byte diode ROM
Now days ROMs use MOS
technology instead ot diode. Fig 104. Sh
nibble (hall-byte) ROM
using MOS transistors. 1
Here, diodes and pull up res
r e s i s t o r s

replac ed by MOS tran51stors. The address on the decn

address lines (Ag and A i1)s
by 2 4 decoder. Decoder
the four rows Selects one of
T e n t r

cOnnected at the output decoder inverts the

making it logic 0. T
state of selected row
Thercfore, cach output data line goes to (1.e
logic 0 if a gate of MOS transistor
Stor i s connect
is c
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Memory Devices and PLDs
select lin
lines.
S e l e c t
hen gate of

connected
rOW

(o transistor is tol
S
Address
M O S

the
row, MOS transistoAddress Binary Data Data in Hex
selected
sele

the
turned
on. This pulls the D D, D, D, D, D, D, D,
s onding column ata line to O0 10 100 10 1 A
ogic0
01
circuits, a thin|
0 1 0 10 0 0 1 51
In integrated

metallizec layer connects the gates 10 0 1 0 46

0 0 1 1 0
transistors to the row
ofsome Table 10.4.1 Contents of ROM
t t lines.
The gate Connections
selec

oS transistors depernd on the data to be stored in the ROM. Therefore, accordirng to

1ser truth table, manufacturer can deposit thin layer of metal to connect gates of the
the user truth

sistors. On
transistors. nce
the pattern/mask is decided, it is possible to make thousands of such
pOMs. Such ROMs are called Mask-programmed ROMs. Masked ROMs are used in
microprocessor based
ba tóys, TV games, home computers and other ch high volume
consumer products.

NcC
00
Ao
2:4
01
Decoder
10-
A
11

OE
Output enable o-

Do D D2 D3
Fig. 10.4.2 Simple four half-byte ROM
Review Questions

Describe the typical ROM internal organization with necessary diagram.

Dec06 Malo
llustrate the concept of 16 x 8-bit ROM arrangement with diagram.
Dec06Maks 18
S.
Design a 16-bit ROM array and explain the operation. May-08, Marks 8

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 Memory Devices and
10- 10 PLD
Digital Electronics Dec.-03, 05, 06, 07, 08
Memories) May-06, 09, 10, 12
10.5 RAM (Random Access

There ae wo types of RAMs

Stahc RAM
ynami RAM

105.1 Statlc RAM (SRAM) their state as long as De

as long,as
povter
circuits capabte of
retaining
memory-(RAM.
i
Memories that consists of accesS

memories.hese
are
random
and
are known as static
PPed
hence combinely called static RAM memóries.

10.5.1.1 Static RAM Cll

The Fig 10.5.1 shows the
implementation of static RAM cell. T2
It consists of two cross-coupled
inverters as a latch
transistors Ti and T2 which act as
a switches.
and two
G
Word lire
The latch is connected to two
bit lines by transistors T and T2. Bit lines

The word line controls the opening Fig. 10.5.1 Static RAM Cell

and closing of transistors T1 and

T2. When word line is at logic 0 level (Ground level), the transistors are off and te
latch retains its state.

Read operation
For read operation, word line is made logic 1 (high) so that both transistors are 0x
Now if the cell is in state 1, the signal on bit line b is high and the signal on bit line t
is low. The opposite is true if the cell is in state 0. The b and
b' are complements of
e
other. The sense/write circuits connected to the bit lines monitor the states ot b anu *
and set the output accordingly.
Write operation
For write operation, the state to be set is placed on the line b and its
placed on line b and then the word line comple
is activated. This the
action forces the cell n
corresponding State and write
operation is completed.

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10-11
Bipolar RAM Cell Memory Devices and PLDs
0.5.1.2
Fig 10.5.2 shows
simplitied schematic of
VcC
a
bipolar memory cell. The
memory cell is jmplemented
R R2
using TT(Transistor
Transistor-Logic) multiple
emitter technology. It stores
1-bit of information. It is

nothing but a
flip-flop.
It Set
Reset
an store either 0 or 1 as
long as power is applied
and it can set or reset to

store either 1 or select line o-

-o Y select line
respectively.
Fig. 10.5.2 TTL RAM ll
Operation: The X select
and Y select input ines select cell from matrix. Thea
Q1 and Q2 are cross couplea
inverters, hence one is always OFF while the other is ON. A "1" is stored in the cell if
Q is conducting and Q2 is OFF. A "0" is stored in the cell if Q2 is conducting and
0, is OFF. The state of the cell is changed to a "0" by pulsing a HIGH on the Q1 (SE
emitter. This turns OFF Q1. When Q1 is turned OFF, Q2 is turned ON. As long as 2
is ON, its collector is LOW and O is held OFF. A 1can be rewritten by pulsing the
Q2(reset) emitter igh.
10.5.1.3 MOSFET RAM Cell X Row select
Fig 10.5.3 shows a

simplified schematic of MOS

static RAM cell.
Enhancement mode MOSFET
transistors are used to make
this RAM cell. It is very Data Lo Data
line 6 ine
similar to TTL cell discussed
earlier.
Here, T and T2 form the
basic cross coupled inverters
and T3 and T4 act as load
resistors for T1 and T2. X Write(W) Read(R)
and Y lines are used for
T
addressing the cell. When XX o- Y Column select 10
and Y both are high, cell is Data-in
selected. When X = 1, T5 and Fig. 10.5.3 MOS static RAM celI
68et ON and the cell is connected to the data and data line. When Y = 1, Tz n T

are made ON. Due to this, either read or write operation is possible.

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 10 - 12 Memory Devices and
and pPLDs
Digital ElectronicS
W signal

W e operation : Write operation

can be
ble
enabied

I, nOae
by making
D 1s also logic 1 T
at
high. With
signal is logic
e operation enabled, if data-in
data-in pin
is lOgiC 0, l2 will1 be ccut-off
ut.

new data on and ,

N
2 and T, is cut-off. If
will be turned ON.
be enabled by making R signal high
lline to read
can
ad operation : Read operation
connects the data output (Data the
ON. This
p e r a t i o n enabled, T1a becomes
in the cell Is available at th
the
aata out and thus the complement
of the bit stored output
10.5.2 Dynamic RAM (DRAM)
Sense line
10.5.2.1 Dynamic RAM Cell
on
Dynamic RAM stores the data as charge a

RAM
the capacitor. Fig. 10.5.4 shows the dynamic
cell. A dynamic RAM contains thousands of such
Storage
ROW
capacitor
memorv cells. When COLUMN (Sense) and
(Control) lines go high, the MOSFET conducts Control-
line
and charges the capacitor. When the COLUMN
and ROW lines go low, the MOSFET opens and Fig. 10.5.4 Dynamic RAM
the capacitor retains its charge. In this way, it
stores 1 bit. Since only a single MOSFET 'and capacitor are needed, the dynamic RAM
contains more premory cells as compared to static RAM per unit area. .

The
disdvagtage of dynamic RAM is that it needs
refreshing of charge on_the
capacit after every few milliseconds. This complicates the system design, since i
requis the extta hardware to control refreshing of dynamic RAMs.

15.2.2 Comparison between SRAM and DRAM

Sr. Static RAM Dynamic RAM
No.
Static RAM Ccontains lesS
memory cells per Dynamic RAM contains more memory eis
unit area.
as
compared to static RAM per umt are
It has less access time
hence laster Its access time is
memories. greater than static RAN
Static RAM Consists of number of
Each flip-ilop stores one bit. flip-flops. Dynamic RAM stores the data s c h a r g
0n the capacitor. It consists af MOSFET O
the
4
capacitor lor each cell.
Refreshing circuitry 15 nol
required. Refreshing circuitry is req Ao maunta
the charge on the capaparitors aftet every t
milliseconds. Extra hardware is r des
Control refreshing, This makes syste
Cost is more.
COmplicated.
Cost is less.
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Memory Devices and PLDs
Review Q u e s t i o n s

1 Draw a RAM cell and

explain its working.
2 Draw the basic aynamic memory cell. Dec.-03, Marks 6
3. Write a note on dynamic RAM cell Dec.05, Marks 2
What is RAM ?
Dec.-05, Marks 8
4
Draz Dec.-06, Marko 2
a dynamic RAM cell and
explain its operation. Compare its simplicity with that of NMO
shatic RAM cell, by way of diagram and operation.
May-06, Marks 16
6. Draw the logic diagram of a memory cell.
Dec-07,Marks 2
7. Draw the block diagram of dynamic RAM cell.
Dec.08, Marks 2
s. Compare static RAMs and dynamic RAMs.
May-09, 12, Dec.-09, Marks 8
What are the advantages of static RAM compared to dynamic RAM?
May-10, Marks 2
10. Explain the principle of operation of bipolar SRAM cell.
May-10, Marks 8
11. Draw and explain the MOSFET RAM cell

12. Draw the logic diagram of static RAM cell and bipolar RAM cell. Dec.-12, Marks 10

10.6 RAM Organization X) Dec-05

RAM memory celIs are Memory cell 8191
organized in the form of Memory cell 8064

an array, in which each 63

Data in
cell is capable of storing 62
one-bit of information. 61
The Fig. 10.6.1 shows the
row and the column

organization of a 8192-bit
Data
memory chip. out
The chip has 13
1
address lines. The first
seven address lines are
Memory cell 0
Connected to the column Memory cell 127
127 126 125 124 2 1 0
decoder to indicate one of
7 to 128 Line decoder
the 128 columns. The
remaining 6 address lines
are connected to the row As As As Ap A A
8192-bit static
decoder to indicate one of column organization for
Fig. 10.6.1 Row and
64 RAM
rows. Where the
aecoded row and column

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Digital Electronics 10- 14 Memory Devices and PLD

cross, they select the desired individual memory

cell. Simple arithmetic
shows that the
has 8192 memory cells.
are 64x 128=8192, crossings. Therefore, this memory

Review Question

1. Describe the RAM organization. Dec-05, Marks12

10.7 DRAM Organization Dec-11
The Fig. 10.7.1 shows the two dinmensional address decoding scheme of typira
DRAM. The DRAM shown in Fig. 10.7.1 is 16 M-bit DRAM. It is configured as 2M x R

The cells are organized in the form of a 4Kx 4K array. The 4096 cells in each row
are
addressed by 12 address bits and are divided in 512 groups of 8, so that a row can store
512x8, i.e. 512 bytes of data. Another 9 bits are used to specify a group of 8 bits in the
selected row. Thus, a 21-bit address identifies a byte in this memory.
RAS

A20-Ag 4096 x (512 x 8)

(row address Row
address Row cell array
latch decoder

A20 Ap
Sense/ write
circuits

Column
address
latch
Column
Ag Ao decoder
(column address)
CAS
Do
Fig. 10.7.1 (a) Internal organization of a 2M x 8 dynamic memory chip
Fig. 10.7.1 (b) shows another
typical DRAM
memory organisation. It is contigue
2M 4. In DRAMs address and column
row
address lines are edue
number of pins. Thus for a
given multiplexed tO
memory DRAM chip has less address
pl thand
a
SRAM chip. The elements of
vertical (column) lines. Each memory array are connected by both horizontal
horizontal line (row cell in
its connects to the select
row each vertical line connects to
the Data-ln/
terminal ot eac
column. sense terminal of each ce"

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10-15 Memory Devices and PLDs
The DRAM organisation
shown in
Fig. 10.7.1 (b) has four arrays of 2048 by 2040
laments. The 11 address lines are
required to select one of 2048 rows. These 11 lines are
fpd
fed into a row decoder, which has 1l lines
of input and 2048 lines for
the decoder activates a
single one of the 2048
output. The logIC
outputs depending on the bit pattern
the 11 input lines (2" =2048).

n additional
11 address lines select
one of 2048 columns of four bits
Four data lines are used for the input and output of four bits to and from a data columl
per butfer.

RAS CAS W
OE
iming and control

Refresh
counter

MUX
Row
Row decoder
Memory array
address (2048x2048x4)
buffer

Data input
Sense amplifier buffer
Column and l/O gate
address Data output
buffer buffer
Column decoder

10.7.1 (b) DRAM organization

Fig.

Review Questions

Explain the DRAM organization of 2M x 8 memory chip.

DRAM in detail.
Describe the tuwo dimensional
address decoding scheme of typical
Dec. 11, Marks 8

and Timing Waveforms May-08, 09, Dec.-08, 10

10.8 Memory Cycles
cycle with their timing parameters.
Let us
study read and write memory

Read Cycle the

is drawn on
for static RAM. The timing diagram
F1g. 10.8.1 shows the read cycle
Dasis of different timing parameters.
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10 25
Memory Devices and PLDs
Solution

Do
D7

(ROM) (ROM)
32 x 8
32 x 8
(ROM) (ROM)
32 x 8
328
CS OE| CS OEE CS OE CS OE
RD

2x4 1
Decoder 2

Fig. 10.10.4
Review Question

1. What is meant by memory expansion? Mention its limit.

May-10, 12, Dec.-12, Marks 2
10.11Pregrammable Logic Devices (PLDs) May-03. 05, 07, 09. 11, 13,
Dec.-03, 06. 09, 12
So far have discussed various
we
digital ICs for performing basic digital operations
and other functions, such as adders,
comparators, arithnmetic logic unit,
demultiplexers, code converters, shift registers, counters etc. These ICs, duemultiplexers,
to their fix
function known as fixed function
are 1Cs. These ICs are
designed by their
manufacturers and produced in large
quantities to satisfy the needs of a wide variety of
applications.
We have seen the
design of digital circuits using fixed function ICs. There are two
more
approaches for the design of digital circuits.
Use of
Application Specific Integrated Circuits (ASICs)
Use of
Programmable Logic Devices (PLDs)
nthe fixed function IC approach, we have to use various tixed tunction Cs to
piement different functional blocks in the digital circuit. On the other hand, in ASIC,
e TC is designed and manufactured to implement the entire circuit. In the third

advantProgrammable logic devices are used to implement logic tunctions. The main
a g e of PLD approach is that PLDs can be easily configurable by the indiv iiual
ser
thrSpecific
three design applications. The Table 10.11.I shows the comparison betwen these
approaches.
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 10- 26 Devicos 5na Pip
Digital E l o c t r o n i c s

Fixed-function IC
ASIC approach PLD approach
Comparison approach

parameter High Low

Low
Development cost Minimum Less
Large
Space required Less Less
Large
Power required
to
other
Highest High
Less compared
Reliability two approaches.

Specialized testing Easy

Easy methods are required
Circuit testing with may
increase cost
and etfort.

No More
Less
Design flexibility May be
Possible with change
in
No possible without
any circuit or
changes butcomponent
Modification in design circuit and/or with
change in components.
only by
recontigurating
device.
the

Lack ofsecurity i.e.

High High
Design security can easily be
circuit
copied by others.

Less
More Less
Design time
approaches
Table 10.11.1 Comparison between design
flexibilihu
seconds and hence giIves more
PLDs can be reprogrammed in few
feature ot PLDs also make it possible acent
experiment with designs. Reprogramming
circuits. These two main advantages and
changes/modifications in the previously design
PLDs very popular in digital design.
others discussed in Table 10.11.1 make

to architecture, complexity and flexibility in programming PLDs are

According
classified as
PROMs: Programmable Read Only Memories

PLAs : Programmable Logic Arrays

PAL :ProgrammableArray Logic
FPGAs Field Programmable Gate Arrays
CPLDs Complex Programmable Logic Devices

10.11.1 PROM (Programmable Read Only Memory)

The 10.11.1 shows the block diagram
Fig.
n
of PROM. It consists of n-input lines and address 2 2 m m data

m-output lines. Each bit combination of the lines

PROM lines

input variables is called an address. Each bit Dm

An-1
combination that comes out of the output Fig. 10.11.1

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Digital Electronics
10 27
Memory Devices and PLDs
liaps is called
word. Ihe number of
a
bits per word is
lines, m. The address Specified in equal
the number of output
to
binary number denotes one of the minterms or
variables. The number of distinct addresses possible with n-inpu
nput variables is 2". An
output word can be selected by
unique address and since there are 2
a
osses in PROM, there
2" distinct are
words in the PROM. The word available
ut lines at any given time
outpu depends the address value applied to the
on
o
input lines.
Let us consider 6 x PROM. The PROM
consists of 64 words of 4-bits each. nis
means that there are four
output lines and particular word fronom 64 words presently
available on the
output lines is determined from the six input lines. There are only six
ts in a 64 x 4 PROM because
inputs 2 64 and with six =

variables, we can sPeciy

addresses
ad or minterms. For each address input, there is a unique selected word. Thus, IT
the input address is O00000, word number 0 is selected and applied to the output lines.
Tf the input address is 111111, word number 63 is selected and applied to the output
lines.
The Fig. 10.11.2 shows the internal
logic construction of a 64 x 4 PROM. The six input
variables are decoded in 64 lines by means of 64 AND gates and 6 inverters. Each
output of the decoder represents one of the minterms of a function of six variables. Ihe
64 outputs of the decoder are connected through fuses to each OR gate. Only four ot
these fuses are shown in the diagram, but actually each OR gate has 64 inputs and each
input goes through a fuse that can be blown as desired.

Ap 0

A
2
6:64
Decoder

As 63

64 x 4 256 Fusess

F F2 Fa
10.11.2 Logic construction of 64x 4 PROM
Fig.
e PROM is a two level implementation in sum ot mnteriis torm. Let us see
10.11.3 shows the
D-OR implementation ot PROM. Fig
and AND-OR-INVERTER
X2 PROM with AND-OR and AND-OR-INVERTER implementations.

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10-21 Mamory D6vi4s ud D

Address input
A

Mintonms

01
AND
matrix 10

8 Fuse6
OR
matri

F1 2

Fig. 10.11.3 (a) 4x 2 PROM with AND-OR gates

A1 Ap

00

AND 10
matrix

D!
OR
matrix

F F2
Fig. 10.11.3 (b) 4x 2 PROM with AND-OR-INVERTER gates

IM

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 mples for Practice
Memory Devices and
PLDs
Example 1 0 . 1 1 . 8
Design switchimg
a

Gray code circuit that

using ROM converts a 4 bit
array. binaryy code into a 4 bit
41.9 Des
Example 10.11.9
Design a 3-bit
gray to
binary code converter
Examp
ple 10.11.10 Implement binary to
using suitable ROM.
Gray code converter using PROM devices.
10.11.2 (Programmable Logic Array) Dec-12, Marks 8
mbinational
The c o m b i n circuit do not use all the
Jon't conditions. Don't care conditionminterms every time.
have don' care Occasionally, they
when implemented with a
address input
hecomes an ad that will never occur. PROM
The result is that not all the
ale in the PROM are used, bit patternsS
available
which may be considered a waste of available
equipment.

Cor cases where the number of

don't care conditions is
excessive, it is more
ronomical to use a
type second
of LSI component called a Programmable Logic Array
PLA). A PLA is similar to a PROM in concept; however it does not provide full
decoding of the variables and does not generates all the minterms as in the PROM. The
PLA replaces decoder by group of AND gates, each of which can be programmed to
enerate a product term of the input variables. In PLA, both AND and have
ER gates
huses at the inputs, therefore in PLA both AND and OR gates are programmable.
buffer with
10.11.20 shows the block diagram of PLA. It consists of n-inputs, output
Fig.
and buffers. The product terms
m outputs, m product terms, m sum terms, input output
terms constitute a group of m OR
Constitute a group of m AND gates and the sum
their complement
inserted between all n-inputs and
gates, called OR matrix. Fuses are
between the outputs ot the-
are also provided
alues to each of the AND gates. Fuses
the output inverters
the OR gates. The third set of fuses in
ND gates and the inputs of form or in the
generated either in the AND-OR
the output function to be AND-OE
S link we get
When inverter is bypassed by be
O I N V E R T form. inverter link has to
AND-OR-INVERTER
implementation
PEmentation. To get
disconnected.
Po S m
Flip-flops outputs
InverU output
1 OR
n
I AND non-invert
buffer
inputs Input matrix
matrix
matrix
buffer
m-1

n-1 Pm
n-1
OE
(DUutput enable) diagram
of a PLA
Block
10.11.20
Fig. for
knowledge

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 10-40
Digital Electronics Memory Devices an
10.11.2.1 Iinput Buffer

are provided in the

buffers (a)
Input that
loading of the sources

PLA to limit
also provide
drive the inputs. They
non-inverted form of
inverted and
10.11.21
inputs at its output. The Fig. (b)
shows two ways of representing input Fig. 10.11.21 Input buffer for single s
buffer for single input.
ingle input ine

S%O
10.11.2.2 Output Buffer
is S
The driving capacity of PLA
at the
increased by providing buffers

output. They are usually TTL SN-1 N-1

10.11.22 shows the
compatible The Fig. OE
buffer.
tri-state,TT compatible output Fig. 10.11.22 Output buffers
The output buffer may provide
open collector or
totem-pole,
tri-state output. So D

10.11.2.3 Output through Flip-Flops

For the implementation of S
sequential circuits we need memory

elements, flip-flops and

combinational circuitry for deriving
the flip-flop inputs. To satisfy both
the needs some PLAs are provided
SN-1 D
with flip-flop at each output, as
shown in the Fig. 10.11.23.

Clock
Output enable (OE)
the outpur
Fig. 10.11.23 PLA with flip-flop at

10.11.2.4 Implementation of Combination Logic Circuit using PLA Wiath

Like ROM, PLA be

can
mask-programmable or
field-progranmhHe table to

mask-programmable PLA, the user must submit a PLA progta LA thatha

manufacturer. This table is used by the vendor to produce a availabte

required internal paths between inputs user-ma PLA

ava
and outputs. A second type of
ype

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D i g i t a l
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10-41 PLDS
Memory Devices and
called. field-programniadie
field-programmable logi
logic array or FPLA. The FPLA can be grammed by the
by
e r
recommended neans of certain
programmed by u
procedures. FPLAs can be prrogrammed with
ercially ailable programmer runits.
Commercially

As mentione med earlier, user has

to submit PLA program table
get the
cor-made PLA. Let us study how to determine
to the
manufacturers
PLA program table with the
help of example.

Examples for Understanding

Example 10.11.10 A combinational circuit is defined by the function-

F m (3, 5, 7), F =
Z m (4, 5, 7)
Inlement the circuit with a PLA having 3 inputs, 3 product terms and two outputf.

Solution:

Simplify the given Boolean functions

p 1
For F For F2
BC BC
A 00 01 11 10 A 00 01 1 1 10

o o o 10 o 0 0

F1 AC+ BC Fa AB+AC
Fig. 10.11.24

The Boolean functions are simplified, as shown in the Fig. 10.11.21. The simplitied
obtained from the maps are
functions in sum of products are

F = AC + BC, F2 AB+AC
=

Step 2: Write PLA program table

Product term Inputs Outputs

A BC F E
1
AC
11
BC 2

AB
TT T/C
table
Table 10.11.4 PLA program
nd hwo sum
terms : AC, BC and AB,
Erore, there are three distinct product columns
consists ot three
10.114
terms ePLA program table shown in Table
product
gives the lists of
first column
itying product terms, inputs outputs. The and and
the required paths
between inputs
err
nerically. The second column specifies

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between the AND

the required paths
AND gates. The third
column specifies
write a T (for true)
if the Outles gates and
variable, w e
to be comblo
output inverter
the OR gates. Under each output
1S to be bypassed, and
C (for
complement)
the f u n c t i o n is
if
the left of first column
lemented with
are not
are
terms
listed on the
the output inverter.
The product r e t e r e n c e only.
pan
included for
are
or PLA program table they

Step 3 Implementation
A B B CC

A
3 Product terms

AC

BC

AB

2 Sum
terms

F F2
Fig. 10.11.25

Draw a PLA circuit to implement the logic functions

Example 10.11.11 Dec.-08, Marke 6
ABC + ABC+ AC and ABC + BC.

Solution
functions
Step 1 Simplify the Boolean
ABC+ A BC + AC = ABC A (BC + C)
=ABC + A (B + C) A + AB =A+

=ABC + AB +AC
The second Boolean function is in simplified form.
Note

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