SOI FinFET

Application Example
GTS Framework Release 2022.03

Demonstrates a basic simulation flow on the basis of an

SOI FinFET. Drift Diffusion and Density Gradient simula-
tions of IV, CV curves and Gate leakage analysis have
been performed.
About this Application Example
This application example was created using GTS Framework in the release specified below.
This is an advanced (level 3) example.
Complementing this document, the respective input data and results are provided by GTS as
GTS project files, which you can open in GTS Framework (specified release recommended).
You are welcome to use the project while you are reading this.

Obtaining the GTS Project Files

All GTS examples and tutorials are provided at [Link]

where you can download the PDF documents or the full project data (ZIP files) via MyGTS.
Read more about MyGTS at [Link]

Opening the Project

Please download the ZIP file and extract it to the GTS Projects folder on your PC – typically
~/gts/Projects (Linux) or Documents/gts/Projects (Windows). Restart GTS Frame-
work, then the example will appear in the Projects list, highlighted yellow. Click Create working
copy, which creates a regular project that you can edit as you prefer. (If not yet familiar with
GTS Framework, please refer to the GettingStarted_I tutorial available at the same location.)

SOI FinFET – Application Example,

Revision of September 17, 2024.
Created using GTS Framework Release 2022.03

Global TCAD Solutions GmbH

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Austria / Europe
Phone: +43 1 9255049
Email: info@[Link]

Additional information is provided at [Link]

© Global TCAD Solutions GmbH, Vienna 2008 – 2024

Cover & layout: prausedesign

Oracle and Java are registered trademarks of Oracle and/or its affiliates. Windows is a registered trademark of Microsoft
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GTS APPLICATION EXAMPLE SOI FinFET

Overview
This example demonstrates a basic simulation flow on the basis of an SOI FinFET. Initially, the
simulation structure is generated based on device templates using GTS Structure. Subsequently,
different simulation modes of Minimos-NT such as the Drift Diffusion and Density Gradient
models are presented and results are compared. The GTS Framework project overview is
displayed in the figure below.

Figure 1: Project tool folder.

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SOI FinFET GTS APPLICATION EXAMPLE

Structure Generation
The device structure for this example is an SOI FinFET based on a predefined device template
available in GTS Structure. The defined device geometry can be easily modified by an elaborate
set of parameters. Thus, also parameter studies can be carried out, as presented later on.

Device Template
For the initial simulations, a FinFET with a gate length of 32 nm is considered. The geometry
parameters are listed below.

nmos_32nm_3d_finfet.ipd
Variables
{
Contactwidth=15 nm;
SDExtent = 35 nm;
gateLength = 32 nm;

finThickness = 30 nm;
oxideThickness = 1.6 nm;
boxThickness = 20 nm;
substrateThickness = 10 nm;
contactThickness = 10 nm;

contactDeepth = 15 nm;
finDeepth= 10 nm;

dopShift = 3 nm;
dopSigma = 1 nm;

gridSpaceGate = 1 nm;
numPointsOxide = 5;
numPointsSDExtent = 10;
numPointsBoxY = 7;
numPointsBoxZoutside = numPointsBoxY/2;
numPointsSubsY = 4;
}
...

Figure 2 shows the template based creation of a 3D FinFET in GTS Structure. In the left column,
the geometry parameters can be modified, while on the right, the device structure with the
net-doping profile is displayed.

Geometry and Doping Editor

Additionally to the template based structure generation, GTS Structure offers a full two- and
three-dimensional graphical geometry editor as shown in Fig. 3. Here, additional segments can
be added, shapes can be modified, and even whole new device structures can be created. As a
next step, the doping is defined using the dopant editor mode of GTS Structure (see Fig. 4).

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GTS APPLICATION EXAMPLE SOI FinFET

Figure 2: Template based generation of an SOI FinFET structure.

Figure 3: Graphical Geometry Editor: Segment Edit Mode.

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SOI FinFET GTS APPLICATION EXAMPLE

Figure 4: Graphical Geometry Editor: Doping Edit Mode.

Figure 5: Graphical Geometry Editor: Segment view and doping distribution in source and drain regions.

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GTS APPLICATION EXAMPLE SOI FinFET

Mesh Generation
After defining device geometry and dopings, the simulation mesh can be created. In this
example, we create a structured mesh refined to the sensitive zones of the device (Fig. 6). The
mesh definition parameters are listed below.

nmos_32nm_3d_finfet.ipd
simulationGrid : ~MeshDefaults
{
{
Refine
{
+Refine1 : ~Ortho1DRefineDefaults
{
dimension = "x";
lower = ~Segments.x3;
upper = ~Segments.x4;
definedBy = "min_max";
minx = ~[Link];
maxx = ~[Link];
}
}
segment = "*";
usage = "all";
}
...
}

Figure 6: Mesh editor: Ortho mode with convenient mesh refinement picks.

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SOI FinFET GTS APPLICATION EXAMPLE

Figure 7: Segment overview with mesh.

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GTS APPLICATION EXAMPLE SOI FinFET

Device Simulation
The device structure is now ready to be simulated. Within the Minimos-NT setup page, the
simulation models are chosen and the contact voltages are defined, as shown in Fig. 8. The
corresponding InputDeck definitions are listed below.

Figure 8: General simulation setup with contact voltage stepping definitions.

Figure 9 shows the electrostatic potential as iso-surfaces for the on- and off-state of the FinFET.
Next, Drift Diffusion based simulations are compared to results based on the Density Gradient
model. As presented in Fig. 10, the spurious rise of the electron concentration against the
oxide interface as given by classical simulations does not occur in DG simulation results.

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SOI FinFET GTS APPLICATION EXAMPLE

[Link]
#include <[Link]>
Device : ~DeviceDefaults
{
Grid
{
simulationGrid = "simulationGrid";
}
Input
{
file = "minimos";
fileType = "devbz";
}
Output
{
enable = ~[Link] || ~[Link];
}
Phys
{
+bandGapNarrowing = "";
}
+Bulk = 0.0 "V";
+Source = 0.0 "V";
+Drain = stepN(0.05 "V", 1.0 "V", 2, pri = 1);
+Gate = step(-0.2 "V", 1.0 "V", 0.1 "V", pri = 2);
}
Iterate : IterateDefaults
{
Scheme : SchemeDefaults.DG_NMos_QFL;
}
...

Figure 9: Electrostatic potential in on- (left picture) and off state (right picture).

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GTS APPLICATION EXAMPLE SOI FinFET

Figure 10: Electron concentration within a perpendicular cut through the fin. The lower left figure presents
classical results, while the electron concentration in the lower right figure has been carried
out with the Density Gradient model.

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SOI FinFET GTS APPLICATION EXAMPLE

Transfer Characteristics
In order to simulate the transfer characteristics of the device, a gate voltage sweep has been
set up for two different source/drain voltages (Vd=0.05 V, Vd=1 V). Thus, both the linear and
the saturated regime of the device can be illustrated (Fig. 11).

Figure 11: Transfer characteristics for Vd=0.05 V and Vd=1 V in linear and logarithmic current scale,
respectively. The results have been carried out applying the density gradient model.

Continuative Simulations
Next, capacitance-voltage (CV) characteristics of both gate and drain capacitance and oxide
leakage currents are investigated. For the CV characteristics, both the gate and drain capac-
itances have been considered, as illustrated in Fig. 12. Figure 13 displays the gate leakage
current of the 32 nm FinFET structure with respect to the gate voltage. As a parameter, the
drain voltage has been swept from 0 V to 1 V.

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GTS APPLICATION EXAMPLE SOI FinFET

Figure 12: Capacitance-Voltage characteristics.

Figure 13: Gate leakage current for different drain voltages.

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SOI FinFET GTS APPLICATION EXAMPLE

Device Scaling
In order to investigate geometrical influences on the device characteristics, GTS Structure can
be used to modify existing device structures and set up parameter sweeps. In our case, the
channel length has been reduced from 32 nm to 22 nm for illustration. Figure 14 shows the
modified device geometry in GTS Structure.

Figure 14: Device Editor: Device scaled to 22 nm gate length.

Subsequently, the transfer characteristics have been simulated for both the 32 nm and 22 nm
FinFETs, respectively. As illustrated in Fig. 15, the 22 nm device (brown curves) achieves higher
current values than the 32 nm device (violet curves) for both the linear and saturated regime.

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GTS APPLICATION EXAMPLE SOI FinFET

Figure 15: Transfer characteristics comparison. Brown curves depict the 22 nm device, violet 32 nm.
Both IDlin and Idsat are displayed in logarithmic (left) and linear (right) current scale.

Summary
Based on a FinFET structure, a simulation workflow including GTS Structure and Minimos-NT
has been demonstrated. The device geometry has been created using GTS Structure and
subsequently used to apply Drift Diffusion and Density Gradient simulations in Minimos-NT.
CV-Curves and Gate leakage analysis have been carried out. Finally, the influence of the channel
length on the transfer characteristics has been illustrated.

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SOI FinFET GTS APPLICATION EXAMPLE

ToolFolder List
The project SOI_FinFET contains the following ToolFolders (TF):

TF Tool Description
001 Structure nMOS, lg=32 nm
002 Minimos 001 - Transfer DD Idlin, Idsat
003 Minimos 001 - Transfer DG Idlin, Idsat
004 Minimos 001 - CV DD
005 Minimos 001 - CV DG
006 Minimos 001 - Gate leakage DD
007 Minimos 001 - Gate leakage DG
008 Structure nMOS, lg=22 nm
009 Minimos 008 - Transfer DG Idlin, Idsat

For information on obtaining the project files, see beginning of this document.

14 © 2024 Global TCAD Solutions GmbH