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ANNA UNIVERSITY (UNIVERSITY DEPARTMENTS)
B.E. (FullTime) -END SEMESTER EXAMINATIONS, APRIL/ MAY 2023
ELECTRONICSAND COMMUNICATION ENGINEERING
VISemester
EC56518DIGITAL VLSI
(Regulation2019)
Time:3hrs Max. Marks: 100
C01 Ability to analyze inverter characteristics and realize modeling of MOS transistors
CO2 Ability to design combinational logic using various logic styles, satisfying static and dynamic
requirements
CO3 Ability to analyze timing issues of sequential logic and design memories
CO4 Ability to design data path elements
CO5 Ability to compare and analyze FPGA architecture and interconnect methodology
BL-Bloom's Taxonomy Levels (L1-Remembering, L2-Understanding, L3-Applying, L4-Analysing. L5
Evaluating, L6-Creating)
Table 1
Use the following transistor prannetera for deaign SalsAaLAREAuä
NIOS
PMOS
· PART-A (10 x 2 = 20Marks)
(Answer all Questions)
[Link] Questions Marks CO BL
Why PMOS pass transistor conducts strong one and weak zero. 2 1 L2
Illustrate with neat diagram.
What are the limitations of scaling? 2 1 L1
2 L3
Implement F = ABC + ACD(and F) in DCVSL using minimum
number of transistors. Assume A, B,C, D, and their complements
are available as inputs.
Compare the logical effort of a three input'NAND gate realized in 2 2 L5
static CMOS logic style with dynamic CMOS logic style.
Define Clock skew and clock jitter. 2 L1
8 Consider the system shown in the Figure1 with positive skew. 2 L2
Write the constraints for minimum clock period and hold time.
R?
Combinatiewet
Figure 1
Obtain the sum and output carry of full adder in terms of delete and 2 4
L2
propagate function.
How many numbers of stages are needed for 14 bit addition using 2 4
Square root carry select adder?
L3
What are prediffused and prewired arrays? 2 5 L1
What is programmable interconnection point. Draw its equivalent 2 5 L1
schematic.
PART-B (5 x13 = 65Marks)
[Link]
Questions Marks CO BL
11 (a) () | Draw the stick diagram of 4x1 static CMOS
multiplexer. List out the 1 L3
Electrical properties of CMOS circuit. Explain any two with
necessary diagram and derivations.
(i) Determine the threshold voltage of NMOS
the substrate effect. Assume Psubstrate isdevice
by considering 4 1 L3
doped to Na=2x1015
atoms/cm³at T=300-K, tox=100A, intrinsic carrier concentration (ni)
=1.5 x 1010 cm³, charge density at Si-Sioz
lcm2, work function difference between gateinterface Qss=10-10 C
and Si ms -0.53,
and VsB= 2.5V.
OR
T(b) Draw the (approximative) load lines for both MOS transistor and L3
resistor shown in Figure 2. Mark some of the significant points.
Assume that M1 is a long-channel device. Redraw the load lines
assuming that M1 is velocity-saturated. Willthe voltage at X rise or
fall?
R, =20 k?
Figure 2
Also. determine the required width of the transistor (for L =
0.25um), such that X equals 1.5 V. Use parameters from the Table
1.
Find the gain of static CMOS Inverter with Vop =2.5V, (WL)=2/1, 4 1 L3
(W/L)n=1/1 and use parameters from the Table 1.
12(0) ) What is the logic function implemented by the CMOS transistor 7 2 L4
NMOS and PMOS devices so
network shown in Figure 3? Size the
that the output resistance is the same as that of an inverter with an
NMOS WIL =2 and PMOS WIL = 4.
L2
L3 A
L1
Figure 3
What are the input patterns that give the worst case toHLand tpLH.
State clearly what are the
have to make a transition initial input patterns and which inputs
in order to achieve this
maximum
propagation delay. Consider the effect of the capacitances
internal nodes. at the
j If P(A=1) = 0.5, P(B=1) =0.2, P(C=1) =
0.3 and P(D=1) = 0.8, 6 2 L4
determine the power dissipation for the circuit
Assume Vop= 1.2V, Cout =10fF and folk =1GHz. shown in Figure 3.
OR
12 (b) (Þ)Compute the following for the
Figure 4 using parameters frompseudo-NMOS inverter shown in 7 L4
the Table 1.
A) VoL and VoH, B) NML and NMH, C) power
low and Vin high. dissipation when Vin
2.5 V
.M WA =
0.5um/0.254um
Yout
M, WL = 4um0.25um
Figure 4
(ii) Determine the delay for the path shown in Figure 5. Assume 6 2 L4
logical ratio of reference inverter is 2.
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Figure 5
13 (a) () With the help of neat diagrams, describe the timing issues present 3 L2
in the sequential circuits. Also, Design a 6T SRAM cell and derive
the pull up ratio and cell ratio.
3
3 L2
C²MOS 5
(ii) With the help of neat circuit diagram explain how dynamic
and clock 1-1 overlap issues.
Tegister overcome clock 0-0 overlap 3 L2
OR 8
implementation of master-slave
13(3) () Describe the transistor-level diagram and derive
negative edge triggered register with the neat
3 L2
its timing properties. logic 1 IS
5
H)Consider a1T DRAM cellshown in the Figure 6, Assume 1) and
(write
Written in the memory cell during the first write assert waveform
the initial data stored in Cs as logic 0. Draw the voltage
at node X and at the node bit line BL. Give the expression for
voltage swing at BL.
BL
WL Write 1 Read 1
WL
JM X
Fiqure 6
4 L3
Describe the realization of mirror adder with necessary equation
and diagram. Analyze its features. 7 4 L3
( Realize the 20-bit square root carry select adder. Mark the worst
case signal arrival times in each stage and derive the critical path
delay.
OR
4 L3
14 (b) () Generate test vectors to find the SA0fault indicated in the logic
shown in the Figure 7.
SAO
Figure 7 L3
of 4X4 bit array 8 4
(ü) With neat diagram, describe how the performance Compare their
multiplier is improved using carry save multiplier.
critical path delays. VLSI L3
different implementation strategies used in
5 5
15 (arExplain the
design. followinglogic
5 L5
) Implement the function F = AB + ABCusing theand C) PLA
modules A) ACT1 FPGA, B) LUT based FPGA
OR
5 L3
architecture of any one type of FPGA 5
15 (b) ()|Describe the Interconnect
device with appropriate diagram. ABC'+A'BC'+A'BCusing 5 L5
=ABC+
(ii) Implement the function F macrocell that has only three product
programmable array logic additional product
feed
term lines. Use shared logic expander to 0LLER O
terms.
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PART- C(1x 15 = 15Marks)
([Link].16 is compulsory)
[Link] Questions Marks CO BL
26. Þ| For the circuit shown in the Figure 8, consider R_=70kn, WIL=4 1 L3
and load capacitance C1=1.2pF. Compute the following:A)VoL and
VOH, B) tpLH, tpHL and t (Neglect intrinsic capacitances of the
device), and C) dynamic power dissipation assuming fastest clock.
Use parameters from Table 1.
+2.5 V
M1 WL
Figure &
7 L3
dynamic CMOS logic produces
( A Explain why cascading Figure 9?
degraded output as shown in
V
CIk
CIk - M, Qut2
Out1 in
In4
Out1
CIk
AV
Out2
Figure 9
using compound
Implement the function O = (0, + O2)03 GH.
B) ABC, O2= DEF and O3 =
domino logic, where O =
ROLLEROF
AU
CHENNAI
600
025 MINA
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