Fault simulation essentials
To reduce the complexity of fault simulation use two approaches.
1. Fault Collapsing
2. Fault Dropping
Fault Collapsing : The number of faulty versions of a circuit that need to be
simulated can be decreased by exploiting two relations between two
faults fi & fj .
1. Fault Equivalence
2. Fault Dominance
Fault collapsing helps to reduce both test generation and fault simulation
times.
Two faults fi and fj in a circuit C are said to equivalent.
If Cfi and Cfj have identical input and output logic behavior.
Simulate Cfi and need not simulate Cfj & vice versa.
fi1, fi2, fi3,…….fil - fil is maintained in the list.
Fault equivalence is a symmetric relation.
fi equivalent fj then
fj equivalent fi
Transitive relation
fi equivalent fj
fj equivalent fl then
fi equivalent fl
Fault Dominance
Let vfi - the set of all vectors that detect fault fi.
Let vfj - the set of all vectors that detect fault fj.
fi is said to dominate fault fj if
a) vfj is subset of vfi
b) Each vector that fi implies identical values at the corresponding
outputs of Cfi and Cfj.
Fault dominance relation is transitive but not symmetric.
Transitive relation
fi dominate fj &
fj dominate fl then
fi dominate fl
fi dominate fj &
fj dominate fi then
fi & fj are equivalent.
{ci1 SAO, cj SA1} {Ci1 SA1, cj SA0} equivalent sets
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{ci1 SA0, ci2 SA0, cj SA0}
equivalent sets
Vfi ={00,01,10} Vfj ={01}
Cj SA1 dominates ci1 SA1
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Cj SA1 dominates ci2 SA1
{ci1 SA1, ci2 SA1, cj SA1} equivalent
sets
Vfi ={01,10,11} Vfj ={10}
Cj SA0 dominates ci1 SA0
Cj SA0 dominates ci2 SA0 6
2 input NAND
{ci1 SA0, ci2 SA0, cj SA1} equivalent sets
Vfi ={00,01,10} Vfj ={01}
Cj SA0 dominates ci1 SA1 Cj SA0 dominates ci2 SA1
2 input NOR
{ci1 SA1, ci2 SA1, cj SA0} equivalent sets
Vfi ={01,10,11} Vfj ={10}
Cj SA1 dominates ci1 SA0 Cj SA1 dominates ci2 SA0
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Fault Dropping output level
7 lines 14 faults in the list 15 simulations
7 faults in the list 8 simulations
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Fault Simulation Algorithms
1. Serial Fault Simulation :
Serial fault simulation is the simplest fault simulation technique.
It consists of fault free and faulty circuit simulations.
Initially, fault-free logic simulation is performed.
After fault-free simulation, a serial fault simulator simulates faults one at a
time.
Fault injection is first performed, which modifies the original circuit to
mimic the circuit behavior in the presence of the fault.
Then, the faulty circuit is simulated.
This process repeats until all faults in the fault list have been simulated.
Nine simulation runs are performed: 3 fault-free and 6 faulty circuit
simulations.
These nine simulation runs can be divided into three simulation passes.
In each simulation pass, either the fault-free or the faulty circuit is simulated
for the whole test pattern set.
The first simulation pass consists of fault-free simulations for P1, P2, and P3,
and the second and third passes correspond to the faulty circuit simulations of
faults f and g, respectively, for P1, P2, and P3.
Advantage: its ease of implementation
can handle a wide range of fault models
Disadvantage : low performance
2. Parallel Fault Simulation :
Take advantage of the bitwise parallelism inherent in the host computer to
reduce fault simulation time.
For example, in a 32-bit wide CPU, logic operations (AND, OR, or XOR)
can be performed on all 32 bits at once.
There are two ways to realize bitwise parallelism in fault simulation:
parallelism in faults and parallelism in patterns.
a. parallel fault simulation
b. parallel pattern fault simulation.
w-bit wide data words
w−1 bits are allocated for w−1 faulty circuits and the remaining bit is
reserved for the fault-free circuit.
Inject the faults by adding extra logic gates.
Assuming that the width of a computer word is three bits,
the first bit stores the fault-free (FF) circuit response,
the second bits store the faulty responses in the presence of faults f
and third bits store the faulty responses in the presence of faults g
parallel fault simulation technique is applicable to the unit or zero delay
models only.
a simulation pass cannot terminate unless all the faults in this pass are
detected.
three simulations (in one simulation pass) are performed.
Best for simulating the beginning of the test pattern sequence when a large
number of faults are detected by each pattern.
It is not used in non Boolean logic.
b) Parallel-Pattern Fault Simulation :
w-bit data width, w test patterns
For the fault-free or faulty circuit, w test patterns can be simulated in parallel
by utilizing bitwise logic operations.
This approach is especially useful for combinational circuits.
Faults are injected by activating rising or falling events, depending on
the stuck-at value, at the faulty signal.
q faults (q + 1) passes
Best suited for simulation of test patterns that come later in the test sequence,
where the fault drop per pattern is lower.
Deductive Fault Simulation
• Fault list propagation
• The output fault list of a gate is generated by set operations such as
union intersection and complementation (-), among
fault lists.
• when both inputs of a two-input AND gate are 0, to propagate through,
the effect of a fault must be present on both inputs.
• This is achieved by the intersection, of the two input fault
lists. In addition, the fault is C1 included.
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Total faults {a/0 , a/1, b/0, b/1, c/0, c/1, d/0, d/1, e/0, e/1, f/0, f/1, g/0, g/1} 14 faults
After fault collapsing {a/0 , a/1, b/0, b/1, c/1, d/0, d/1 } 7 Faults
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{a/0 , a/1, b/0, b/1, c/1, d/0, d/1 }
C1 SA1 undetectable
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