EBEC22IL1 DIGITAL SYSTEMS LAB
LAB MANUAL - STAFF MANUAL
DEGREE : [Link]
BRANCH : COMPUTER SCIENCE AND ENGINEERING
SUBJECT CODE EBEC22IL1
SUBJECT NAME DIGITAL SYSTEMS LAB
REGULATION 2022
EBEC22IL1 DIGITAL SYSTEMS LAB
BEC18IL1 DIGITAL SYSTEMS LAB
LIST OF EXPERIMENTS
1. VERIFICATION OF TRUTH TABLES OF LOGIC GATES
2. IMPLEMENTATION OF BOOLEAN FUNCTION
3. IMPLEMENTATION OF ADDERS & SUBTRACTORS
4. IMPLEMENTATION OF MULTIPLEXERS
5. IMPLEMENTATION OF DEMULTIPLEXERS
6. IMPLEMENTATION OF ENCODER
7. IMPLEMENTATION OF DECODERS
8. VERIFICATION OF FLIP – FLOPS
9. IMPLEMENTATION OF SISO,SIPO
10. IMPLEMENTATION OF PISO,PIPO
11. IMPLEMENTATION OF JOHNSON COUNTER
12. STUDY OF MODULO-N COUNTER
EXP. NO: 1 VERIFICATION OF TRUTH TABLES OF LOGIC GATES
AIM: To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
THEORY:
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level
when any one of the inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when
both the inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is
low. The output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when
both inputs are low and any one of the input is low .The output is low level when
both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.
X- OR GATE:
The output is high when any one of the inputs is high. The output is low
when both the inputs are low and both the inputs are high.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:
SYMBOL:PIN DIAGRAM:
OR GATE:
NOT GATE:
SYMBOL: PIN DIAGRAM:
X-OR GATE :
SYMBOL :PIN DIAGRAM :
2- INPUT NAND GATE:
SYMBOL: PIN DIAGRAM:
3-INPUT NAND GATE :
NOR GATE:
RESULT: Thus the different kinds of logic gates are studied.
EXP. NO: 2 IMPLEMENTATION OF BOOLEAN FUNCTION
AIM: Implementation of the Given Boolean Functions using Logic Gates in Both
SOP and POS Forms.
I. Two input SOP: Y = A.B + A.𝐵̅
II. Two input POS: Y = (A+B) (A+𝐵̅)
EQUIPMENT REQUIRED: Power Supply, Digital Trainer, IC’s (7404, 7408,
7432) Connecting leads.
THEORY
SOP FORM OF BOOLEN FUNCTION: The sum of product or SOP form is represented by using
basic logic gates like AND gate and OR gate. The SOP form implementation will have the AND
gate at its input side and as the output of the function is the sum of all product terms, it has an OR
gate at its output side. This is important to remember that we use NOT gate to represent the inverse
or complement of the variables.
POS FORM OF BOOLEN FUNCTION:
The product of sums or POS form can be represented by using basic logic gates like AND gate and
OR gates. The POS form implementation will have the OR gate at its input side and as the output
of the function is product of all sum terms, it has AND gate at its output side. In POS form
implementation, we use NOT gate to represent the inverse or complement of the variables.
Logic diagram for SOP Boolean function
AB
A
7408 Y = AB+A𝐵
B
7432
A
A𝐵
𝐵 7408
B
7404
Truth Table for this SOP expression
A B 𝐵̅ A.B ̅
A.𝐵 Y = A.B + A.𝐵̅
0 0 1 0 1 1
0 1 0 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
Logic Diagram For POS Form
A A+B
7432
B
̅ Y = (A+B)(A+𝐵̅)
A+𝐵 7408
A
7432
̅
𝐵
Truth Table For POS Expression
A B 𝐵̅ A+B A+𝐵̅ Y = (A+B)(A+𝐵̅)
0 0 1 0 1 0
0 1 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 1
PROCEDURE
SOP form
1. Place the Digital lab kit at one place.
2. Take the one AND gate ICs i.e. IC no.7408, one NOT gate IC i.e. IC no. 7404 and one OR gate
IC i.e. IC no. 7432.
3. Place these 3 ICs in the breadboard one by one.
4. Now, connect the AND gate with the inputs of A and B and other AND gate in the same IC is
given by the complement input of the A and B i.e. A’ and B’ by using NOT gate with the help of
connecting wires.
5. Give the output voltage Vcc and GROUND to all the ICs separately.
6. When whole configuration is read, gently on the switch and note there output of different values
of A and B i.e. either 0 or 1.
For POS form
Place the Digital lab kit at one place.
1. Take the 1 OR, 1 AND, 1 NOT gates IC
2. Place these 3 ICs in the breadboard one by one.
3. Now, connect the OR gate of Input A or B, B or C and last one is A or C’ (i.e. complement of C
using NOT gate. Inputs are connected with the help of connecting wires.
4. When whole circuit is complete, on the switch and note down the output with different values of
A, B and C.
RESULT:-Hence, given Boolean Expression is implemented by the Logic Gates.
1. Y = A.B + A.𝐵̅
2. Y = (A+B) (A+𝐵̅)
[Link]: 3 IMPLEMENTATION OF ADDERS & SUBTRACTORS
AIM:
To design and implement the adder and subtractor circuits using logic gates and to
verify its truth tables.
EQUIPMENT REQUIRED:
Digital Trainer kit
IC 7408 – AND IC
IC 7432 –OR IC
IC 7486 – EXOR IC
IC 7404 – NOT IC
THEORY:
Half Adder:
A combinational circuit that performs the addition of two bits is called half adder. A half
adder circuit needs two binary inputs and binary outputs. The input variable designates the augends
and the addend bits. The output variables produce the sum and the carry.
The carry output is 0 unless both inputs are [Link] S output represents the least significant
bit of the sum.
The simplified Boolean functions for the two outputs can be obtained directly from the
truth table.
S=X’Y+XY’
C=XY
Full Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs. The two outputs are designated by the symbols S for sum
and C for carry.
The binary variable S gives the value of the least significant bits of the sum.
Binary variable C gives the output carry.
When all inputs are 0,the output is [Link] S output is equal to 1 when only one input is equal to
[Link] c output has a carry of 1 if two or three inputs are equal to 1.
The simplified Boolean functions for the two outputs can be obtained directly from the truth
table.
S=X’YC’+X’YZ’+XY’Z’+XYZ
C=XY+XZ+YZ
Half Subtractor:
A half subtractor is a combinational circuit that subtracts two bits and produces their
differences. A half subtractor needs two binary inputs and two binary outputs. The input variable
designate minuend and subtrahend bits. The output variables produce the difference and borrow.
The simplified Boolean functions for the two outputs can be easily obtained directly from
the truth table.
D=X’Y+XY’
B=X’Y
Full Subtractor:
A full subtractor is a combinational circuit that performs a subtraction between three bits,
1 may have been borrowed by a lower significant bit. This circuit has three inputs and 2 outputs.
The three inputs a, b and c denote the minuend subtrahend and previous borrow. The two outputs
D and B represent the difference and output borrow.
The simplified Boolean functions for the two outputs can be obtained directly from the
truth table.
D= X’Y’Z+X’YZ’+XY’Z’+XYZ
B=X’Y+X’Z+YZ
Truth table of half subtractor
Truth table for full subtractor
INPUTS OUTPUTS
X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
PROCEDURE:
1. The connections are given per the logic diagram.
2. The supply voltage and the ground are connected to the appropriate pins.
3. The inputs are given by switches. If the switch is ON input is 1, otherwise 0
4. The output obtained from LED glows output is 1, else 0
5. For various combinations of input the output is verified.
RESULT: Thus an adder and subtractor circuits using logic gates were
implemented and its truth tables are verified
[Link] IMPLEMENTATION OF MULTIPLEXERS
AIM:
To construct the Multiplexer using logic gates and verify its truth table
APPARATUS REQUIRED:
1. Digital trainer kit
2. IC 7404 – NOT IC
3. IC 7411-3 I/P AND GATE
THEORY:
Multiplexer
Multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. A multiplexer is also called as data selector. Normally there are 2 n input lines
and n selection lines whose bit combinations determine which input is selected.
In a 4 to 1 line multiplexer, each of four input lines I0 to I3 is applied to one input of an AND gate. Selection
lines S1 and S0 are decoded to select a particular AND gate. The function table lists the input to output path for
each possible bit combination of selection linesTo demonstrate the circuit operation consider the case when
S1S0=10. The AND gate associated with input I2 has two of its inputs equal to 1 and third input connected to I2.
The other three AND gates have at least one input equal to 0, which makes their output equal to 0. The OR gate
have at least one output is now equal to the value of I 2, thus providing path from the selected input to the output.
PROCEDURE:
1) Supply voltage and ground are connected to the appropriate pins.
2) The input and output are connected to switches and LEDs respectively.
3) For various select input combinations, the output is verified.
Circuit diagram for 1x4 Multiplexer
Truth table for 1X4 Multiplexer
RESULT: Thus the Multiplexer using logic gates was constructed and verified its truth table
[Link] IMPLEMENTATION OF DEMULTIPLEXER
AIM:
To construct Demultiplexer using logic gates and verify its truth table.
APPARATUS REQUIRED:
1. Digital trainer kit
[Link] 7404 – NOT IC
[Link] 7408 – AND IC
THEORY:
DeMultiplexer
A demultiplexer is a combinational logic circuit that receives the information on a single input and transmits the
same information over one of 2n possible output lines. The bit combinations of the select lines control the
selection of specific output line to be connected to the input at given instant.A 1-to-2 demultiplexer consists of
one input line, two output lines and one select line. The signal on the select line helps to switch the input to one
of the two outputs. There are only two possible ways to connect the input to output lines, thus only one select
signal is enough to do the demultiplexing operation. When the select input is low, then the input will be passed
to Y0 and if the select input is high then the input will be passed to Y1. Demultiplexers are also called as data
distributors, since they transmit the same data which is received at the input to different destinations.
PROCEDURE:
4) Supply voltage and ground are connected to the appropriate pins.
5) The input and output are connected to switches and LEDs respectively.
6) For various select input combinations, the output is verified.
Circuit diagram for 1x4 Multiplexer
Logic Diagram for Demultiplexer Truth Table for 1X4 Demultiplexer
RESULT: Thus the Demultiplexer using logic gates was constructed and verified its truth table
[Link]: 6 IMPLEMENTATION OF ENCODER
AIM:
To design and implement ENCODER using logic gates and verify its truth table
APPARATUS REQUIRED:
S..No. COMPONENT SPECIFICATION QTY.
1. OR GATE IC 7432 3
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27
THEORY:
ENCODER: An encoder is a digital circuit that performs inverse operation of a decoder. An
n
encoder has 2 input lines and n output lines. In encoder the output lines generates the binarycode
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and
three output that generate the corresponding binary code. In encoder it is assumed that only one input has a
value of one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs
are zero the outputs are zero. The zero outputs can also be generated when D0 = 1.
LOGIC DIAGRAM FOR ENCODER:
TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the encoder was designed and implemented using logic gates and verified its truth table.
[Link]: 7 IMPLEMENTATION OF DECODER
AIM:
To design and implement DECODER using logic gates and verify its truth table
APPARATUS REQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. 3 I/P NAND GATE IC 7410 2
2. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 27
THEORY
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into coded output
where input and output codes are different. The input code generally hasfewer bits than the output code. Each
input code word produces a different output code word [Link] is one to one mapping can be expressed in truth
n
table. In the block diagram of decoder circuit the encoded information is present as n input producing 2 possible
n n
outputs. 2 output values are from 0 through out 2 – 1.
LOGIC DIAGRAM FOR DECODER
TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the decoder was designed and implemented using logic gates and verified its truth table
[Link]: 8 VERIFICATION OF FLIP FLOPS
AIM: ‐To design and construct basic flip-flops R-S, J-K, D and T flip-flops using gates and verify their truth tables
EQUIPMENT REQUIRED
1 IC‟s - 7404, 7402, 7400
2 Electronic circuit designer
3 Connecting patch chords
THEORY:
JK Flip Flop: A JK Flip Flop is a refinement of the RS Flip Flop in that the indeterminate state of the RS type is
defined in the JK type. Inputs J and K behave like S and R to set and clear the flip-flops respectively. When both
inputs J and K are equal to 1, the flip-flop switches to its complement state that is the flip-flop toggles its output.
T Flip Flop: The T flip flop is a single input version of the JK flip-flop. The T flip-flop is obtained from the JK
flip-flop when both inputs are together. The designation T comes from the ability of the flip-flop to toggle its
state.
D Flip Flop: One way to eliminate the undesirable condition of the indeterminate state in the RS flip flop is to
ensure that inputs S and R are never equal to 1 at the same time. This is done in D flip flop. The D input has only
two inputs D and clk. If D=1 and clk=1 outputgoes to 1 and if D=0 and clk =1 then output goes to 0.
PROCEDURE:
1. Connect the circuit as shown in logic connections for JK, D and T Flip Flops.
2. Verify the truth table of all the Flip Flops.
Logic diagram and truth table of JK flip flop
Logic diagram and truth table of RS flip flop
CLK INPUT OUTPUT
State
Clock S’ R’ Q Q’
LOW x x 0 1
HIGH 0 0 0 1
HIGH 1 0 1 0
HIGH 0 1 0 1
HIGH 1 1 1 1
Logic diagram and truth table of D flip flop
Clock OUTPUT
D Q Q’
X X 1 0
X X 0 1
X X 1 1
HIGH 0 0 1
HIGH 1 1 0
Logic Diagram and Truth Table of T Flip Flop
Clock INPUT OUTPUT
RESET T Q Q’
X LOW X 0 1
HIGH HIGH 0 No Change
HIGH HIGH 1 Toggle
LOW HIGH X No Change
RESULT:
Thus RS, JK, D and T flip flops using gates were designed and verified.
[Link]: 9 IMPLEMENTATION OF SISO, SIPO
AIM:
To construct and verify the truth table of the following shift registers for 4 bit using D
Flip Flop
1. Serial In Serial Out
2. Serial In Parallel Out
EQUIPMENT REQUIRED:
Digital Trainer kit
IC 7474
THEORY:
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group
of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop.
Most of the registers possess no characteristic internal sequence of states. All the flip-flops are driven by a
common clock, and all are set or reset simultaneously.
Serial In - Serial Out Shift Registers:
The register is first cleared, forcing all four outputs to zero. The input data is then applied
sequentially to the D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is
transmitted from left to right.
Serial In - Parallel Out Shift Registers:
For this kind of register, data bits are entered serially in the same manner as discussed in the
last section. The difference is the way in which the data bits are taken out of the register. Once the data
are stored, each bit appears on its respective output line, andall bits are available simultaneously.
PROCEDURE:
1. The connections are given as per the circuit diagram
2. Verify the truth table.
PIN DIAGRAM:
Dual D Flip Flop
CIRCUIT DIAGRAMS:
Serial in - Serial Out Shift Registers
Serial In - Parallel Out Shift Registers:
TRUTH TABLES:
Serial in - Serial Out
Serial In Parallel Out
RESULT:
Thus a shift registers are designed and verified their truth tables respectively.
[Link]: 10 IMPLEMENTATION OF PISO, PIPO
AIM:
To construct and verify the truth table of the following shift registers for 4 bit using D flip flop.
1. Parallel In Serial Out
2. Parallel In Parallel Out
EQUIPMENT REQUIRED:
Digital Trainer kit
IC 7474
THEORY:
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group
of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop.
Most of the registers possess no characteristic internal sequence of states. All the flip-flops are driven by a
common clock, and all are set or reset simultaneously.
Parallel In - Serial Out Shift Registers:
The circuit uses D flip-flops and NAND gates for entering data (ie writing) to the register. D0, D1, D2
and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. To write
data in, the mode control line is taken to LOW and the data is clocked in. The data can be shifted when the
mode control line is HIGH as SHIFT is active high.
Parallel In - Parallel Out Shift Registers:
For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits. The D's are the parallel inputs and the
Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the
corresponding Q outputs simultaneously.
PROCEDURE:
1. The connections are given as per the circuit diagram
2. Verify the truth table.
PIN DIAGRAM:
Dual D Flip Flop
CIRCUIT DIAGRAMS:
Parallel In - Serial Out Shift Registers:
Parallel in Parallel out Shift registers:
TRUTH TABLES:
Parallel In serial Out
Parallel In parallel Out
RESULT:
Thus a shift registers are designed and verified their truth tables respectively
[Link]: 11 IMPLEMENTATION OF JOHNSON COUNTER
AIM:
To study and implement Johnson ring counter and verify its truth table.
EQUIPMENT REQUIRED:
Digital Trainer kit
74LS74 IC
Connecting
wires
THEORY:
A counter is used to count a repeated set of values for a variable like clock pulse.
The Johnson Ring Counter or “Twisted Ring Counters”, is another shift register with feedback
exactly the same as the standard Ring Counter above, except that this time the inverted output
Q of the last flip-flop is now connected back to the input D of the first flip-flop as shown below.
The main advantage of this type of ring counter is that it only needs half the number of flip-
flops compared to the standard ring counter then its modulo number is halved. So a “n-stage”
Johnson counter will circulate a single data bit giving sequence of 2n different states and can
therefore be considered as a “mod-2n counter”.
PROCEDURE:
1. The D flip flops are connected as shown in logic diagram.
2. The clock pulse is applied and the output is verified by reading the LED output.
3. Verify the corresponding truth table.
Logic diagram for JOHNSON RING counter
Truth tables for JOHNSON RING counter
RESULT:
Thus JOHNSON RING counter was designed and implemented & its truth table
was verified.
[Link]: 12 STUDY OF MODULO-N COUNTER
AIM:
To study about Modulo N counter.
APPARATUS REQUIRED:
[Link] COMPONENTS SPECIFICATION QTY
1 Modulo N Counter IC 7490 1
2 IC Trainer Kit 1
3 Patch Chord 14
THEORY:
A Modulus-N Counter is a counter in which N represents the number of states present. N= 2n(2 raised to
power n), where ‘n’ is the number of flip-flops required to design the modulus-M counter.
The modulus-6 counter, for example, has six states. The value of n, in this case, is 3. That means the
module-6 counter requires three flip-flops to be designed.
MOD Counters are cascaded counter circuits that count to a predetermined modulus value before being reset.
A counter’s job is to count by advancing its contents by one count with each clock pulse. Counters in a
“count-up” mode advance their sequence of numbers or states when activated by a clock input. Similarly,
counters that reduce their sequence of numbers or states when activated by a clock input are said to be in
“count-down” mode. Bidirectional counters are those that can operate in both the UP and DOWN directions.
Counters are devices that use sequential logic and are activated or triggered by an external timing pulse or
clock signal. A counter can be built to work as either a synchronous or asynchronous circuit. When a clock
signal is applied to synchronous counters, all of the data bits change synchronously. An asynchronous
counter circuit, on the other hand, is independent of the input clock, so the data bits change state one after the
other.
Counters, on the other hand, are sequential logic devices that execute a predetermined sequence of counting
states when triggered by an external clock (CLK) signal. The modulus is the number of states or counting
sequences through which a specific counter advances before returning to its original first state (MOD).
In other words, the modulus (or simply modulo) is the counter’s dividing number and the number of states it
counts.
Modulus Counters, or simply MOD counters, are defined by the number of states they will cycle through
before returning to their original value. For instance, consider a 2-bit counter that counts from 00 to 11.
In binary, that is 0 to 3 in decimal, has a modulus value of 4 (00 1 10 11, and return to 00), and is thus known
as a modulo-4, or mod-4, counter. It’s also worth noting that it took four clock pulses to get from 00 to 11.
Because there are only two bits in this simple example (n = 2), the maximum number of possible output
States (maximum modulus for the counter is; 2n (2 raised to power n) = 2×2 = 4.
Counters, on the other hand, can be designed to count to any number of 2n(2 raised to power n) states in
their sequence by cascading multiple counting stages into a single modulus or MOD-N counter.
As a result, to count a single data bit while providing 2n(2 raised to power n) different output states, a
“Mod-N” counter will require “N” flip-flops connected (n is the number of bits). It should be noted that N is
always a whole integer value.
LOGIC DIAGRAM: -
MOD – N COUNTER USING 7490 (N=5) Decoding logic
RESULT:
MOD – N counter are realized using 7490 IC and the count sequence is studied.
