VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY

UNIVERSITY OF TECHNOLOGY
FACULTY OF COMPUTER SCIENCE AND ENGINEERING
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LOGIC DESIGN WITH HDL REPORT

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Instructor: Nguyễn Thành Lộc
Students Student IDs
Nguyễn Phạm Lương
2353322
Việt
Trần Đức Chính 2352139
Nguyễn Đặng Minh
2353262
Trường
Nguyễn Ngọc Minh
2352575
Khoa
Trần Nguyễn Minh Hiếu 2352338
Đặng Thái Khang 2352464
FIFO (First In First Out)

FIFO, which stands for "First In First Out," is a method used to manage data structures where the first
element added is the first one to be processed, and the newest element is processed last. Think of a
checkout line at a supermarket: the person who gets in line first is checked out first, while the person
who joins last will be the last to be checked out. This is a simple real-life example of FIFO in action.

Applications in Computing and Digital Systems:

1. Data Structures:

 Queues use the FIFO method to manage data. The first element added to a queue is
the first one removed.

2. Disk Scheduling:

 Disk controllers may use FIFO to decide the order in which to service disk I/O
requests. The first request received is the first one handled.

3. Communications and Networking:

 Network devices like bridges, switches, and routers use FIFOs to manage data
packets. The first packet to arrive is the first one sent out.

4. Task Scheduling in Operating Systems:

 Operating systems might use FIFO to schedule tasks. The first task in the queue is
executed first, ensuring a fair order of processing.
 5. Print Spooling:

 When multiple print jobs are sent to a printer, FIFO is used to manage them. The first
document sent to the printer is printed first.

6. Audio Buffers:

 In audio processing, FIFO buffers handle audio data streams, ensuring that the first
audio sample to enter the buffer is the first to be processed and played, which helps
maintain smooth audio playback.

7. Inventory Management and Accounting:

 FIFO is used to calculate inventory value, assuming that the oldest items are sold
first. The cost of these items is recorded as the cost of goods sold, while the cost of
the newest items remains in inventory.

Design and Implementation of a FIFO Circuit using Verilog HDL

This Verilog module implements a FIFO buffer with parameterizable depth. It employs a ring buffer
technique using separate read and write pointers to control the data flow. The signals full and empty
provide the current status of the FIFO.

Basic Functions of the Implemented Circuit:

1. Module Definition:

 Define the module and its input and output.

2. FIFO Depth and Memory Array:

 Define the depth of the FIFO, the width of the address, and the memory array that
stores the data.
3. Pointers:

 Define two pointers: write_ptr and read_ptr.

4. Control Logic:

 The full signal is high when the write pointer is one location behind the read pointer
(indicating that the FIFO is full).

 The empty signal is high when the write and read pointers are at the same location
(indicating that the FIFO is empty).

5. Behavior on Each Clock Cycle:

 If the reset signal is high, the read and write pointers are reset to 0.

 If the write_enable signal is high and the FIFO is not full, data is written to the
memory array at the location pointed to by the write pointer, and the write pointer
is incremented.

 If the read_enable signal is high and the FIFO is not empty, data is read from the
memory array at the location pointed to by the read pointer, and the read pointer is
incremented.
Verilog Module for FIFO:

module fifo(

input clk,

input reset,

input [7:0] din,

input write_enable,

input read_enable,

output reg [7:0] dout,

output is_empty,

output is_full

);

// Parameters for FIFO depth

parameter FIFO_DEPTH = 16;

parameter PTR_WIDTH = 4;

// Memory array to store data

// Read and write pointers

reg [PTR_WIDTH-1:0] write_ptr, read_ptr;

// FIFO control logic

assign is_full = ((write_ptr + 1) % FIFO_DEPTH) == read_ptr;

assign is_empty = write_ptr == read_ptr;

always @(posedge clk or posedge reset) begin

if (reset) begin

write_ptr <= 0;

read_ptr <= 0;

end else begin

if (write_enable && !is_full) begin

fifo_mem[write_ptr] <= din;

write_ptr <= (write_ptr + 1) % FIFO_DEPTH;

end

if (read_enable && !is_empty) begin

dout <= fifo_mem[read_ptr];

read_ptr <= (read_ptr + 1) % FIFO_DEPTH;

end

end

end

endmodule

Test Bench for the FIFO Module:

module test_fifo;

reg clk;
reg reset;

reg [7:0] din;

reg write_enable;

reg read_enable;

wire [7:0] dout;

wire is_empty;

wire is_full;

// Instantiate the FIFO module

fifo uut (

.clk(clk),

.reset(reset),

.din(din),

.write_enable(write_enable),

.read_enable(read_enable),

.dout(dout),

.is_empty(is_empty),

.is_full(is_full)

);

initial begin

// Initialize signals

clk = 0;

reset = 1;

write_enable = 0;

read_enable = 0;

din = 0;

// Apply reset

#5 reset = 0;
 // Write data to FIFO

#10 din = 8'hA5; write_enable = 1;

#10 din = 8'h5A; write_enable = 1;

#10 write_enable = 0;

// Read data from FIFO

#10 read_enable = 1;

#10 read_enable = 0;

end

// Clock generation

always #5 clk = ~clk;

endmodule

Board Demonstration Plan:

1. LED Indicators:

 LED1, LED2, LED3, and LED4 represent the queue positions.

2. Initialize Queue:

 Turn off all LEDs.

3. Enqueue Operation:

 Press Button 1 to add an element to the queue (turn on the next LED in sequence).

 Example: Press Button 1 three times to turn on LED1, LED2, and LED3.

4. Dequeue Operation:

 Press Button 2 to remove an element from the queue (turn off the first LED that was
turned on).

 Example: Press Button 2 and LED1 turns off first, followed by LED2, then LED3.

References:

 Introduction to FIFO Buffers

 Overview of FIFO HDL Implementation