Department of Electrical Engineering

Faculty Member: Dr. Shazad Younis Date: 15th February,2025

Semester: 6th (spring 2025) Section:BEE-14-D

EE-421 Digital System Design

Lab 1: Introduction to Verilog HDL and Quartus
Software

PLO4 PLO4 PLO5 PLO8 PLO9

CLO4 CLO4 CLO5 CLO6 CLO7

Ethics
Viva / Modern
Student Name Reg. No Analysis Individual
Quiz / of Data Tool and
Demo in Report Usage Teamwork

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

Ahmad Nasir 409959

Sataish Elahi 423621

Irfa Farooq 412564

Page 1 of 20
Introduction:
Objective:
The objective of this lab is to familiarize yourself with Verilog Hardware descriptive
language and familiarity with Inte; Quartus Software:

🗹 Familiarize yourself with all basic Verilog Concepts

🗹 Create a Quartus Project and Program the FPGA

Software
• Quartus
VERILOG:
Verilog is a Hardware Description Language; a textual format for describing electronic
circuits and systems. Applied to electronic design, Verilog is intended to be used for verification
through simulation, for timing analysis, for test analysis (testability analysis and fault grading)
and for logic synthesis.
Quartus:
Quartus is a comprehensive software tool suite used for FPGA (Field Programmable
Gate Array) and CPLD (Complex Programmable Logic Device) design. Developed by Intel
(formerly Altera), Quartus Prime is widely used in the field of digital circuit design and is known
for its advanced features and capabilities. Here are some key aspects of Quartus Prime:
Key Features of Quartus
Design Entry and Synthesis:
Quartus allows for design entry using schematic diagrams, VHDL, Verilog, and System
Verilog.It includes a sophisticated synthesis engine to convert high-level design descriptions
into lower-level representations (like RTL - Register Transfer Level).
Simulation and Verification:
The software integrates with simulation tools like Modelsim to verify the logic
and functionality of the design before hardware implementation.
Hardware Support:
Quartus supports a wide range of Intel FPGA and CPLD hardware, enabling designers
to create complex digital systems that can be programmed into these devices.
Timing Analysis:
The tool includes powerful timing analysis features, helping designers ensure
that their designs meet the required performance criteria.

Device Programming and Configuration:

Page 2 of 20
 Quartus also supports device programming, enabling users to upload their
designs to physical FPGA or CPLD devices.
IP Core Integration:
It includes a range of Intellectual Property (IP) cores that can be integrated into
designs, speeding up the development process.
FPGA BOARD:
A FPGA is an integrated circuit designed to be configured by a customer or a designer
after manufacturing – hence the term field-programmable. The FPGA configuration is generally
specified using a hardware description language (HDL), similar to that used for an
applicationspecific integrated circuit (ASIC). Circuit diagrams were previously used to specify
the configuration, but this is increasingly rare due to the advent of electronic design automation
tools.
FPGAs enable manufacturers to implement systems that can be updated when
necessary. A good example of FPGA use is high-speed search: Microsoft is using FPGAs in
its data centres to run Bing search algorithms. The FPGA can change to support new
algorithms as they are created.

Page 3 of 20
Lab Procedure
Lab Task 1:
Code:

Module (output f, input a,input b);

and u1(f,a,b);
endmodule

OUTPUT:

OUTPUT Waveform:

Page 4 of 20
Simulation Through Modelsim:

Test Bench:

module tb_andgate; //Declare Input Vectors as reg reg a; reg b;

//Declare outputs are wires

wire f;

//Module Instantation

andgate uut(.a(a), .b(b), .f(f)); //The Initial Block initial

begin

//At time t=0 ns

a=0; b=0; #100;

a=1;b=0; #100

a=0; b=1; #100

a=1; b=1;

//Stop and Finish the Simulation

$stop;

$finish;

end endmodule

Output:

Page 5 of 20
.

Lab Task 2
CODE:
module andgate (
input [9:0] SW,
output [9:0] LEDR
);
assign LEDR = SW;
endmodule
Output Snippet:

Hardware Implementation:

Page 6 of 20
Lab Task 3
Write gate level code for or, not, xor , xnor gates and test their working on FPGA board.
XOR Gate:
Code:
module task2(output f, input a, input b);
xor exlusive_or(f,a,b); endmodule
Output:

Hardware implementation:

Page 7 of 20
OR gate:
Code:
module task2(output f, input a, input b);
or OR(f,a,b); endmodule
Output:

Page 8 of 20
Hardware Implementation:

Not Gate:
Code:
module task2(output f, input a); not
NOT(f,a);
endmodule

Page 9 of 20
Output:

Xnor Gate:
Code:
module task2(output f, input a,input b); xnor
exclusive_nor(f,a,b);
endmodule
Output:

Page 10 of 20
Hardware Snippet:

Lab Task 4
In this exercise you will learn how to construct a 4 bit and gate using 2 bit and gates. In the working
example of and gate you saw that and gate can be constructed by using its gate primitive. To
construct a 4 bit and gate we will use three instances of 2 bit and gates as shown in the figure 41
below

Figure 41: A 4 bit and gate constructed using two bit and gates only

Page 11 of 20
Code:
module andgate(
output f, input a,b wire w1, w2;
);
assign f = a & b; andgate G1(.f(w1), .a(a),
.b(b));
endmodule
andgate G2(.f(w2), .a(c),
.b(d));
module andgate_4bit(
andgate G3(.f(f), .a(w1),
input a, b, c, d, output f .b(w2));
); endmodule

Test Bench
`timescale 1ns / 1ps // Monitor outputs
$monitor("Time=%0t | Inputs: a=%b,
b=%b, c=%b, d=%b | Output: f=%b",
module andgate_4bit_tb;
$time, a, b, c, d, f);
// Testbench signals
reg a, b, c, d;
// Apply test cases
wire f;
a = 0; b = 0; c = 0; d = 0; #10;
a = 0; b = 0; c = 0; d = 1; #10;
// Instantiate the module under test
a = 0; b = 0; c = 1; d = 1; #10;
andgate_4bit UUT (
a = 0; b = 1; c = 1; d = 1; #10;
.a(a), .b(b), .c(c), .d(d),
a = 1; b = 1; c = 1; d = 1; #10;
.f(f)
);
// End simulation
$finish;
// Test sequence
end
initial begin
endmodule

Page 12 of 20
Output Snippets:

Hardware:

Page 13 of 20
Lab Task 5

1.Design a half adder circuit on paper using a truth table.

Page 14 of 20
2.Use gate level modelling for the half adder.

module half_adder ( input A, B,

output Sum, Carry
);
xor (Sum, A, B);
and (Carry, A, B);
endmodule

3.Write a test bench for half adder circuit

module tb_half_adder;
reg A,B;
wire Sum,Carry;

half_adder uu1(.A(A),.B(B),.Sum(Sum),.Carry(Carry)); initial

begin

A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;

$stop;
$finish;

end endmodule

Page 15 of 20
4.Verify the simulation using a test bench.

Output:

Page 16 of 20
Lab Task 6
1.Create a full adder circuit using half adder designed in task 5. Make a paper design
first

2.Use gate level modelling for full adder circuit.

module full_adder ( input A, B, Cin,
output Sum, Cout
);
wire S1, C1, C2;
half_adder HA1 (.A(A), .B(B), .Sum(S1), .Carry(C1));

Page 17 of 20
 half_adder HA2 (.A(S1), .B(Cin), .Sum(Sum), .Carry(C2));
or (Cout, C1, C2);
endmodule

3.Write a test bench for the full adder circuit

module tb_full_adder; reg A, B, Cin; wire Sum, Cout; full_adder uut (
.A(A), .B(B), .Cin(Cin),
.Sum(Sum), .Cout(Cout)
); initial begin

A = 0; B = 0; Cin = 0; #10;
A = 0; B = 0; Cin = 1; #10;
A = 0; B = 1; Cin = 0; #10;
A = 0; B = 1; Cin = 1; #10;
A = 1; B = 0; Cin = 0; #10;
A = 1; B = 0; Cin = 1; #10;
A = 1; B = 1; Cin = 0; #10;
A = 1; B = 1; Cin = 1; #10;

$stop; $finish; end

endmodule

Page 18 of 20
4.Verify the simulation of full adder using a test bench.
\

Output:

Page 19 of 20
Conclusion:
This lab covered the basics of Verilog HDL and the Quartus software environment, focusing on design
entry, simulation, and FPGA implementation. Students gained hands-on experience in designing and testing
digital circuits, including fundamental logic gates and arithmetic modules. The exercises emphasized circuit
validation through simulation and hardware implementation, demonstrating the significance of HDL in
contemporary digital design. Additionally, the lab introduced essential FPGA concepts like pin mapping and
resource management, reinforcing the importance of efficient coding for practical applications.

Page 20 of 20