MP8862
MP8862
DESCRIPTION FEATURES
The MP8862 is a synchronous, 4-switch, Wide 2.8V to 22V Operating Input Voltage
integrated buck-boost converter capable of Range
regulating the output voltage across a 2.8V to 1V (1) to 20.47V Output Voltage Range (5V
22V wide input voltage range with high Default) with 10mV Resolution through I2C
efficiency. 2A Output Current or 4A Input Current
Four Low RDS(ON) Internal Buck Power
The MP8862 uses constant-on-time (COT)
MOSFETs
control in buck mode and constant-off-time
control in boost mode, providing fast load Adjustable Accurate CC Output Current
transient response and smooth buck-boost Limit with Internal Sensing MOSFET via I2C
mode transient. The MP8862 provides auto 500kHz (1) Switching Frequency
PFM/PWM or forced PWM switching modes, Output Over-Voltage Protection (OVP)
and programmable output constant current (CC) Hiccup
current limit, which support flexible design for Output Short-Circuit Protection (SCP) with
different applications. Hiccup Mode
Over-Temperature Warning and Shutdown
Full protection features include over-current I2C Interface with ALT Pin
protection (OCP), over-voltage protection
Four Programmable I2C Addresses
(OVP), under-voltage protection (UVP),
One-Time Programmable (OTP) Non-
programmable soft start, and thermal shutdown.
Volatile Memory
The MP8862 is available in a 16-pin QFN I2C Programmable Line Drop Compensation,
(3mmx3mm) package. PFM/PWM Mode, Soft Start, and OCP, etc.
EN Shutdown Discharge Programmable
Available in a QFN-16 (3mmx3mm)
Package
APPLICATIONS
Buck-Boost Bus Supplies
Industrial Systems
Personal Medical Products
DSLR Cameras
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS,” the MPS logo, and “Simple, Easy Solutions” are registered trademarks of
Monolithic Power Systems, Inc. or its subsidiaries.
Note:
1) For VOUT < 3V applications, the switching frequency decreases.
TYPICAL APPLICATION
C4 100nF
Efficiency
VIN = 12V, VOUT = 5V to 20V, L = 4.7µH,
VIN L1 4.7µH RDC = 19.5mΩ, forced PWM mode
12V BST1 SW1
100
IN C5 100nF
+ BST2
C1 C1A 95
100µF 22µF SW2
R3
499kΩ 90
EFFICIENCY (%)
VOUT
OUT
EN
C2A
+
C2 85
VCC
C7
22nF
MP8862 10µFx2 100µF
80
R4
499kΩ
ADD ALT 75
R5 VCC 2 SCL
Vo=12V
301kΩ I C slave 70
C3 SDA Vo=20V
1µF
Vo=9V
AGND GND OC 65
Vo=5V
C6
60
R1
21.5kΩ 22nF 0.01 0.1 1 10
OUTPUT CURRENT (A)
ORDERING INFORMATION
Part Number* Package Top Marking
MP8862GQ-xxxx** QFN-16 (3mmx3mm) See Below
MP8862GQ-0000 QFN-16 (3mmx3mm) See Below
EVKT-MP8862 Evaluation kit
* For Tape & Reel, add suffix –Z (e.g. MP8862GQ-XXXX–Z).
** “xxxx” is the configuration code identifier for the register setting stored in the OTP. The default number is “0000”.
Each “x” can be a hexadecimal value between 0 and F. Please work with an MPS FAE to create this unique
number, even if ordering the “0000” code. MP8862GQ-0000 is the default version.
TOP MARKING
Input Power
Supply
Input
Output
Load
PACKAGE REFERENCE
TOP VIEW
BST1 SW1 SW2 BST2
16
IN 1 OUT
GND GND
EN AGND
ADD VCC
QFN-16 (3mmx3mm)
PIN FUNCTIONS
Pin # Name Description
Supply voltage. IN is the drain of the internal power device and provides power to the
entire chip. The MP8862 operates from a 2.8V to 22V input voltage. A capacitor (CIN) is
1 IN
required to prevent large voltage spikes from appearing at the input. Place CIN as close to
the IC as possible.
Power ground. GND is the reference ground of the regulated output voltage. GND
2, 11 GND
requires extra care during PCB layout. Connect GND with copper traces and vias.
On/off control for entire chip. Drive EN high to turn on the chip. Drive EN low or float
3 EN
EN to turn off the device. EN has an internal 2MΩ pull-down resistor to ground.
I2C slave addresses program pin. Connect a resistor divider from VCC to ADD to set
4 ADD
four different I2C slave addresses.
5 SCL Clock pin of the I2C interface. SCL can support an I2C clock up to 3.4MHz.
6 SDA Data pin of the I2C interface.
7 OC Output constant current limit set pin.
8 ALT Alert output. ALT pulling to logic low indicates that a fault or warning has occurred.
9 VCC Internal 3.65V LDO regulator output. Decouple VCC with a 1µF capacitor.
10 AGND Analog ground. Connect AGND to GND.
12 OUT Output power pin. Place the output capacitor close to OUT and GND.
Bootstrap. Connect a 0.1µF capacitor between SW2 and BST2 to form a floating supply
13 BST2
across the high-side switch driver.
Switching node of the second half-bridge. Connect one end of the inductor to SW2 for
14 SW2
the current to run through the bridge.
Switching node of the first half-bridge. Connect one end of the inductor to SW1 for the
15 SW1
current to run through the bridge.
Bootstrap. Connect a 0.1µF capacitor between SW1 and BST1 to form a floating supply
16 BST1
across the high-side switch driver.
Output voltage 5V
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 5V, TJ = -40°C to +125°C (7), typical value is tested at TJ = +25°C, unless otherwise
noted.
Parameter Symbol Condition Min Typ Max Units
Supply current (shutdown) IIN VEN = 0V 0 3 μA
Supply current (quiescent) IQ Non-switching, I2C sets PFM mode 1 mA
EN rising threshold VEN_Rising 1.00 1.10 1.20 V
EN hysteresis VEN_Falling 65 110 160 mV
EN to ground resistance REN VEN = 2V 2 MΩ
EN on to VOUT > 90% delay TDelay See Figure 8 900 μs
VCC regulator VCC 3.3 3.65 4 V
VCC load regulation VCC_LOG ICC = 10mA 1 %
VIN under-voltage lockout
VIN_UVLO 2.50 2.65 2.8 V
threshold rising
VIN under-voltage lockout
VUVLO_HYS 95 160 205 mV
threshold hysteresis
Power Converter
HS switch on resistance RDSON_HS Switch A, D 35 80 mΩ
LS switch on resistance RDSON_LSB Switch B, C 30 70 mΩ
Output voltage VOUT -1.5% 5.0 +1.5% V
Output discharge
RDIS 60 100 Ω
resistance
VEN = 0V, VSW1, SW2 = 22V, TJ = +25°C 1
Switch leakage SWLKG VEN = 0V, VSW1, SW2 = 22V, μA
5
TJ = -40°C to +125°C
Oscillator frequency Fs TJ = +25°C -20% 530 20% kHz
Minimum on time (8) TON_MIN1 Switch A, B, C, D 160 ns
Maximum duty cycle DMAX Buck mode, fREQ = 500kHz 85 %
Minimum duty cycle (8) DMIN Boost mode, fREQ = 500kHz 15 %
Protection
Output over-voltage
VOVP_R 150 160 170 %
protection
Output OVP recovery VOVP_F 130 140 150 %
Low-side B valley limit ILIMIT2 Switch B 6 8 10 A
Low-side C peak current
ILIMIT3 Switch C 10 A
limit
IOUT_LIM1 VOUT = 5V, over 0-125°C temp range 0.85 1 1.15 A
Output average current (8)
IOUT_LIM2 VOUT = 5V, over 0-125°C temp range -7.5% 3 7.5% A
Output UV threshold VUVP 20µs deglitch, UV falling 45% 50% 55% VREF
0 0
-0.1 -0.1
Io=0A
-0.2 -0.2 Io=1A
Io=2A
-0.3 -0.3
0 0.5 1 1.5 2 3 6 9 12 15 18 21
OUTPUT CURRENT (A) INPUT VOLTAGE (V)
Line Regulation vs. Input Voltage Line Regulation vs. Input Voltage
VIN = 3V to 22V, VOUT = 9V, IOUT = 0A to 2A VIN = 3V to 22V, VOUT = 12V, IOUT = 0A to 2A
0.3 0.3
0.2
LINE REGULATION (%)
0.2
LINE REGULATION (%)
0.1
0.1
0
-0.1 0
-0.2
-0.1
-0.3 Io=0A Io=0A
Io=1A -0.2 Io=1A
-0.4 Io=2A Io=2A
-0.5 -0.3
3 6 9 12 15 18 21 3 6 9 12 15 18 21
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
0.2 Vout=9V
10
0.1
8
0
6
-0.1
Io=0A 4
-0.2
Io=1A 2
-0.3 Io=2A
-0.4 0
3 6 9 12 15 18 21 0 0.4 0.8 1.2 1.6 2
INPUT VOLTAGE (V) OUTPUT CURRENT (A)
2 2
IO_MAX (A)
IO_MAX (A)
1.5 1.5
1 Vo=5V 1
Vo=9V Vo=5V
0.5 Vo=12V 0.5 Vo=9V
Vo=20V Vo=12V
0 0
0 2 4 6 8 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20 22 24
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Efficiency Efficiency
VIN = 12V, VOUT = 5V to 20V, L = 4.7µH, VIN = 12V, VOUT = 5V to 20V, L = 4.7µH,
RDC = 19.5mΩ, forced PWM mode RDC = 19.5mΩ, PFM mode
100 100
95 95
90 90
EFFICIENCY (%)
EFFICIENCY (%)
85 85
80 80
75 75
Vo=12V Vo=12V
70 Vo=20V 70 Vo=20V
Vo=9V Vo=9V
65 65 Vo=5V
Vo=5V
60 60
0.01 0.1 1 10 0.01 0.1 1 10
OUTPUT CURRENT (A) OUTPUT CURRENT (A)
Output Voltage vs. Temperature VIN UVLO Rising and Falling
Threshold vs. Temperature
6 3
VIN UVLO RISING AND FALLING
5.8
OUTPUT VOLTAGE (V)
5.6 2.5
5.4
THRESHOLD (V)
2
5.2
5 1.5
4.8
4.6 1
4.4
0.5 Rising
4.2
Falling
4 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
EN Rising and Falling Threshold vs. Output Voltage UVP Threshold vs.
Temperature Temperature
2 100
90
EN RISING AND FALLING
80
70
THRESHOLD (%)
60
1 50
40
0.5 30
Rising 20
Rising
Falling 10 Falling
0
0
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
400μs/div. 2ms/div.
20ms/div. 1ms/div.
CH2: VSW1
CH2: VSW1
10V/div.
10V/div.
CH3: VSW2
CH3: VSW2
10V/div.
5V/div.
CH4: IL
1A/div. CH4: IL
5A/div.
20ms/div. 2ms/div.
CH4: IL CH4: IL
2A/div. 5A/div.
1ms/div. 1ms/div.
CH4: IL CH4: IL
5A/div. 5A/div.
400μs/div. 400μs/div.
CH4: IL CH4: IL
5A/div. 2A/div.
2ms/div. 400μs/div.
CH1: CH1:
VOUT/AC VOUT/AC
50mV/div. 20mV/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2
CH3: VSW2 20V/div.
5V/div.
CH4: IL CH4: IL
1A/div. 2A/div.
1μs/div. 2μs/div.
CH1:
CH1: VOUT/AC
VOUT/AC 20mV/div.
50mV/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2
CH3: VSW2 20V/div.
10V/div.
CH4: IL
CH4: IL
1A/div.
2A/div.
1μs/div. 2μs/div.
CH1:
CH1: VOUT/AC
VOUT/AC 100mV/div.
50mV/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2
CH3: VSW2 20V/div.
10V/div.
CH4: IL
CH4: IL
2A/div.
2A/div.
2μs/div. 2μs/div.
CH1:
VOUT/AC CH1:
200mV/div. VOUT/AC
100mV/div.
CH4: IOUT
1A/div. CH4: IOUT
500mA/div.
400μs/div. 400μs/div.
CH1: VOUT
5V/div.
CH1:
VOUT/AC
CH2: VSW1
100mV/div. 10V/div.
CH3: VSW2
CH4: IOUT 5V/div.
1A/div. CH4: IL
5A/div.
400μs/div. 4ms/div.
CH1: VOUT
5V/div. CH1: VOUT
5V/div.
CH2: VSW1
10V/div. CH2: VSW1
10V/div.
CH3: VSW2 CH3: VSW2
10V/div. 20V/div.
CH4: IL CH4: IL
5A/div. 10A/div.
10ms/div. 2ms/div.
200μs/div. 2ms/div.
2ms/div. 1ms/div.
CH1: VOUT
5V/div.
CH1: VOUT
CH2: VSW1 5V/div.
10V/div. CH2: VSW1
10V/div.
CH3: VSW2
CH3: VSW2
5V/div.
10V/div.
CH4: IL
CH4: IL
2A/div.
2A/div.
1s/div. 20ms/div.
CH1: VOUT
5V/div.
CH1: VOUT
5V/div. CH2: VSW1
CH2: VSW1 10V/div.
10V/div.
CH3: VSW2 CH3: VSW2
10V/div. 10V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
20ms/div. 20ms/div.
I2C VID
VIN = 12V, VOUT = 5V to 9V, IOUT = 2A
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH4: IL
2A/div.
20ms/div.
IN
OUT Bootstrap
Regulator BST1
VCC
On A
Timer
SCL DAC
I2C/OTP
SW1
IF &
SDA A, B, C, D
Register
FET Sensing B
ALT
ADD GND
Buck-Boost IN
Control Bootstrap
EN Regulator OUT
2MΩ Logic
COMP BST2
Rup
OUT D
Rdown
SW2
SS
PG & OVP C
OV
GND
OC AGND
OPERATION
The MP8862 is a 4-switch, integrated buck- SWA turns on. SWA turns on for a fixed on-time
boost converter that works in constant-on-time period before turning off. Then SWB turns on
(COT) mode with fixed frequency, which again, and the operation repeats. The COMP
provides fast transient response for buck, signal is the error amplifier (EA) output from the
boost, and buck-boost modes. One special VOUT feedback and internal FB reference
buck-boost control strategy provides high voltage (see Figure 5).
efficiency over the full input range and smooth SW1
transient between different modes.
SW2
Buck-Boost Operation
The MP8862 can regulate the output to be IL
above, equal to, or below the input voltage. tON COMP
Figure 3 shows that the 1-inductor, 4-switch
Control by COMP
power structure can operate in buck mode,
boost mode, or buck-boost mode with different Figure 5: Buck Waveform
VIN inputs (see Figure 4).
Boost Mode (VIN < VOUT)
VIN VOUT
When the input voltage is significantly lower
than the output voltage, the MP8862 works in
SWA SWD
boost mode. In boost mode, SWC and SWD
switch for boost regulation. SWB is off, and
SW1 SW2
SWA remains on to conduct the inductor
current.
SWB SWC
SWC remains off with COT control in each
period, while SWD turns on as a complement to
SWC to boost the inductor current to the output.
In each cycle, SWC turns on to conduct the
Figure 3: Buck-Boost Topology inductor current. When the inductor current
rises and reaches VCOMP, SWC turns off and
Boost Buck-Boost Buck SWD turns on. SWC turns off with a fixed off-
SWA On, SWB Off, All FET D On, C Off, time before turning on again. During this period,
SWC and SWD Switching A and B Switching SWD turns on for the current freewheel (see
Switching Figure 6).
VO-SET
VIN Voltage
Boost Boost Buck Buck
DMAX DMIN DMAX DMIN
Figure 4: Buck-Boost Operation Range
Buck Mode (VIN > VOUT)
When the input voltage is significantly higher
than the output voltage, the MP8862 works in
buck mode. In buck mode, SWA and SWB Figure 6: Boost Waveform
switch for buck regulation. SWC is off, and
Buck-Boost Mode (VIN ≈ VOUT)
SWD remains on to conduct the inductor
current. When VIN is close to VOUT, the converter may be
unable to provide enough energy to operate in
SWA works with COT control logic, and SWB buck mode due to SWA’s minimum off time, or
turns on as a complement to SWA. In each the converter may supply too much power to
cycle, SWB turns on to conduct the inductor
current. When the inductor current drops to the
COMP voltage (VCOMP), SWB turns off, and
MP8862 Rev 1.0 www.MonolithicPower.com 19
5/30/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
MP8862 – 22V VIN, 2A IOUT, INTEGRATED BUCK-BOOST WITH I2C INTERFACE
The MP8862 recovers switching once VCOMP Internal Soft Start (SS)
rises above the PSM threshold. The switching Soft start (SS) prevents the converter output
pulse skips based on VCOMP in very light-load voltage from overshooting during start-up.
condition. PSM has a much higher efficiency When the chip starts up, the internal circuitry
than FCCM mode in light load, but the VOUT generates a SS voltage that ramps up from 0V
ripple may be higher due to the group switching to 3.6V. When SS is lower than VREF, the error
pulse. amplifier uses SS as the reference. When SS is
Internal VCC Regulator higher than VREF, the error amplifier uses VREF
as the reference.
The 3.65V internal regulator powers most of the
internal circuitries. This regulator takes VIN and If the output of the MP8862 is pre-biased to a
operates in the full VIN range. When VIN certain voltage during start-up, the IC disables
exceeds 3.65V, the output of the regulator is in the switching of both the high-side and low-side
full regulation. If VIN is less than 3.65V, the switches until the voltage on the internal SS
output decreases with VIN. VCC requires an capacitor exceeds the internal feedback voltage
external 1µF ceramic capacitor for decoupling. (see Figure 9).
Enable Control (EN)
The MP8862 has an enable control pin (EN). EN
Pull EN high to enable the IC. Pull EN low or 90%
VOUT
float EN to disable the IC.
tDELA Y
If EN is pulled down when the output discharge
function is enabled, the MP8862 completely Figure 9: EN On to VOUT > 90% Delay
shuts down after 55ms. The MP8862’s I2C
register value is reset to default only after the Output Constant Current Limit (OCP)
MP8862 completely shuts down. If EN is pulled The MP8862 has a constant-current limit
high within 55ms, the I2C register is not reset, control loop to limit the output average current.
and the MP8862 enables the output with The current information is sensed from switches
previous register setting. A, B, C, and D. Then an average algorithm is
used to calculate the output current.
If the output discharge function is disabled, the
MP8862 completely shuts down once EN is When the output current exceeds the current-
pulled down for more than 100µs, and the limit threshold, the output voltage starts to drop.
MP8862 I2C register is reset after a 100µs If VOUT drops below the under-voltage (UV)
delay. threshold (typically 50% below the reference),
VOUT = 12V (I2C Setting) VOUT = 12V (I2C Setting)
the MP8862 enters hiccup mode or latch-off
mode, according to the I2C setting.
VOUT = 5V (I2C Reset)
In hiccup mode, the MP8862 stops switching
and recovers automatically with 12.5% duty
EN EN Off
< 55ms
cycles. In latch-off mode, the MP8862 stops
EN Off > 55ms switching until the IC restarts (VIN, EN, or EN bit
toggle).
Figure 8: EN On/Off Logic for I2C Register Reset
Over-Voltage Protection (OVP)
Under-Voltage Lockout (UVLO) The MP8862 monitors a resistor-divided
Under-voltage lockout (UVLO) protects the chip feedback voltage to detect output over-voltage.
from operating at an insufficient supply voltage. When the feedback voltage exceeds 160% of
The UVLO comparator monitors the input the target voltage, the over-voltage protection
voltage and enables or disables the entire IC. (OVP) comparator output goes high, and the
output-to-ground discharge resistor turns on.
S Slave Address WR A Register Address K A Write Data K A Write Data K+1 A Write Data K+N A P
Register address to read specified Read register data from current register location
Note:
* These items have one-time programmable (OTP) non-volatile memory. The OTP is reloaded to the I2C register during VIN > UVLO or EN
shutdown.
REGISTER DESCRIPTION
I2C Bus Slave Address
A resistor-divider from VCC to GND can achieve an accurate reference voltage. Connect ADD to this
reference voltage to set different I2C addresses. The internal circuit changes the I2C address
accordingly. Table 1 shows the four voltage thresholds for the four I2C addresses, and recommended
resistor settings.
Table 1: I2C Address Setting via ADD Voltage
ADD Upper ADD Lower I2C Address
ADD Voltage Resistor R4 Resistor R5
(kΩ) (kΩ) Binary Hex
<25%VCC No connection No connection 1101 001 69H
25% to 50% VCC 499 301 1101 011 6BH
50% to 75% VCC 301 499 1101 101 6DH
>75% VCC 100 No connection 1101 111 6FH
VOUT Setting
The registers VOUT_L and VOUT_H set the output voltage and follow the 11-bit direct format below.
Name VOUT
Format Direct, unsigned binary integer
Register Name N/A VOUT_H D[7:0] VOUT_L D[2:0]
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Function N/A Data bit high Data bit low
Default Value
N/A 500 integer
(5V)
The output voltage can be calculated with Equation (1):
VOUT (V) = V / 100 (1)
Where V is an 11-bit unsigned binary integer of VOUT[10:0], and V ranges from 0 to 2047. The VOUT
resolution is 10mV/LSB.
Inside the MP8862, there is a feedback resistor network from OUT to the internal FB reference voltage.
The feedback resistor ratio is VOUT / VFB = 12.5. The output voltage change slew rate is fixed at 1mV/µs.
Refer to the GO_BIT bit when implementing the output voltage change.
VOUT_GO Register
GO_BIT D[0]
The MP8862 can be controlled when to VOUT begins to change. Set GO_BIT to 1 to start the output
change based on the VOUT register. When the VOUT change is complete (internal VREF steps to the goal
of VREF), GO_BIT auto-resets to 0. This prevents a false operation of the VOUT scaling.
Write the output voltage (0x00 and 0x01 registers) first, and then write GO_BIT = 1. VOUT changes
based on the new register setting. GO_BIT resets to 0 when VOUT reaches a new value. The host can
read GO_BIT to determine if the VOUT scaling is finished or not.
The VOUT-to-ground discharge function is enabled when GO_BIT is 1. This can help ramp VOUT from
high to low in light-load condition.
When GO_BIT is 0, VOUT will not change. When GO_BIT is 1, VOUT changes based on the VOUT register
setting. After VOUT scaling finishes, GO_BIT is reset to 0 automatically.
PG_DELAY_EN D[1]
When PG_DELAY_EN D[1] is 0, there is no delay on PG. When PG_DELAY_EN D[1] is 1, PG
experiences a 100µs rising delay. The default value is 0.
IOUT_LIM Register
Set the output current limit threshold.
Name IOUT_LIM
Format Direct, unsigned binary integer
Bit 7 6 5 4 3 2 1 0
Access N/A R/W R/W R/W R/W R/W R/W R/W
Default Value (3A) N/A 60 integer
CTL2 Register
NAME BITS DEFAULT DESCRIPTION
Sets the output voltage compensation vs. the load feature.
00: No compensation
LINE 01: VOUT compensates 100mV @ 2A IOUT
DROP D[7:6] 00 10: VOUT compensates 200mV @ 2A IOUT
COMP 11: VOUT compensates 400mV @ 2A IOUT
The above compensation amplitude is fixed for any output voltage. Line drop
compensation is only enabled for VOUT ≥ 5V.
Sets the output start-up soft-start timer (from 0 to 100%). For 5V output voltage:
00: 300µs
01: 500µs
SS D[5:4] 11 10: 700µs
11: 900µs
The SS slew rate is constant, but changes for different VOUT values.
Status Register
NAME BITS DEFAULT DESCRIPTION
Output power good indication.
PG D[7] X 0: Output power is not good
1: Output power is good
Over-temperature protection indication.
OTP D[6] X 0: Normal state
1: Chip is in over-temperature protection state These status bits
Over-temperature warning indication. indicate instantaneous
value.
OTW D[5] X 0: Normal state
1: Chip is in-over temperature warning state
The chip works in constant-current output mode or constant-
CC_ voltage output mode.
D[4] X
CV 0: CV mode
1: CC mode
Interrupt Register
NAME BITS DESCRIPTION
Over-temperature protection entry indication. When this bit is high,
OTEMPP_ the IC enters thermal shutdown. This bit is not masked, even if
D[7] OTPMSK = 1. OTPMSK = 1 only masks the interrupt pin’s output
ENTER
(ALT).
Die temperature early warning entry bit. When this bit is high, the die
OTWARNING_ temperature is above 120˚C. This bit is not masked, even if
D[6] OTWMSK = 1. OTWMSK = 1 only masks the interrupt pin’s output
ENTER
(ALT). This bit is latched once
Entry of OC or CC current-limit mode. The OC_MSK bit can enable triggered.
OC_ENTER D[5] or disable OC_ENTER and OC_RECOVER alert output.
Write 0xFF to this
Recovery from CC current-limit mode. Recovering from a hiccup will
OC_RECOVER D[4] not trigger this interrupt signal.
register to reset the
interrupt (ALT) pin’s
UVP_FALLING D[3] Output voltage is in under-voltage protection. state.
Over-temperature protection exit. OTPMSK can mask off the ALT of
OTEMPP_EXIT D[2] this bit.
Die temperature early warning exit bit. When the die temperature is
OTWARNING_ lower than 100°C, this bit is set to 1. This bit is not masked, even if
D[1] OTWMSK = 1. OTWMSK = 1 only masks the interrupt pin’s output
EXIT
(ALT).
PG_RISING D[0] Output power good rising edge.
MSK Register
NAME BITS DEFAULT DESCRIPTION
SET OTPMSK = 1 to mask off the OTP alert. OTPMSK = 1 only masks the interrupt
OTPMSK D[4] 0 pin’s output (ALT). This is not the interrupt register, but is similar for other mask bits.
OTWMSK D[3] 0 Masks off the over-temperature warning.
OC_MSK D[2] 0 Masks off both OC/CC entry and recovery.
UVP_MSK D[1] 0 Masks off the output UVP interrupt.
Masks off the PG indication function on ALT.
PG_MSK D[0] 0 1: ALT pin does not indicate a PG event
0: ALT indicates a PG rising event
OTEMPP_ENTER
OTWARNING_ENTER
OC_ENTER
Event
ALT Pin
Active Low
APPLICATION INFORMATION
Component Selection Input and Output Capacitor Selection
Selecting the Inductor It is recommended to use ceramic capacitors
In a buck-boost topology circuit, the inductor plus an electrolytic capacitor for input and
must support buck applications with the output capacitors, to filter the input and output
maximum input voltage, and boost applications ripple current and achieve stable operation.
with the minimum input voltage. Two critical Since the input capacitor absorbs the input
inductance values can be determined according switching current, it requires sufficient
to the buck mode and boost mode current ripple capacitance. For most applications, a 100µF
using Equation (2) and Equation (3): electrolytic capacitor plus a 22µF ceramic
VOUT (VIN(MAX) VOUT ) capacitor are sufficient.
LMINBUCK (2) The output capacitor stabilizes the DC output
VIN(MAX) fREQ IL
voltage. Low-ESR capacitors and a sufficient
VIN(MIN) (VOUT VIN(MIN) ) capacitor value are recommended to limit the
LMINBOOST (3) output voltage ripple. Considering the ceramic
VOUT fREQ IL DC voltage derating, if the output voltage is less
Where fREQ is the switching frequency, and ∆IL than 12V, the minimum COUT should be 22µFx5
is the peak-to-peak inductor current ripple. As a ceramic. If the output voltage is greater than
rule of thumb, the peak-to-peak ripple can be 12V, use a 100µF low-ESR (≤80mΩ) aluminum
set as 0.5A to 1.5A of the inductor current. The electrolytic or polymer capacitor and two 10µF
minimum inductor value for the application must ceramic capacitors.
be higher than both the Equation (2) and The input and output ceramic capacitors must
Equation (3) results. be placed as close as possible to the device.
In addition to the inductance value, to avoid
saturation, the inductor must support the peak
current based on Equation (4) and Equation (5):
VOUT (VIN(MAX) VOUT )
IPEAK BUCK IOUT (4)
2 VIN(MAX) fREQ L
SW2
operation and thermal dissipation. For best L1
SW1
results, refer to Figure 12 and follow the
guidelines below:
1. Place the ceramic CIN and COUT capacitors
close to the IC’s VIN-to-GND and OUT-to- OUT
GND pins, respectively.
VIN
2. Use a large copper plane for PGND.
GND
3. Add multiple vias to improve thermal
dissipation.
4. Connect AGND to PGND.
5. Use short, direct, and wide traces to
connect OUT.
6. Add vias under the IC and routing the OUT Top Layer
trace on both PCB layers (highly
recommended).
7. Use a large copper plane for SW1 and SW2. L1
8. Place the VCC decoupling capacitor as
SW1
SW2
close to VCC as possible.
Notes:
9) The recommended layout is based on the Typical
Application Circuits on page 31.
VIN OUT
GND
Close-Up of Layout
Figure 12: Recommended Layout
16
VIN L1 4.7µH
15
2.8V-22V BST1 SW1
1
IN 13 0 R7
+ C1 BST2 VOUT
C1B C1A C5
100µF 22µF 14 100nF 1V-20V
0.1µF SW2
R3
499kΩ 12
OUT
3 + C2
EN C2A C2B C2C
0.1µF 10µF 10µF 100µF
VCC
C7
22nF
MP8862 EMZJ350ARA101MHA
1.8V
R4
499kΩ 4 R1
ADD 8 100kΩ
R5 9 ALT
VCC I2C Slave SCL 5
301kΩ C3 6
SDA
1µF
AGND GND OC
10 2, 11 7
R2 C6
21.5kΩ 22nF
0 R6 C4 100nF
16
VIN L1 4.7µH
15
2.8V-22V BST1 SW1
1
IN 13 0 R7
+ C1 BST2 VOUT
C1B C1A C5
100µF 22µF 14 100nF 1-12V
0.1µF SW2
R3
499kΩ 12
OUT
3 C2D C2E C2F
EN C2A C2B C2C
0.1µF 22µF 22µF 22µF 22µF 22µF
VCC
C7
22nF
MP8862
1.8V
R4
499kΩ 4 R1
ADD 8 100kΩ
R5 9 ALT
VCC I2C Slave SCL 5
301kΩ C3 6
SDA
1µF
AGND GND OC
10 2, 11 7
R2 C6
21.5kΩ 22nF
PACKAGE INFORMATION
QFN-16 (3mmx3mm)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP8862 Rev. 1.0 MonolithicPower.com 32
5/30/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
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