Scribd
Upload
46 views17 pages

Digital Logic Design DLD Lab Report 2

The document outlines a lab report on the universality of NAND and NOR gates for designing other logic gates in a Digital Logic Design course. It includes tasks for verifying AND, OR, and NOT functions using both NAND and NOR gates, as well as post-lab designs for NOR, XOR, and XNOR gates using NAND gates and vice versa. The report is submitted by two students and includes detailed input-output tables for each logic function tested.

Uploaded by

salwamir51621
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
46 views17 pages

Digital Logic Design DLD Lab Report 2

The document outlines a lab report on the universality of NAND and NOR gates for designing other logic gates in a Digital Logic Design course. It includes tasks for verifying AND, OR, and NOT functions using both NAND and NOR gates, as well as post-lab designs for NOR, XOR, and XNOR gates using NAND gates and vice versa. The report is submitted by two students and includes detailed input-output tables for each logic function tested.

Uploaded by

salwamir51621
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Submitted By: Syed Asfar Ahmad Bukhari

Muhammad Faisal

Roll No. SP21-BSE-088


SP21-BSE-020

Section: C

Department: Software Engineering

Course: DLD (Digital Logic Design)

Submitted To: Muhammed Mohsin


LAB # 2
To Explain the Universality of NAND and NOR GATES in Order to
Design Other Logic Gates
Objectives:
• To construct various logic gates using NAND gates
• To construct various logic gates using NOR gates

Part 1 - Implementing any logic expression by using only NAND gates


Lab Tasks Part - 1:
Lab Task 1:
(Verification of AND function)

A (AB)’
AB
B

Inputs
Outputs
A B
0 0 0
0 1 0
1 0 0
1 1 1

Page 2 of 17
Lab Task 2:
(Verification of OR function)

A’
A

(A’B’)’=A+B

B
B’

Page 3 of 17
Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 1

Lab Task 3:
(Verification of NOT function)

A A’

Input
Output
A
0 1
1 0

Page 4 of 17
Part 2 - Implementing any logic expression by using only NOR gates
Lab Tasks Part - 2:
Lab Task 1:
(Verification of AND function)

A’
A

(A’+B’)’= A.B

B
B’

Page 5 of 17
Inputs
Outputs
A B
0 0 0
0 1 0
1 0 0
1 1 1

Lab Task 2:
(Verification of OR function)

A (A+B)’
A+B
B

Inputs
Outputs
A B
0 0 0

Page 6 of 17
0 1 1
1 0 1
1 1 1

Lab Task 3:
(Verification of NOT function)

A A’

Input
Output
A
0 1

Page 7 of 17
1 0

Post Lab:
1) Design NOR, XOR and XNOR gate Using NAND gate only.
• NOR using NAND:

Page 8 of 17
Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 0

Page 9 of 17
• XOR using NAND:

Page 10 of 17
Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 0

• XNOR using NAND:

Page 11 of 17
Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 1

Page 12 of 17
2) Design NAND, XOR and XNOR gate Using NOR gate only.
• NAND using NOR:

Page 13 of 17
Inputs
Outputs
A B
0 0 1
0 1 1
1 0 1
1 1 0

• XOR using NOR:

Page 14 of 17
Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 0

Page 15 of 17
• XNOR using NOR:

Page 16 of 17
Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 1

Page 17 of 17

You might also like