Analog Integr Circ Sig Process (2016) 87:379–387

DOI 10.1007/s10470-016-0730-4

A CMOS low power fast-settling AGC amplifier based

on integrated RSSI
Chunfeng Bai1,2 • Jianhui Wu1,2 • Meng Zhang1,2

Received: 28 October 2015 / Revised: 9 March 2016 / Accepted: 31 March 2016 / Published online: 12 April 2016
Ó Springer Science+Business Media New York 2016

Abstract This paper presents a low power CMOS feed- which is vastly used for its high linearity and well-defined
forward automatic gain control (AGC) amplifier based on loop dynamics [1]. However, large system time constant is
an integrated received signal strength indicator (RSSI) with needed to obtain stable loop [2], leading to slow AGC
process-variation tolerance. Low ripple high dynamic RSSI convergence and consequently unfitness for fast AGC
and fast settling AGC are both achieved with a power- settling applications such as Bluetooth low energy (BLE).
efficient implementation. Raised feedforward AGC BLE standard, which has been used widely in smart phones
amplifier also gets superior linearity to cascade ones due to and tablet devices, is proving to be a strong candidate for
its high dynamic range detection to input signals. No wireless interface in the approaching world of Internet of
external component is needed and this design was fabri- Things. Compared with traditional Bluetooth, BLE speci-
cated in 0.18 lm CMOS process. The measurement results fies more relaxed system requirement to permit low power-
show that RSSI gains at least 60-dB log-linear range and cost realizations, while the AGC settling must be done in
the AGC convergence time is less than 7.8-ls for a 2 MHz 8 ls after each frequency hopping [3–5]. The feedforward
signal. It draws 1.1 mA from a 1.5 V supply and obtains AGC amplifier shown in Fig. 1(b) presents much faster
-52-dB THD with 0.7 Vpp output voltage. gain setting [6–9]. Gain of the variable gain amplifier
(VGA) is available as soon as the peak detector (PD) settles
Keywords Low power  CMOS  Fast settling AGC  up. However, its dynamic range is limited by that of PD,
Integrated RSSI  High dynamic range  Feedforward which is exposed to input signal and commonly has narrow
AGC  High linearity dynamic range due to PD’s poor ability of detecting weak
signals. As a result, most feedforward AGC amplifiers
employ cascading to get enough dynamic range, as shown
1 Introduction in Fig. 2. It may result in such a case: VGA1 is set to high
gain mode while both VGA2 and VGA3 are set to lowest
Automatic gain control (AGC) amplifier is an essential gain mode, aggravating the overall linearity.
block to enlarge the dynamic range of a receiver. Fig- This paper shows a new CMOS feedforward AGC
ure1(a) shows a conventional feedback AGC amplifier, amplifier using successive detection logarithmic amplifier
(SDLA) [10] for power estimation. SDLA is an excellent
analog realization of received signal strength indicator
& Jianhui Wu (RSSI), which is a necessity of BLE receiver for link
wjh@[Link] quality monitoring and location estimation. SDLA can
1
sense as small signals as the noise floor of the signal chain
National ASIC System Engineering Research Center,
and exhibits intrinsic high dynamic range. Therefore, one-
Southeast University, Nanjing 210000,
People’s Republic of China step feedforward AGC can be achieved and consequently
2 signals just need to go through required gain stages to the
Jiangsu Provincial Key Laboratory of Sensor Network
Technology, Southeast University, Nanjing 210000, final stage as shown in Fig. 3. As large dynamic range
People’s Republic of China input signals can be ’watched’ ahead, main voltage gain

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380 Analog Integr Circ Sig Process (2016) 87:379–387

Fig. 1 Architecture of a feedback AGC and b feedforward AGC

amplifier

Fig. 4 Architecture of proposed feedforward AGC amplifier for BLE

receivers

offers dB-linear output voltage with respect to input power

Fig. 2 Structure of a typical cascade feedforward AGC amplifier due to its piecewise approximation to logarithmic function.
The output has ripples and the smoothness trades off with
the settling time, hence a ripple-tolerant gain computation
(RTGC) module is designed to implement coarse gain
setting according to the fast settling RSSI out with conse-
quently high ripple (FSROHR), which is a pre-filtered
RSSI output. Therefore, fast AGC convergence and accu-
rate RSSI can be both obtained. Moreover, the addition of
RTGC circuit and switch to the raised high dynamic inte-
grated RSSI constitutes proposed coarse gain control
amplifier, which is appealing to BLE owning to the saving
Fig. 3 Signal path with strong input applied to proposed AGC of power. Such RSSI can watch large dynamic range sig-
amplifier nals, hence one-step gain control is available. The RTGC
module switches in corresponding stages of LA in a
can be firstly assigned to the last stage with high linearity, feedforward loop according to the FSROHR, obtaining a
which improves the overall linearity. The limiting ampli- fast settling coarse gain control with the step of gain of LA
fiers (LAs) in RSSI also serve as fixed gain stages of the (12-dB). The fine gain control stage is fed on largish sig-
AGC circuit, gaining a power-efficient AGC topology. nals with reduced dynamic range, which relaxes the
Low ripple output of SDLA settles up slowly and thus is dynamic range requirement to PD. Thus, a normal feed-
unfit for fast-settling AGCs. This contradiction has been forward AGC amplifier is competent and a similar
overcome in proposed design as well. scheme to typical feedforward AGC amplifier is adopted
This paper is organized as follows. The whole archi- [7]. It offers 0–12-dB gain with the step of 3-dB as the
tecture is sketched in Sect. 2. A comparative study to preceding stage has provided 0–60-dB gain with the step of
signal detection of PD and SDLA as well as the design of 12-dB.
raised fully integrated RSSI is presented in Sect. 3. Sec-
tion 4 gives circuit level description of raised AGC
amplifier. The measurement results are given in Sect. 5 and 3 Fully integrated RSSI with high dynamic range
a conclusion is drawn in Sect. 6.
3.1 A comparative study to signal detection of PD
and successive detection logarithmic amplifier
2 Architecture of proposed AGC amplifier

The architecture of proposed AGC amplifier with embed- As shown in Fig. 5, PDs are commonly based on uni-
ded RSSI is shown in Fig. 4. The coarse gain control stage lateral device or circuit. Ideally, the charge to the capacitor
is based on a SDLA, which also serves as a high dynamic C is on so long as the voltage on C is lower than the input
RSSI and is indispensable to BLE receivers. Such RSSI voltage. The current source ID provides the discharge path

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Analog Integr Circ Sig Process (2016) 87:379–387 381

Fig. 5 Basic structures of peak

detectors. a Diode based PD,
b Unilateral source-follower
PD, c Unilateral current-mirror
PD

and it must satisfy (1) to assure small enough droop strength from its sensitivity to the limiting output power
according to analysis in [11]. (10logððA2L Þ=0:1Þ dBm), which will be detailed below.
ID \ 2CfL Dmax ð1Þ Each rectifier along with the LPF network is equivalent to
a PD getting the amplitude of its input voltage, as shown in
Here fL denotes the lower frequency boundary of detected Fig. 6. The input voltage of each PD is separately labeled as
signal and Dmax is the allowed droop for PD. Detection Vin , VO1 , VO2 , VO3 , VO4 and VO5 , whose amplitudes, except
error mainly derives from this droop and the delayed that of Vin , are all limited to AL as the amplitude of Vin
charging due to limited bandwidth of the amplifier A. increases, as presented in Fig. 7(a). The sum of those
Equation (1) indicates that ID need to be kept sufficiently amplitudes is exactly the RSSI out, which approximately
small to minimize the droop. However, PD turns into a varies logarithmically with the increasing of the input
buffer driving a large capacitor when the output is close to voltage amplitude, as will be proved below. In Fig. 7, A1 ,
the input or weak input is applied. Smaller ID results in A2 , A3 , A4 , A5 and A6 respectively denote where the input
lower output pole, hence the bandwidth of A should be voltage amplitudes are in the horizontal axis when the PDs
much lower to obtain a stable loop, which further increases successively saturate due to the limiting of corresponding
the error due to the delayed charging. Besides, the severe LAs. These saturation points can be estimated by Eq. (2).
DC-offset in deep-submicron CMOS process brings about AL i
more process uncertainty. Hence, CMOS PD generally Ai ¼ G i ¼ 1; 2; 3; 4; 5; 6 ð2Þ
G6
operates well just as the input signal power exceeds
20 dBm. We can see that the saturation point grows geometrically
In contrast, SDLA can sense quite weak signal so long along the horizontal axis while the corresponding RSSI
as the LA chain has sufficiently high gain and low noise output increases approximately linearly from 0 to 6AL at
performance. For a typical SDLA serving as a RSSI with the step of AL , which means a piecewise approximation to
its topology shown in Fig. 6, the minimum detectable input the logarithmic law and is more visible in Fig. 7(b).
voltage can be expressed as AL =ð5GÞ, where AL and G Associated error is defined as
respectively denotes the limiting output voltage amplitude Ei ¼ OUTRSSI ðAi Þ  iAL i ¼ 1; 2; 3; 4; 5; 6 ð3Þ
and the gain of LA. The LAs operate at the intermediate
frequency (IF) and hence is immune to the severe DC- which is a diminishing value. As can be seen in Fig. 7, E6
offset in CMOS process. Moreover, such RSSI possesses is equal to 0 and E1 is the maximum. E1 produces the
dB-linear output voltage with respect to the input signal maximum error, which can be calculated as in (4).

Fig. 6 Structure of a typical

successive detection RSSI

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with gain insensitive to process-variations is required here.

Secondly, variations of the resistor R1 lead to translations of
RSSI curve as illustrated in the Fig. 8(b). Those two prob-
lems must be tackled for an accurate integrated RSSI.
In order to reduce gain variation with a low power
approach, source-degenerated amplifiers is employed for
LAs. The first stage LA shown in Fig. 9(a) owns superior
noise performance to succeeding LAs shown in Fig. 9(b) as
the current sources 2I0 in first stage LA only contribute to
common-mode (CM) noise. The gain of these two types of
LAs can be obtained as in (5).
RL gm1  RS RL T
G¼  ¼  ð5Þ
RS 1 þ gm1  RS RS 1 þ T
where gm1 denotes transconductance of the input pair (M1a
and M1b ). We define that T ¼ gm1  RS , which is a process
variation dependent variable and assumed to vary about
30 %. Basing on the differential expression in (6) and
expected gain of 12 dB, we can obtain that minimum T of
2.3 is required to keep the gain error within 0:2-dB. If RS
has a typical value of 8 kX, required gm1 is just 286:9 ls,
which is easily achievable. The limiting output voltage
amplitude of LA is equal to I0  RL , which stays constant
when I0 is made to be an adaptive current source varying
against the variation of resistors.
DG RS DT
¼  ð6Þ
G RL Tð1 þ TÞ
The translation of RSSI curve derives from process-varia-
tion of the resistor R1 in Fig. 6, which can be compensated
Fig. 7 Output voltage of SDLA versus its input voltage amplitude in
by that of another matched resistor. As shown in Fig. 10,
a a linear coordinate and b a semi-logarithmic coordinate
the employed CMOS rectifier consists of two unbalanced
source-coupled pairs with different gate W / L ratios [13].
! The maximum output current is expressed in (7). This
  X5
AL þ E1 1 current converts into the output voltage of RSSI on R1
¼ 20log 1 þ ¼ GdB  ðG  1ÞdB
AL dB G j when the input voltage is below the sensitivity.
j¼1

ð4Þ Ilimit ¼ 2ðK  1Þ=ðK þ 1Þ  Itail ð7Þ

Therefore, the maximum error is 2.46-dB for a general Here Itail denotes the tail current source of the unbalanced
gain of 12-dB. Thus, such a successive detection RSSI can source-coupled pair and K is the gate W / L ratio of the
achieve 72-dB log-linear range with less than 2.5-dB error
in theory. In fact, OUTRSSI ðAi Þ in (3) is lower than
expectation due to limit bandwidth of rectifiers and inser-
tion loss of filtering. Hence the real linear error is much
smaller than 2.46-dB.

3.2 Integrated RSSI with process-variation

tolerance

The LAs are cascaded in AC-coupling to avoid the spread of

DC-offsets. However, there exist two problems for such
RSSI. Firstly, gain variations of LAs bring about slope error Fig. 8 a RSSI output curves as the gain of LA varies. b RSSI output
to RSSI curve as shown in Fig. 8(a) [12]. As a result, LA curves as R1 varies

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Analog Integr Circ Sig Process (2016) 87:379–387 383

Fig. 9 Circuits of a low noise

first stage LA and b succeeding
LAs. c Transistor sizes and
parameter values

input pair. As shown in Fig. 10, Itail is compelled to vary

against variation of resistor R3 , which should be deliber-
ately matched with the summing resistor R1 in Fig. 6. As a
result, the output voltage of RSSI for inputs below sensi-
tivity can be fixed. The slope determined by the gain of LA
can also be fixed as proved above. Therefore, an integrated
RSSI with process variation tolerance can be achieved.

4 Fast settling coarse gain control based on RSSI

Low ripple RSSI output is achieved by employing cas-

Fig. 10 Schematic of the full-wave rectifier with the bias current cade LPF as shown in Fig. 11. However, the lowered
generator tracking speed makes it unsuitable for fast gain setting.

Fig. 11 Full circuit of proposed fast settling coarse gain control amplifier based on integrated RSSI

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Table 1 Transistor dimensions and component values for the circuit

in Fig. 13
Transistor/component Value

I1, I2 40 lA
I3, I4 2:5 lA
M1, M2 32 lm/0:4 lm
M3, M4 1 lm/2 lm
M5, M6, M7, M8 64 lm/1 lm
RS 4.5–10 kX
RL 10 kX
CC1 ,CC2 1 pF

Fig. 12 Ripple tolerant gain control module employing hysteresis

comparator

Fig. 14 Chip photograph of the proposed AGC amplifier & RSSI

attendant high ripple. The RTGC module owns flash ADC

structure and the hysteresis width of HCs can be obtained
as in (8), which must cover the maximum ripple amplitude
of FSROHR. Besides, The bandwidth of the first LPF
network should guarantee fast settling RSSI out while it
should also be much lower than the lower frequency limit
of signal.
Fig. 13 Circuit of high linearity PGA in proposed feedforward AGC R5
WHC ¼ VDD ð8Þ
amplifier R5 þ R6

Hence using FSROHR is the only approach. The coarse

gain control is realized by switching in the output voltage
of corresponding LA to the final stage according to the 5 Highly linear PGA for fine gain control
indicating of FSROHR. Proposed RSSI serves as a high
dynamic range RMS detector in the coarse gain control Preceding coarse gain control circuits reduce the dynamic
circuit, and consequently required gain can be set in one range of input signals and hence the traditional feedforward
step. The LAs in RSSI chain also serve as the fixed gain AGC circuit can be qualified. A highly linear pro-
amplifiers of coarse gain control stage, leading to a com- grammable gain amplifier (PGA) is shown in Fig. 13,
pact circuit share. From the view of AGC amplifier, the which offers 012-dB gain at the step of 3-dB. PGA
RSSI function is obtained for free, saving what should be basically utilizes the linear voltage-current response of
cost to realize a digital RSSI. resistor to achieve high linearity [14]. The gm -boost tech-
The errors due to the high ripples of FSROHR hardly nique provides enough drive capability to transfer the input
affect the coarse gain control, but the gain computation voltage signals to a linear device RS , meanwhile, the
module must tolerate the ripples to obtain stable gain feedback loop (M1, M3 and M5) also creates a low
control word. Therefore, hysteresis comparators (HCs), impedance node (C in Fig. 13) to absorb the linear current
whose circuit is shown in Fig. 12, are used to tolerate signal on RS . The distortion caused in this process is

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Fig. 15 Measured RSSI response versus the input signal strength at

2 MHz

Fig. 17 Single-ended output spectrums for different input signal

amplitudes at 2 MHz (0.7-Vpp single-ended output)

where gm1 , gm3 and gm5 are the transconductance of M1, M3

and M5, respectively. CA , CB and CC represent the equivalent
parasitic capacitance of node A, B and C, respectively. rOA
denotes the equivalent output resistance of node A, and Cgs3
is the capacitance between gate and source of M3. The node
A provides the dominating pole while the node B contributes
a pole and a LHP zero, which can be neutralized by each
other if an appropriate compensating capacitor is inserted
Fig. 16 Measurements of AGC convergence performance (single- between node A and node B. This means that little current is
ended). a Attack time of proposed AGC amplifier as input has a step needed by M3 to form a stable loop without reducing the loop
increase, b decay time of propose AGC convergence performance
bandwidth. The main transistors dimensions and compo-
(single-ended)
nents values are listed in Table 1.

suppressed by the local feedback loop, which has the loop

gain expressed as 6 Experimental results and analysis
 
gm5 gm1 rOA gm3 þ sCgs3
LG     h  i Proposed AGC amplifier with embedded RSSI for BLE
1 þ sCA rOA gm1 þ sCC gm3 þ s CB þ Cgs3 was fabricated in a standard 0.18-lm CMOS process and
ð9Þ requires none external components. The capacitors C1 and

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Table 2 Summary and comparison of principle parameters

Parameter This work Single stage AGC AGC RSSI & PGA
(RSSI ? AGC) AGC (2010) [7] (2013) [8] (2015) [15] (2005) [12]

RSSI range & error 60 & 1 dB No RSSI No RSSI No RSSI 80 & 0.7 dB
Technology 180 nm CMOS 350 nm CMOS 130 nm CMOS 180 nm CMOS 350 nm CMOS
Area (mm2 ) 0.54 – 0.54 0.6 2.25 (including pads)
Power consumption 1.65 mW & 1.5 V 2.4 mW & 1.8 V 5.2 mW & 1.2 V 15 mW & 3 V 15 mW & 3 V
AGC output voltage 0.7 Vpp 0.4 Vpp 0.78 Vpp – Ocp ¼ 6 dBm ð0:63 VppÞ
Bandwidth 10 MHz 100 MHz 10 MHz – 74 MHz
Gain range 0–71 dB 0–22 dB 10–58 dB 0–70 dB -7.8 to 80 dB
AGC Attack time 7:8 ls & 2 MHz 0:8 ls & 20 MHz 2:8 ls & 5 MHz 1:25 ls –
Decay time 5:8 ls & 2 MHz 2:4 ls & 20 MHz
THD 52 to 45 dB & 0.7 Vpp 50 to 45 dB&0.6 Vpp 50 to 37 dB [-47.87 dB OIP3 = 13.7 dBm
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
Input referred noise 58 nV= Hz* 44 nV= Hz* 82nV= Hz / /

* Simutation results

C2 in Fig. 11 are implemented by NMOSs, whose gate- settling time product at worst case is 15.6, comparable to
source and gate-drain capacitance has high efficiency in those of other feedforward AGCs. The cascade feedfor-
chip area. The whole circuit (including I-path and Q-path) ward AGC amplifier reported in [8] executes independent
occupies 0:6mm  0:9mm on the chip, as shown in Fig. 14. gain control before each gain stage by switching in or
It draws 1.1 mA current from a 1.5 V supply and gets a bypassing corresponding gain stages according to the
minimum bandwidth of 10 MHz when driving a 2-pF indication of comparators. This is also a trying to solve the
capacitive load. The chip is bonded to a PCB for test. problem of feedforward AGC discussed in Sect. 1. How-
In Fig. 15, it is shown that the measured RSSI outputs of ever, large input signals have to pass through too many
two different chips basically coincide with the simulated switches, still resulting of bad linearity at low gain modes.
results as the input ranges from -60 to 5 dBm. It can Moreover, proposed RSSI-AGC integrated circuit con-
achieve a 60-dB log-linear range (from -57 to 3 dBm) sumes much lower power and needs none external
within the error of less than 1-dB. Such embedded RSSI is component.
qualified for BLE as it can sense more than 80-dB linear
range with another required 20-dB gain provided by the RF
front end. Previously reported analog RSSI [12] based on
SDLA owns 80-dB linear range as its LA chain has six gain 7 Conclusion
stages. However, five stages of LAs are included in pro-
posed SDLA. Low ripple process-variation tolerant high dynamic range
Fast AGC convergence is also obtained together with a RSSI and fast coarse gain control are both achieved by
high dynamic range RSSI as shown in Fig. 16. At an input making proper modification to SDLA. A power-efficient
frequency of 2 MHz, the attack time and decay time are structure with no need for external component is hence
7.8-ls and 5.8-ls, respectively. Shorter settling time is not obtained. Reasonable overall linearity derives from two
profitable as the AGC circuit may respond to interferences aspects: firstly raised RSSI can ’watch’ the strength of
unexpectedly or even smooth low frequency signals. input signals with a high dynamic range, hence required
The harmonic distortion (HD) analysis to differential gain stages can be determined in advance; secondly, a low
output of proposed AGC amplifier is executed in a digital power linearity-boosted amplifier serves in the last stage
oscilloscope. For a 0.7-Vpp AGC output voltage, calcu- for fine gain control. Therefore, a low power low cost AGC
lated THD can reach 52 dB. Moreover, the THD main- amplifier with embedded RSSI is achieved, which owns
tains below 45 dB for an input signal varying in 40-dB improved linearity. It can be used in full integrated BLE
range applied to the raised amplifier. The HD measurement receivers.
results for input power of 10 and 45 dBm at the fre-
quency of 2 MHz are shown in Fig. 17. Acknowledgments This work was supported by The Scientific
Research Foundation of Graduate School of Southeast University
The performance of proposed AGC amplifier with under the Project Number of YBJJ1557, and The National Natural
embedded RSSI is summarized in Table 2 along with Science Foundation of China under the Project Numbers of 61401090
several previously published designs. The frequency and 61574035.

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