Digital Systems - 0
Pere Palà Schönwälder
iTIC http://itic.cat
February 2025
Introduction
I VHDL: VHSIC Hardware Description Language
I VHSIC: Very High Speed Integrated Circuit
I IEEE Standard (Institute of Electrical and Electronic
Engineers)
I VHDL-87, VHDL-93, VHDL-2002
std logic 1164
I Standardized package : std_logic_1164
type std_ulogic is ( ’U ’ , -- U n i n i t i a l i z e d
’X ’ , -- Forcing Unknown
’0 ’ , -- Forcing zero
’1 ’ , -- Forcing one
’Z ’ , -- High I m p e d a n c e
’W ’ , -- Weak Unknown
’L ’ , -- Weak zero
’H ’ , -- Weak one
’-’ ); -- Don ’ t care
I This is used in almost any VHDL file
library ieee ;
use ieee . std_log ic_1164 . all ;
Example: AND gate
library ieee ;
use ieee . std_log ic_1164 . all ;
Entity
entity and_gate is
port ( a , b : in std_logic ;
y : out std_logic );
end and_gate ;
architecture logic_and of and_gate is Architecture
begin
y <= a and b ;
end ;
I entity: connections to the outside world
I architecture: what it does
Identifiers
I Case insensitive: AND is the same as aNd
I Reserverd words
I entity, or, and, register, begin, ... The editor
usually highlights them!
I Only alphabetic letters (‘Aa’ to ‘Zz’), decimal digits (‘0’ to
‘9’) and the underscore character (‘ ’)
I Must start with an alphabetic letter
I May not end with an underscore character
I May not include two successive underscore characters
Example: Full Adder
Example: Full Adder
library ieee ;
use ieee . std_log ic_1164 . all ;
entity full_adder is
port ( a , b , c_in : in std_logic ;
s , c_out : out std_logic );
end full_adder ;
architecture arch_1 of full_adder is
signal temp : std_logic ;
begin
temp <= a xor b ;
s <= temp xor c_in ;
c_out <= ( a and b ) or ( c_in and temp );
end ;
All assignments are concurrent! This is exactly the same:
s <= temp xor c_in ;
c_out <= ( a and b ) or ( c_in and temp );
temp <= a xor b ;
Testing. Classical instantiation
library ieee ; begin
use ieee . std_log ic_1164 . all ; dut : my_adder port map
(a = > t_a ,
entity full_adder_tb is b = > t_b ,
end full_adder_tb ; c_in = > t_c_in ,
s = > t_s ,
architecture behav of c_out = > t_c_out );
full_adder_tb is process
component my_adder begin
port (a , t_a <= ’0 ’;
b, t_b <= ’0 ’;
c_in : in std_logic ; t_c_in <= ’0 ’;
s, wait for 1 sec ;
c_out : out std_logic ); t_a <= ’0 ’;
end component ; t_b <= ’1 ’;
for dut : my_adder use t_c_in <= ’0 ’;
entity work . full_adder ; wait for 1 sec ;
wait ;
signal t_a , t_b , t_c_in , end process ;
t_s , t_c_out : std_logic ; end behav ;
Testing. Direct instantiation
begin
-- Direct DUT i n s t a n t i a t i o n
dut : entity work . full_adder
port map ( a = > t_a ,
b = > t_b ,
c_in = > t_c_in ,
library ieee ;
s = > t_s ,
use ieee . std_log ic_1164 . all ;
c_out = > t_c_out );
-- S t i m u l u s process
entity full_a dder_tb 2 is
process
end full_ad der_tb2 ;
begin
t_a <= ’0 ’;
architecture behav of
t_b <= ’0 ’;
full_ adder_t b2 is
t_c_in <= ’0 ’;
signal
wait for 1 sec ;
t_a , t_b , t_c_in ,
t_a <= ’0 ’;
t_s , t_c_out : std_logic ;
t_b <= ’1 ’;
t_c_in <= ’0 ’;
wait for 1 sec ;
wait ;
end process ;
end behav ;
Testing/2
I $ ghdl -a full_adder.vhd
I $ ghdl -a full_adder_tb.vhd
I $ ghdl -e full_adder_tb
I $ ghdl -r full_adder_tb --vcd=full_adder_tb.vcd
I $ gtkwave full_adder_tb.vcd &
