Testing Digital Systems I

Testing Digital Systems I

Lecture 12:
Design for Testability

Instructor: M. Tahoori

Copyright 2010, M. Tahoori TDS I: Lecture 12 1

History
„ During early years, design and test were separate
„ The final quality of the test was determined by keeping track of the
number of defective parts shipped to the customer
„ Defective parts per million (PPM) shipped was a final test score.
„ This approach worked well for small-scale integrated circuit
„ During 1980s, fault simulation was used
„ Failed to improve the circuit’s fault coverage beyond 80%
„ Increased test cost and decreased test quality lead to DFT
engineering

EE141TDS I: Lecture 12 2

Lecture 12 1
 Testing Digital Systems I

History
„ Various testability measures & ad hoc testability
enhancement methods
„ To improve the testability of a design
„ To ease sequential ATPG (automatic test pattern
generation)
„ Still quite difficult to reach more than 90% fault coverage
„ Structured DFT
„ To conquer the difficulties in controlling and observing
the internal states of sequential circuits
„ Scan design is the most popular structured DFT approach
„ Design for testability (DFT) has migration recently
„ From gate level to register-transfer level (RTL)
Copyright 2010, M. Tahoori TDS I: Lecture 12

Design for Testability (DFT)

„ Design techniques that are used to make testing of

the resulting product economical
„ Testability
„ Easy to generate test patterns with “high” fault coverage
within reasonable time

Copyright 2010, M. Tahoori TDS I: Lecture 12 4

Lecture 12 2
 Testing Digital Systems I

Challenge
„ “Right” DFT technique to choose
„ Observability and controllability play a major role in
influencing the testability of a given IC
„ Observability refers to the ease with which the state of internal
signals can be determined at the circuit output leads.
„ Controllability refers to the ease of producing a specific internal
signal value by applying signals to the circuit input leads
„ Improve testability
„ Introduce test points, that is, additional circuit inputs and outputs to
be used during testing

Copyright 2010, M. Tahoori TDS I: Lecture 12 5

Ad-Hoc DFT Techniques

Feature Ad hoc Technique
Unknown initial state Initialization circuitry
Internal clock Circuitry to disconnect internal clock and substitute
tester clock
Logical redundancy Avoid or add test points
Feedback loops Circuitry to permit tester to break feedback loop
Internally generated signals for Circuitry to permit tester not to allow the tester not
asynchronous set and to allow these signals to set/reset flip-flops during
Reset inputs of flip-flops test
Wired logic Avoid
Bidirectional I/O pins Circuitry to permit tester to configure them to
operate in one direction
Tristate drivers and pass Circuitry to permit tester to configure them so that
transistors only 1 driver drives the bus

Copyright 2010, M. Tahoori TDS I: Lecture 12 6

Lecture 12 3
 Testing Digital Systems I

Scan Architecture

Copyright 2010, M. Tahoori TDS I: Lecture 12 7

Structured DFT

„ Difficulty with the ad hoc testability techniques

„ The requirement of adding extra control inputs or
observation outputs
„ Structured DFT techniques
„ Permit access to internal nodes of a circuit without
requiring a separate external connection for each node
accessed
„ At the cost of additional internal logic circuitry used
primarily for testing

Copyright 2010, M. Tahoori TDS I: Lecture 12 8

Lecture 12 4
 Testing Digital Systems I

Scan Features
„ Very few (from 1 to 4) additional external connections are
used to access many internal nodes
„ Typically all of the system bistable elements
„ Serialization of the test data
„ Otherwise, a large number of I/O pins will be required to control and
observe logic values stored in each system bistable
„ Test data must be transferred serially or scanned in and out
of the circuit being tested.
„ The change from normal system operation to test mode can
be controlled by a level test-mode signal or by a separate
test clock signal

Copyright 2010, M. Tahoori TDS I: Lecture 12 9

Scan Features

„ Most important advantage

„ sequential circuit test pattern generation is not required
„ Test pattern generation need only be done for the
combinational circuits
„ the bistable elements can be accessed and tested directly
„ converting between parallel and serial data
„ Two approaches
„ shift register (scan-path method)
„ multiplexer

Copyright 2010, M. Tahoori TDS I: Lecture 12 10

Lecture 12 5
 Testing Digital Systems I

Scan Design
„ Circuit is designed using pre-specified design rules.
„ Test structure (hardware) is added to the verified design:
„ Add a test control (TC) primary input.

„ Replace flip-flops by scan flip-flops (SFF) and connect to form

one or more shift registers in the test mode.

„ Make input/output of each scan shift register
controllable/observable from PI/PO.
„ Use combinational ATPG to obtain tests for all testable
faults in the combinational logic.
„ Add shift register tests and convert ATPG tests into scan
sequences for use in manufacturing test.

Copyright 2010, M. Tahoori TDS I: Lecture 12 11

Scan Design Rules

„ Use only clocked D-type of flip-flops for all state

variables.
„ At least one PI pin must be available for test;
more pins, if available, can be used.
„ All clocks must be controlled from PIs.
„ Clocks must not feed data inputs of flip-flops.

Copyright 2010, M. Tahoori TDS I: Lecture 12 12

Lecture 12 6
 Testing Digital Systems I

Scan Path Method

„ Circuit with two modes of operation
„ Normal functional mode
„ Test mode
„ Circuit bistables are interconnected into a shift register

„ With the circuit in test mode

„ It is possible to shift an arbitrary test pattern into the bistables
„ By returning the circuit to normal mode for one clock period
„ The combinational circuitry acts upon the bistable contents and
primary input signals,
„ Stores the results in the bistables
„ Circuit is then placed into test mode
„ It is possible to shift out the contents of the bistables and
„ Compare these contents with the correct response

Copyright 2010, M. Tahoori TDS I: Lecture 12 13

Scan Path Methods for

Flip-Flop Machines

Copyright 2010, M. Tahoori TDS I: Lecture 12 14

Lecture 12 7
 Testing Digital Systems I

Scan Path Methods for Flip-Flop Machines

„ Each of the circuit flip-flops is replaced by

„ Multiplexed data flip-flop (MD flip-flop)
MUX D0 0, 2D
T d Q D0
G1 1D & + D1 Q
T 1, 2D
D0 C1 d T
0
D1 1 C2
CK
D1
CK
(a) (b) (c)

„ (a) flip-flop with multiplexer (MUX)

„ (b) multiplexer circuit diagram
„ (c) symbol for multiplexed data flip-flop (MD flip-flop)

Copyright 2010, M. Tahoori TDS I: Lecture 12 15

MD Flip-flop Architectures

„ A multiplexer is placed at the data input of a flip-

flop
„ To permit a selection of two different data inputs
„ d0: (normal system operation)
„ d1: (test mode).
„ The choice of data input is based on the value of
the control input, T.
„ When T=0, data is gated from the d0 input upon an
active clock transition.
„ Data is taken from d1 if T is equal to 1.

Copyright 2010, M. Tahoori TDS I: Lecture 12 16

Lecture 12 8
 Testing Digital Systems I

MD Flip-flop Architectures
„ (a) General structure of a flip-flop finite state machine
„ (b) MD-flip-flop scan path architecture

X1 X1 Z1
Combinational Combinational Circuit
Xn Circuit Z1 Xn Zm
CK Zm
Y1 y1 Y1 y2 Y2 ys Ys
1D y1
C1 0, 2D 0, 2D 0, 2D
SDI SDO
1, 2D 1, 2D 1, 2D
ys Q Q Q
Ys G1 G1 G1
1D
C1 C2 C2 C2

CK
T
(a) (b)

Copyright 2010, M. Tahoori TDS I: Lecture 12 17

MD Full-Scan Design

• Primary inputs (PIs) • Primary outputs (POs)

– the external inputs to the circuit – the external outputs of the circuit
– can be set to any required logic – can be observed
values – are observed directly in
– set directly in parallel from the – parallel from the external outputs
external inputs
• Pseudo primary inputs • Pseudo primary outputs
(PPIs) (PPOs)
– the scan cell outputs – the scan cell inputs
– can be set to any required logic – can be observed
values – are observed serially through scan
– are set serially through scan chain chain outputs
inputs

Copyright 2010, M. Tahoori TDS I: Lecture 12

Lecture 12 9
 Testing Digital Systems I

MD Flip-flop Architectures
„ general structure of a flip-flop finite state machine
„ CK is the clock input,
„ X1, …, Xn are the primary inputs
„ Z1, …, Zm are the primary outputs.
„ There are s D-flip-flops corresponding to internal variables y1, …, ys.
„ scan path architecture using MD flip-flops
„ One additional input, the T input, has been added
„ T = 0: The upper data inputs (y1, …, ys) act as the flip-flop D inputs
„ T = 1: The lower data inputs become the flip-flop D inputs.
„ D = Q
i i-1 for i from 2 to s, and a shift register is formed
„ The primary input Xn is connected to D1 becoming the shift register
input
„ Qs, the shift register output, appears at the primary output Zm.

Copyright 2010, M. Tahoori TDS I: Lecture 12 19

Testing of the combinational logic

1. Setting T = 1 (scan mode)
2. Shifting the test pattern yj values into the flip-flops.
3. Setting the corresponding test values on the Xi inputs.
4. Setting T = 0 and, after a sufficient time for the
combinational logic to settle, checking the output Zk values.
5. Applying a clock signal to CK.
6. Setting T = 1 and shifting out the flip-flop contents via Zm.
„ The next yj test pattern can be shifted in at the same time.
„ The yj values shifted out are compared with the good response
values for yj.

Copyright 2010, M. Tahoori TDS I: Lecture 12 20

Lecture 12 10
 Testing Digital Systems I

Testing of the combinational logic

Don’t care
or random
PI I1 I2 bits

SCANIN S1 S2
TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0000000

PO O1 O2

SCANOUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number of scan flip-flops
Copyright 2010, M. Tahoori TDS I: Lecture 12 21

Testing Flip-Flops in Scan Chain

„ Scan register must be tested prior to application of scan test
sequences
„ To verify the possibility of shifting both a 1 and a 0 into
each flip-flop
„ Shifting a string of 1s and then a string of 0s through the shift
register
„ More complex pattern such as 00110011… (of length nsff+4) may be
necessary
„ To verify that all possible data transitions are possible

„ These tests are often called flush tests

„ Test sequences for scan flip-flops based on checking
experiments
„ Checking experiments are exhaustive tests for sequential circuits and
detect all combinational faults

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Lecture 12 11
 Testing Digital Systems I

Total Scan Test

„ Total scan test length:

„ (ncomb + 2) nsff + ncomb + 4 clock periods.
„ Example:
„ 2,000 scan flip-flops, 500 comb. vectors,
„ total scan test length ~ 106 clocks.
„ Multiple scan registers reduce test length.

Copyright 2010, M. Tahoori TDS I: Lecture 12 23

Issues
„ The MD-flip-flop based scan path architecture does not need
to route any extra clock
„ However, the test signal T has to be routed to all flip-flop
„ Depending on the layout, the routing of the test signal T with proper
skew control limits the speed at which scan shift can be done
„ Scan speeds between 10 MHz to 200 MHz aren’t uncommon

„ Another factor that limits the speed at which the scan chains
can be operated is the amount of power dissipation during
scan

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Lecture 12 12
 Testing Digital Systems I

Two-port Flip-flop Architectures

„ Basic requirement of the scan path

„ Be able to gate data into the system flip-flops from two
different sources
„ Approaches
„ Add multiplexers to the system flip-flops: MD flip-flop
„ Replace each system flip-flop by a two-port flip-flop
„ A flip-flop having two control inputs with the data source
determined by which of the control inputs is pulsed

Copyright 2010, M. Tahoori TDS I: Lecture 12 25

Two-port Flip-flop Architectures

„ Two-port flip-flop
„ When a pulse is applied to C1, data is entered from D1
„ When a pulse occurs at C2, data is entered from D2
D1 D1 1D
& + L1 L2
d Q Q D2 Q
2D
D2 1D 1D
C1 C1 CK1 C1
CK2 C2
CK1 +
CK2
(a) (b)

Copyright 2010, M. Tahoori TDS I: Lecture 12 26

Lecture 12 13
 Testing Digital Systems I

Two-port Flip-flop Scan Architecture

X1 Z1
Xn Combinational Circuit
Zm

y1 Y1 y2 Y2 ys Ys
1D 1D 1D
SDI SDO
2D 2D 2D
Q Q Q
C1 C1 C1
C2 C2 C2

CK
TCK

Copyright 2010, M. Tahoori TDS I: Lecture 12 27

Modified Test Procedure

1. Scan in the test vector yj values via Xn using test clock TCK
2. Set the corresponding test values on the Xi inputs.
3. After sufficient time for the signals to propagate through
the combinational network, check the output Zk values.
4. Apply one clock pulse to the system clock CK to enter the
new values of Yj into the corresponding flip-flops.
5. Scan out and check the Yj values by pulsing test clock TCK

Copyright 2010, M. Tahoori TDS I: Lecture 12 28

Lecture 12 14
 Testing Digital Systems I

Two-Phase Latch Machines

„ General structure of a two-phase double latch finite

state machine
X1
Combinational
Xn Circuit Z1
(L1) (L2) Zm
1D 1D y1
Y1
C1 C1

Ys
1D 1D ys
C1 C1

C0 C1

Copyright 2010, M. Tahoori TDS I: Lecture 12 29

Two-Phase Latch Machines

„ Edge-triggered D-flip-flops have been replaced by two
latches in a master-slave connection
„ The master latches are called L1 latches,
„ Those with inputs from the combinational logic block

„ The slave latches are called L2 latches

„ Whose inputs come from the master latches

„ A clock skew driver is used to derive the control signals CK1

and CK2 of the latches
„ CK1 and CK2 signals do not overlap
„ They are never both equal to 1 at the same time

„ This is to reduce various hazards in sequential circuits

„ Arise when clock and data inputs change at the same time

„ There can be an overlap between CK1 and CK2 to speed up circuit

„ Must be controlled: short path constraints are not violated

Copyright 2010, M. Tahoori TDS I: Lecture 12 30

Lecture 12 15
 Testing Digital Systems I

IBM's LSSD
„ Level Sensitive Scan Design
„ Standard design technique in current use at IBM
„ L1 latch is replaced by a two-port (dual-port) latch
X1 Z1
Xn Combinational Circuit
Zm

y1 Y1 y2 Y2 ys Ys
L1-1 L1-2 L1-s
1D 1D 1D
SDI Q Q Q SDO
2D 2D 2D

C1 C1 C1
C2 C2 C2

CK1
TCK

L2-1 L2-2 L2-s

Q Q Q
1D 1D 1D
C1 C1 C1
CK2

Copyright 2010, M. Tahoori TDS I: Lecture 12 31

Test Application Procedure

1. Scan in the test vector yj values via SDI by applying pulses

alternately to the test clock input TCK and the system clock
input CK2
2. Set the corresponding test values on the Xi inputs.
3. After sufficient time for the signals to propagate through
the combinational network, check the output Zk values.
4. Apply one clock pulse to the system clock CK1 to enter the
new values of yj into the corresponding L1 latches.
5. Scan out and check the yj values by applying clock pulses
alternately to CK2 and TCK.

Copyright 2010, M. Tahoori TDS I: Lecture 12 32

Lecture 12 16
 Testing Digital Systems I

Multiplexer Scan Structures

„ Parallel data can be serialized with a multiplexer rather than
a shift register
„ Use of more than one scan-out point increases the speed of
scanning,
„ But does increase the number of I/O connections required.
„ One possibility for avoiding this increase is to place multiplexers on
output pins to permit some of the output pins to be used both for
system output and for scanning out test data
„ With a multiplexer scan structure, nodes other than latch
outputs can be accessed
„ The scanning operation can take place while the system is operating

Copyright 2010, M. Tahoori TDS I: Lecture 12 33

Multiplexer Scan Structures

X1 Z1
Xn Combinational Circuit
Zm

y1 Y1 y2 Y2 ys Ys
L1 L2 Ls
1D 1D 1D
Q Q Q
C1 C1 C1
CK

MUX
s-1 SDO

1
0
SADR G

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Lecture 12 17
 Testing Digital Systems I

Random Access Scan Design

„ Multiplexer structure improves the observability of a

design
„ But does nothing for the controllability
„ Setting of the system latches can be accomplished with a
demultiplexer
„ Random access scan design
„ Multiplexer to read out bistables (observability)
„ Demultiplexer to set bistables (controllability)
„ Addressable latch

Copyright 2010, M. Tahoori TDS I: Lecture 12 35

Traditional Random-Access Scan Architecture

PI Combinational logic PO
All scan cells are
organized into a
SC SC … SC two-dimensional
array. A ┌ log2n ┐ -
Row (X) decoder

CK
SC SC … SC SI bit address shift
SCK register, where n is
…
…

SO the total number of

SC SC … SC scan cells, is used to
specify which scan
Column (Y) decoder cell to access.
Address shift register AI

Copyright 2010, M. Tahoori TDS I: Lecture 12

Lecture 12 18
 Testing Digital Systems I

Automated Scan Design

Behavior, RTL, and logic
Rule
Design and verification
violations
Scan design
rule audits
Gate-level
netlist
Combinational Scan hardware
ATPG insertion
Combinational Scan
vectors netlist
Scan sequence Scan chain order Chip layout: Scan-
and test program chain optimization,
generation timing verification
Design and test
data for
Test program manufacturing Mask data

Copyright 2010, M. Tahoori TDS I: Lecture 12 37

Scan Economics
„ Additional circuitry is added to each flip-flop or latch
„ One or more additional circuit pins are required
„ The number of additional pins required for scan test has a direct
relationship with the test time
„ Testing time is increased by the need to shift the test
patterns into the flip-flops serially
„ The modified circuit requires shorter test sets than the original circuit
„ Because only combinational logic test patterns are used

„ There can be a performance penalty.

„ The speed of normal operation may be decreased due to increased
propagation delay in the scan path latches or flip-flops
„ Available functional area can be reduced due to the
increased interconnect
„ Timing closure can be a problem
„ Power dissipation during scan
Copyright 2010, M. Tahoori TDS I: Lecture 12 38

Lecture 12 19
 Testing Digital Systems I

Summary
„ Scan is the most popular DFT technique:
„ Rule-based design
„ Automated DFT hardware insertion
„ Combinational ATPG
„ Advantages:
„ Design automation
„ High fault coverage; helpful in diagnosis
„ Hierarchical – scan-testable modules are easily combined into
large scan-testable systems
„ Moderate area (~10%) and speed (~5%) overheads
„ Disadvantages:
„ Large test data volume and long test time
„ Basically a slow speed (DC) test
Copyright 2010, M. Tahoori TDS I: Lecture 12 39

Lecture 12 20