Performance Comparison of MCML,

PFSCL, and Dynamic CML Gates

with Parametric Analysis in 45 nm
CMOS Technology

M. Sivasakthi and P. Radhika

Abstract In this survey, the comparison results of current mode logic styles such
as MOS Current Mode Logic (MCML), Dynamic Current Mode Logic (DyCML),
and Positive Feedback Source Coupled Logic (PFSCL) gate structures are analyzed.
In this, MCML and PFSCL are static logic circuits. The dynamic logic uses a clock
signal as one of the inputs. The simulation results are performed at a voltage of
1 V and a temperature of 27 °C. The values of power, propagation delay, and power
delay product are obtained and analyzed using the Cadence Virtuoso tool. The power
and the delay values are verified with Monte Carlo simulations using a histogram
plot of 200 samples. The process variations for different corners are simulated and
the parametric analysis with different temperatures are compared for the different
topologies of current mode logic gates. From the comparison, it is clear that Dynamic
CML provides high performance and operates in a low-power environment.

Keywords Current mode logic (CML) · MOS current mode logic (MCML) ·
Inverters · Dynamic current mode logic (DyCML) · Positive feedback source
coupled logic (PFSCL)

1 Introduction

Rapid technological improvement depends mainly on low-power and high-speed

hardware devices. Recent progress in the fields of optical communication and signal
processing has led to improvement in the field of mixed-signal circuit design. In this,
analog circuit determination is restricted by the switching noise that is produced
because of fabricating mixed-signal circuits on the same chip [1]. As for higher
switching noise in CMOS circuits, it is not chosen nowadays in circuit design.

M. Sivasakthi · P. Radhika (B)

Department of Electronics and Communication Engineering, SRM Institute of Science and
Technology, Kattankulathur, Chennai 603203, India
e-mail: [email protected]
M. Sivasakthi
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 451
V. Bindhu et al. (eds.), Proceedings of Fourth International Conference on Communication,
Computing and Electronics Systems, Lecture Notes in Electrical Engineering 977,
https://doi.org/10.1007/978-981-19-7753-4_35
452 M. Sivasakthi and P. Radhika

Along with this, CMOS has more power consumption and hence it cannot be
preferred for high-speed applications [2, 3].
Hence, a new logic style called current mode logic is preferred because of its
low-power consumption and low noise [4]. Three different types of current mode
logic styles are MCML [5, 6], Dynamic CML [7, 8], and PFSCL [9, 10].
The MCML circuit has 2 differential inputs and 2 differential outputs. PFSCL
has one input and produces one output, along with positive feedback in the circuit.
Hence, in Dynamic CML, instead of a constant current source in MCML and PFSCL,
a dynamic current source is used, and hence it achieves low-power consumption. It
operates in the precharge and evaluation mode and has true and complementary input
and output similar to MCML with less propagation delay.
In this survey, the performance comparison of three different topologies of current
mode logic circuits are analyzed and compared using power, delay, and PDP. It is
simulated using Cadence Virtuoso 45 nm technology with a temperature of 27 °C
and a voltage of 1 V. The results are also verified with Monte Carlo simulation using
a histogram plot of 200 samples. From the comparison result, it proves that dynamic
topology achieves higher performance compared to others.
The following section is arranged as: Sect. 2 represents the conventional archi-
tecture of different CML topologies. Section 3 discusses the comparison of different
simulation results and their performance, and finally, Sect. 4 describes the conclusion.

2 Different CML Topologies

Current Mode Logic (CML) circuits are generally designed around differential ampli-
fiers with a pair of source coupled transistors acting as pulldown networks. According
to the fundamental idea of CML, current from a constant current generator is switched
between two different routes based on logical values. CML circuits operate quickly
primarily because of lower swing voltage.

2.1 MOS Current Mode Logic (MCML) Gates

The traditional MCML structure is shown in Fig. 1 [11]. Transistors M 2 and M 3 act as
a pulldown network, a constant source current is applied via V bias through transistor
M 1 and the load circuit M 4 and M5. The logic function is performed by the transistors
M 2 and M 3 . The inputs for M 2 and M 3 are differential, so the system requires both
the logical input and its inverse. The pulldown network, which is made up of NMOS
transistors (M 2 and M 3 ), carries out the Boolean function of the gate. Depending
on the logical operation carried out, this network directs more current to one or the
other of the two output branches, resulting in a lower voltage on one side than the
other. Although in reality, this source is an NMOS transistor that is functioning in
Performance Comparison of MCML, PFSCL, and Dynamic CML Gates … 453

(a) (b)

Fig. 1 MCML inverter logic [11]: a traditional MCML logic gate, b MCML gate with PMOS load

the saturation region, the current source for an ideal gate will be considered as ideal.
This source offers a bias current, I B , that is constant.
Load resistance RL determines swing voltage. Since the current is present in
both paths of the device, each resistance should be adjusted to provide an equal
voltage swing on either side of the device. The load resistance and the biasing current
source are the only factors that affect the swing voltage, which is often hundreds of
millivolts lower than V dd . The load resistors are frequently implemented as active
devices in the form of PMOS transistors that operate in the linear region, providing
a voltage-controlled resistance.
The voltage swing is determined by the load circuit, RL , and current source I ss .
The MCML relies on current steering to function. The overall swing voltage [12] is,

Vswing = RL × Iss (1)

The voltage gain Av is calculated as

Av = gm1 RL (2)

where gm1 is the transconductance of transistor M 2 and RL is the load resistance.

In Fig. 1b, the load resistors are replaced by PMOS load. As compared to the
passive resistance RL, the PMOS consumes minimum area but it varies from the
linear characteristics at higher speeds [13].
According to the BSIM3v3 model, the PMOS resistance Rp is,

Rint
RP = (3)
1− RDS
Rint
454 M. Sivasakthi and P. Radhika

[ ]
wp ( I I) −1
Rint = µeff,p Cox VDD − IVT,P I (4)
Lp

Because of the constant current source used in MCML circuits, static power
dissipation may be high. Therefore, to minimize that, DyCML circuits are preferred.

2.2 Dynamic Current Mode Logic (DyCML) Gates

The DyCML uses the CLK signal to reduce static dissipation and other drawbacks.
Dynamic CML has a high switching speed because of capacitance arrangement.
For this, a CLK signal with full swing is employed. The circuit must exhibit a
precharge phase for low CLK signal values, which means the load capacitance must
be precharged to V DD and gate inputs must not have changed the voltage level at the
output node. As an alternative, with high CLK values, the gate is evaluated according
to the inputs while the output capacitance is disconnected from the power supply.
To achieve this, the PMOS load transistors (M 1 , M 2 ), which are now referred to as
precharge transistors, are driven by CLK.
The load resistors in MCML are replaced by the active loads to minimize dissi-
pation of power. Figure 2 depicts the structure of Dynamic CML. Figure 2c consists
of an MCML block, a precharge circuit, a dynamic current source, and latches. For
evaluating logic functions, the MCML block is used, and the transistors M 5 , M 6, and
M 2 act as a pre charge circuit.
During the low clock phase, the precharge transistors become ON and M 1 becomes
OFF, and the output nodes are charged to V dd by the transistors M 5 , M 6 , and M 2
discharge C 1 to the ground. When CLK is high, transistors M 5 , M 6 , and M 2 becomes

(a) (b) (c)

Fig. 2 Dynamic CML logic gate [11]: a DyCML-NN gate, b DyCML-NP gate, c dynamic CML
inverter
Performance Comparison of MCML, PFSCL, and Dynamic CML Gates … 455

OFF and M1 becomes ON which forms the current route between precharged output
nodes and the capacitor C1 . At the time of evaluation, if any one of the outputs
becomes lower than Vdd − |V tp |, it will turn on the transistor that is connected at that
node, and hence it charges another node to V dd again.
As a result of the construction between C L and C 1 based on the inputs, the logic
function is assessed during the evaluation phase. The output node potential decreases
because of charge transfer from C L to C 1 . The charge transfer continues until the
potential of both capacitors is equal. Therefore, it is important to make sure that
charge transfer only stops when V swing reduces the output node’s potential. This
can be achieved by sizing capacitor C 1 appropriately. With the usage of the charge
conservation principle [14],
( )
VDD COUT = (C1 + Cout ) VDD − Vswing (5)

where C out is the sum of load capacitance C L . C 1 can be written as,

Vswing Cout
C1 = (6)
VDD − Vswing

In Dynamic CML inverter, the transistor pairings M 1 and M 2 never switch ON

simultaneously, because a direct link between the source and ground is not estab-
lished. This is due to differential signal driving these transistors. As a result, the static
power is quite small, but because these gates include capacitors, they need dynamic
power. The power consumption of Dynamic CML inverter is given as,

Pdyn = Cout VDD Vswing f clk + PCMOS_ inv (7)

where f clk is the clock frequency and PCMOS _inv is the CMOS inverter power
consumption [15].

2.3 Positive Feedback Source Coupled Logic (PFSCL) Gates

The PFSCL inverter structure is shown in Fig. 3. Transistor M 1 for biasing and
transistors M 2 and M 3 form a pair of nMOS transistors. Positive feedback is applied
from the output terminal to the M 3 gate terminal. The operation of the PFSCL is
similar to that of the MCML with the same swing voltage and the linear resistance
Rp as in Eqs. (1) and (2). Because of the feedback, the mid-swing voltage gain [12]
is,

gm1 Rp /2
Av = (8)
1 − gm1 Rp /2

Noise margin NM is,

456 M. Sivasakthi and P. Radhika

(a) (b)

Fig. 3 PFSCL logic gate [11]: a N-input PFSCL gate, b PFSCL inverter

( )
Vswing 1
NM = 1− (9)
2 Av

Signal lines in digital multiplexers are used in order to direct the data. Demul-
tiplexers work in conjunction with multiplexers to improve the communication
of concurrent data. This can be utilized in the multimedia streams and wireless
communication [16].

3 Simulation Results of MCML, Dynamic CML,

and PFSCL Gates

The performance of MCML, Dynamic CML, and PFSCL inverters are verified using
the simulation environment as mentioned in Table 1.

Table 1 Simulation
CMOS technology 45 nm
environment
Supply voltage 1V
Process corner TT, FF, SS, SF, FS
Load capacitance 10 fF
Source current 100 µA
Temperature 27 °C
Operating frequency 50 Hz
Performance Comparison of MCML, PFSCL, and Dynamic CML Gates … 457

Fig. 4 Simulation waveform of MCML inverter logic

Fig. 5 Simulation waveform of PFSCL inverter logic

3.1 Output Waveform of MCML, PFSCL, and Dynamic CML

The output waveform for the MCML inverter topology using Cadence Virtuoso is
shown in Fig. 4. The differential inputs applied in the pulldown network performs the
Boolean function. Depending on the logical operation, it produces the output. One
end of the transistor produces inverted output and its differential end produces buffer
output. The average power consumed by the MCML circuit is 21.75 µW, PFSCL is
24.35 µW and for Dynamic CML is 0.054 µW.
The output waveforms of PFSCL and Dynamic CML is shown in Figs. 5 and 6,
respectively, along with the average power values.
Table 2 compares the power, propagation delay, and power delay product values
for the MCML, PFSCL, and Dynamic CML for different process corners.

3.2 Monte Carlo Analysis

In Monte Carlo, 200 samples of random statistical variations are analyzed. The
histogram plot in Fig. 7 reveals that the average power value, which is mentioned
458 M. Sivasakthi and P. Radhika

Fig. 6 Simulation waveform of dynamic CML inverter logic

Table 2 Comparison of Simulation results with different process corners

Parameter Different topology Different process corners
of CML TT FF SS FS SF
Power (µW) MCML 21.75 29.1 14.68 23.7 17.93
PFSCL 24.35 32.72 16.47 26.79 20.52
DyCML 0.054 0.059 0.049 0.055 0.053
Propagation MCML 360.7 281.7 407.9 357.9 380.9
delay (ps) PFSCL 446.5 385.6 530.1 421.3 487.6
DyCML 20.4 1.75 45.36 10.81 30.8
Power delay MCML 7.85 8.19 5.98 8.48 6.82
product (fJ) PFSCL 10.87 12.61 8.73 11.28 10.1
DyCML 1.10 0.10 2.22 0.59 1.63

in Table. 2, is nearer to the mean value. The histogram plot represents the average
values of power and propagation delay.

3.3 Parametric Analysis

The parametric analysis with different temperatures is analyzed using the Cadence
Virtuoso tool and the corresponding average delay values for different topologies are
compared in Table 3.

3.3.1 Simulation Results Using Parametric Analysis with Temperature

The parametric analysis is performed with different temperatures as shown in Fig. 8.

The simulation results of input voltage with 1 V and its corresponding output results
Performance Comparison of MCML, PFSCL, and Dynamic CML Gates … 459

(a) (b)

(c) (d)

(e) (f)

Fig. 7 Histogram plot of Monte Carlo simulation for the inverter logic: a MCML power, b MCML
propagation delay, c PFSCL power, d PFSCL propagation delay, e dynamic CML power, f dynamic
CML propagation delay

with different temperatures as mentioned in Table 3, along with the propagation delay
and average power waveform for MCML, PFSCL, and Dynamic CML, respectively.
These results reveal that CML topology can be performed in various temperatures
with less propagation delay.
460 M. Sivasakthi and P. Radhika

Table 3 Comparison of propagation delay with different temperatures

S. No. Temperature (°C) Propagation delay (ps)
MCML PFSCL Dynamic CML
1 0 353 437 1.4
2 25 358 445 20.8
3 50 363 454 47.4
4 75 372 462 74.6
5 100 378 468 97.8

3.4 Overall Performance Comparison of MCML, DyCML,

and PFSCL

The overall performance comparison of different CML topologies are verified with
different process corners. Figure 9 shows the overall comparison of various process
corners Vs power, propagation delay, and power delay product.
This graph is plotted based on the values in Table 2. In this, the power values of
MCML, PFSCL, and Dynamic CML are measured in µW, propagation delay in ps,
and power delay product in fJ. Among these, the comparison graph shows clearly the
dynamic CML can achieve more performance with reduced power and delay values
as compared to the other topologies.

4 Conclusion

In this survey, the performance comparison of different CML topologies, namely

MCML, PFSCL, and DyCML, have been analyzed using the Cadence Virtuoso tool.
The simulation results are achieved with different process corners. The results of
power and propagation delay are verified with Monte Carlo simulations using a
histogram plot of 200 samples. The parametric analysis has been performed with
different temperatures, and the corresponding delay values are analyzed. The simu-
lation results reveal that Dynamic CML achieves greater performance in terms of
power and delay than MCML and PFSCL, but it is quite complex to design. In future,
current mode logic can be used to achieve better performance in high-speed appli-
cations. It is also used to achieve less switching noise in mixed-signal circuit design
such as optical communication and signal processing.
Performance Comparison of MCML, PFSCL, and Dynamic CML Gates … 461

(a)

(b)

(c)

Fig. 8 Parametric analysis of temperature with delay and power waveforms: a MCML temperature
versus delay, b PFSCL temperature versus delay, c DyCML temperature versus delay
462 M. Sivasakthi and P. Radhika

(a) (b)

(c)

Fig. 9 Overall performance comparison with different process corners versus a power, b propaga-
tion delay, c power delay product

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