Chapter 4 IC Design & Low Power techniques
Dr. Mohamed Abdel- Hamid
Electronics & Communications Engineering Department
Types of Digital IC Designs
Digital designs can be one of three groups: Full Custom Every transistor designed and laid out by hand ASIC (Application-Specific Integrated Circuits) Designs synthesized automatically from a high-level description language Semi-Custom Mixture of custom and synthesized modules
Technology Trends
Digital Design Cycle
How Chips are Designed
Electronic Design Automation (EDA) Design Tools
Modern chips are far too complex to design manually Now, EDA design tools are used.
Schematic Capture
Schematics are drawn on a computer screen using schematic-capture software. With this, you can drag and drop symbols for various electrical components (adders, resistors, etc.) across your screen and then connect them by drawing wires between them.
Hardware Synthesis
Engineers have turned to a new method, called hardware synthesis. Engineers feed their computers instructions about the chip's organization and the computer generates the detailed circuit designs. The engineer still has to design the chip, just not at such a detailed level. It's like the difference between describing a brick wall, brick by brick and inch by inch, or telling an assistant, "Build me a brick wall that's three feet high by 10 feet long." Hardware-Description Languages Hardware-description languages (HDLs), the next step up the evolutionary ladder from schematic-capture programs. HDLs also enable hardware synthesis. Using an HDL, engineering teams can design the behavior of a circuit without exactly designing the circuit itself in detail. The HDL tool will translate the engineers' wishes. The HDL Leaders: VHDL and Verilog, The two most common HDLs are called VHDL and Verilog. Practically all new chips are designed using one of these HDLs.
Producing a Netlist
Whether engineers use schematic capture or an HDL, their input will eventually be translated into something called a netlist.
Floor Planning
After a chip's circuit design is created, it's time to start getting physical layers to fabricate a chip
Place and Route
After the chip has been floor-planned, it's time for the detail work: routing all the tiny wires that connect the chip's various parts
If you don't solve it after the first few days, don't feel too bad. The task has been mathematically proven to be impossible.
Now imagine the same puzzle with 1 million houses and 1 million utilities
Verifying the Design Works
Now, after Verifying the Design, it would normally be ready to send to the foundry for manufacturing. The cost of tooling up a foundry to make a new chip is so expensive (in the neighborhood of $500,000)
Using Outside IP
One of the quickest ways to design a new chip is to not design it at all. Most big new chips include a fair amount of reused, borrowed, licensed, or recycled circuitry; not physically recycled silicon, of course, but recycled design ideas. In engineering circles this is called design reuse or intellectual property (IP) reuse.
General Approaches to Low Power Design
1) Lower VDD
Most attractive due to quadratic dependence of power However, tP may be increased
2) Reduce CL 3) Lower VTH to recover circuit speed
Enhances the circuit speed by Increasing gate overdrive |VGS| - |VTH|
4) Employ dual-VTH process and use lower VTH for critical circuits 5) Employ multiple supply voltage and use lower VDD for non-critical circuits 6) power can be reduced through System-on-a-chip integration (SoC)
Review of Constant Field Scaling
Parameter
Transistor Gate Transistor Source Electron Flow Transistor Drain Transistor Isolation
Value L, W, Tox Na, Nd V C I t P d P/A
Scaled Value L, W, Tox Na/, Nd/ V C I t 2P d/2 P/A
Dimensions
STI
n+
n+ STI
Conventional Silicon Substrate All Features Reduce in W idth and Thickness Shorter Distance for Electron Flow Produce Faster Transistors
Dopant concentrations Voltage Field Capacitance Current Propagation time (~CV/I) Power (VI) Density Power density
STI
n+
Electron Flow
n+ STI
Scale factor <1
Recent (180nm 65nm) Real Scaling
Parameter Dimensions Value L, W, Tox Na, Nd Scaled Value L, W, Tox 1.4 Na, 1.4 Nd
Dopant concentrations Voltage Performance Power/device Power/chip Power density
V F P P P/A
0.7 V 1.4 F 0.5 P 1P P/A
0.9 V 2.0 F 1.0 P 1.5 P 2.0 P/A
