M 24AA128/24LC128

128K I2C™CMOS Serial EEPROM

DEVICE SELECTION TABLE PACKAGE TYPE
PDIP
Part VCC Max Clock Temp
Number Range Frequency Ranges A0 1 8 Vcc
24AA128 1.8-5.5V 400 kHz† I

24xx128
A1 2 7 WP
24LC128 2.5-5.5V 400 kHz‡ I, E
†100 A2 3 6 SCL
kHz for VCC < 2.5V.
‡100 kHz for E temperature range.
Vss 4 5 SDA

FEATURES
• Low power CMOS technology SOIC
- Maximum write current 3 mA at 5.5V 1 8
A0 VCC

24xx128
- Maximum read current 400 µA at 5.5V 2 7
A1 WP
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I2C compatible A2 3 6 SCL
• Cascadable for up to eight devices VSS 4 5 SDA
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time TSSOP
A0 1 14 Vcc
• Hardware write protect for entire array
A1 2 13 WP
• Output slope control to eliminate ground bounce

24xx128
NC 3 12 NC
• Schmitt trigger inputs for noise suppression
NC 4 11 NC
• 1,000,000 erase/write cycles guaranteed
NC 5 10 NC
• Electrostatic discharge protection > 4000V
A2 6 9 SCL
• Data retention > 200 years
Vss 7 8 SDA
• 8-pin PDIP and SOIC (150 and 208 mil) packages
• 14-pin TSSOP package
• Temperature ranges:
- Industrial (I): -40°C to +85°C BLOCK DIAGRAM
- Automotive (E): -40°C to +125°C
A0…A2 WP
HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24AA128/24LC128
(24xx128*) is a 16K x 8 (128K bit) Serial Electrically I/O MEMORY
EEPROM
Erasable PROM, capable of operation across a broad CONTROL CONTROL XDEC ARRAY
LOGIC LOGIC
voltage range (1.8V to 5.5V). It has been developed for
advanced, low power applications such as personal PAGE LATCHES

communications or data acquisition. This device also

has a page-write capability of up to 64 bytes of data. I/O
SCL
This device is capable of both random and sequential YDEC
reads up to the 128K boundary. Functional address
lines allow up to eight devices on the same bus, for up SDA
to 1M bit address space. This device is available in the
standard 8-pin plastic DIP, 8-pin SOIC (150 and VCC
208 mil), and 14-pin TSSOP packages. VSS SENSE AMP
R/W CONTROL

I2C is a trademark of Philips Corporation.

*24xx128 is used in this document as a generic part number for the 24AA128/24LC128 devices.

 1998 Microchip Technology Inc. DS21191B-page 1

24AA128/24LC128
1.0 ELECTRICAL TABLE 1-1 PIN FUNCTION TABLE
CHARACTERISTICS Name Function
1.1 Maximum Ratings* A0, A1, A2 User Configurable Chip Selects
VCC.................................................................................................7.0V VSS Ground
All inputs and outputs w.r.t. VSS ............................. -0.6V to VCC +1.0V SDA Serial Data
Storage temperature ...................................................-65°C to +150°C
Ambient temp. with power applied...............................-65°C to +125°C SCL Serial Clock
Soldering temperature of leads (10 seconds) ...........................+300°C
ESD protection on all pins........................................................... ≥ 4 kV WP Write Protect Input
*Notice: Stresses above those listed under “Maximum Ratings” may VCC +1.8 to 5.5V (24AA128)
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions +2.5 to 5.5V (24LC128)
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.

TABLE 1-2 DC CHARACTERISTICS

All parameters apply across the Industrial (I): VCC = +1.8V to 5.5V Tamb = -40°C to +85°C
specified operating ranges, unless Automotive (E): VCC = +4.5V to 5.5V Tamb = -40°C to 125°C
otherwise noted.
Parameter Symbol Min Max Units Conditions
A0, A1, A2, SCL, SDA, and WP
pins:
High level input voltage VIH 0.7 VCC — V
Low level input voltage VIL — 0.3 VCC V VCC ≥ 2.5V
0.2 VCC V VCC < 2.5V
Hysteresis of Schmitt Trigger VHYS 0.05 VCC — V VCC ≥ 2.5V (Note)
inputs (SDA, SCL pins)
Low level output voltage VOL — 0.40 V IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
VIN = VSS or VCC, WP = VSS
Input leakage current ILI -10 10 µA
VIN = VSS or VCC, WP = VCC
Output leakage current ILO -10 10 µA VOUT = VSS or VCC
Pin capacitance CIN, COUT — 10 pF VCC = 5.0V (Note)
(all inputs/outputs) Tamb = 25°C, fc= 1 MHz
ICC Read — 400 µA VCC = 5.5V, SCL = 400 kHz
Operating current
ICC Write — 3 mA VCC = 5.5V
SCL = SDA = VCC = 5.5V
Standby current ICCS — 1 µA
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING DATA

TF THIGH VHYS TR

SCL
TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
SDA
THD:STA
IN TSP

TBUF
TAA
SDA
OUT

WP (protected) THD:WP
TSU:WP
(unprotected)

DS21191B-page 2  1998 Microchip Technology Inc.

 24AA128/24LC128
TABLE 1-3 AC CHARACTERISTICS
All parameters apply across the spec- Industrial (I): VCC = +1.8V to 5.5V Tamb = -40°C to +85°C
ified operating ranges unless other- Automotive (E): VCC = +4.5V to 5.5V Tamb = -40°C to 125°C
wise noted.
Parameter Symbol Min Max Units Conditions
Clock frequency FCLK — 100 kHz 4.5V ≤ VCC ≤ 5.5V (E Temp range)
— 100 1.8V ≤ VCC ≤ 2.5V
— 400 2.5V ≤ VCC ≤ 5.5V
Clock high time THIGH 4000 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
4000 — 1.8V ≤ VCC ≤ 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
Clock low time TLOW 4700 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
4700 — 1.8V ≤ VCC ≤ 2.5V
1300 — 2.5V ≤ VCC ≤ 5.5V
SDA and SCL rise time TR — 1000 ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
(Note 1) — 1000 1.8V ≤ VCC ≤ 2.5V
— 300 2.5V ≤ VCC ≤ 5.5V
SDA and SCL fall time TF — 300 ns (Note 1)
START condition hold time THD:STA 4000 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
4000 — 1.8V ≤ VCC ≤ 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
START condition setup time TSU:STA 4700 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
4700 — 1.8V ≤ VCC ≤ 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
250 — 1.8V ≤ VCC ≤ 2.5V
100 — 2.5V ≤ VCC ≤ 5.5V
STOP condition setup time TSU:STO 4000 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
4000 — 1.8V ≤ VCC ≤ 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
WP setup time TSU:WP 4000 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
4000 — 1.8V ≤ VCC ≤ 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
WP hold time THD:WP 4700 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
4700 — 1.8V ≤ VCC ≤ 2.5V
1300 — 2.5V ≤ VCC ≤ 5.5V
Output valid from clock TAA — 3500 ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
(Note 2) — 3500 1.8V ≤ VCC ≤ 2.5V
— 900 2.5V ≤ VCC ≤ 5.5V
Bus free time: Time the bus must be TBUF 4700 — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
free before a new transmission can 4700 — 1.8V ≤ VCC ≤ 2.5V
start 1300 — 2.5V ≤ VCC ≤ 5.5V
Output fall time from VIH TOF 10 250 ns CB ≤ 100 pF (Note 1)
minimum to VIL maximum
Input filter spike suppression TSP — 50 ns (Notes 1 and 3)
(SDA and SCL pins)
Write cycle time (byte or page) TWC — 5 ms
Endurance 1M — cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

 1998 Microchip Technology Inc. DS21191B-page 3

24AA128/24LC128
2.0 PIN DESCRIPTIONS 4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
2.1 A0, A1, A2 Chip Address Inputs
• Data transfer may be initiated only when the bus
The A0, A1, A2 inputs are used by the 24xx128 for is not busy.
multiple device operations. The levels on these inputs • During data transfer, the data line must remain
are compared with the corresponding bits in the slave stable whenever the clock line is HIGH. Changes
address. The chip is selected if the compare is true. in the data line while the clock line is HIGH will be
Up to eight devices may be connected to the same bus interpreted as a START or STOP condition.
by using different chip select bit combinations. If left Accordingly, the following bus conditions have been
unconnected, these inputs will be pulled down inter- defined (Figure 4-1).
nally to VSS.
4.1 Bus not Busy (A)
2.2 SDA Serial Data
Both data and clock lines remain HIGH.
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open- 4.2 Start Data Transfer (B)
drain terminal, therefore, the SDA bus requires a pullup
A HIGH to LOW transition of the SDA line while the
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
clock (SCL) is HIGH determines a START condition.
400 kHz)
All commands must be preceded by a START condi-
For normal data transfer SDA is allowed to change only tion.
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi- 4.3 Stop Data Transfer (C)
tions.
A LOW to HIGH transition of the SDA line while the
2.3 SCL Serial Clock clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
This input is used to synchronize the data transfer from
and to the device. 4.4 Data Valid (D)

2.4 WP The state of the data line represents valid data when,
after a START condition, the data line is stable for the
This pin can be connected to either VSS, VCC or left duration of the HIGH period of the clock signal.
floating. An internal pull-down resistor on this pin will
The data on the line must be changed during the LOW
keep the device in the unprotected state if left floating.
period of the clock signal. There is one bit of data per
If tied to VSS or left floating, normal memory operation
clock pulse.
is enabled (read/write the entire memory 0000-3FFF).
Each data transfer is initiated with a START condition
If tied to VCC, WRITE operations are inhibited. Read
and terminated with a STOP condition. The number of
operations are not affected.
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0 FUNCTIONAL DESCRIPTION
4.5 Acknowledge
The 24xx128 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data Each receiving device, when addressed, is obliged to
onto the bus is defined as a transmitter, and a device generate an acknowledge signal after the reception of
receiving data as a receiver. The bus must be con- each byte. The master device must generate an extra
trolled by a master device which generates the serial clock pulse which is associated with this acknowledge
clock (SCL), controls the bus access, and generates bit.
the START and STOP conditions while the 24xx128 Note: The 24xx128 does not generate any
works as a slave. Both master and slave can operate as acknowledge bits if an internal program-
a transmitter or receiver, but the master device deter- ming cycle is in progress.
mines which mode is activated.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24xx128) will leave the data line HIGH
to enable the master to generate the STOP condition.

DS21191B-page 4  1998 Microchip Technology Inc.

 24AA128/24LC128
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

FIGURE 4-2: ACKNOWLEDGE TIMING

Acknowledge
Bit

SCL 1 2 3 4 5 6 7 8 9 1 2 3

SDA Data from transmitter Data from transmitter

Transmitter must release the SDA line at this point Receiver must release the SDA line at this point
allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data.
acknowledge the previous eight bits of data.

 1998 Microchip Technology Inc. DS21191B-page 5

24AA128/24LC128
5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT
A control byte is the first byte received following the Read/Write Bit
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code; for the Chip Select
24xx128 this is set as 1010 binary for read and write Control Code Bits
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits S 1 0 1 0 A2 A1 A0 R/W ACK
allow the use of up to eight 24xx128 devices on the
same bus and are used to select which device is
Slave Address
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2, Start Bit Acknowledge Bit
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address. 5.1 Contiguous Addressing Across
The last bit of the control byte defines the operation to Multiple Devices
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is The chip select bits A2, A1, A0 can be used to expand
selected. The next two bytes received define the the contiguous address space for up to 1 Mbit by add-
address of the first data byte (Figure 5-2). Because ing up to eight 24xx128's on the same bus. In this case,
only A13…A0 are used, the upper two address bits are software can use A0 of the control byte as address bit
don’t care bits. The upper address bits are transferred A14; A1, as address bit A15; and A2, as address bit
first, followed by the less significant bits. A16. It is not possible to sequentially read across
device boundaries.
Following the start condition, the 24xx128 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24xx128 will select a read or
write operation.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE

A A A A A A A A A A A
1 0 1 0 1 0 R/W X X • • • • • •
2 13 12 11 10 9 8 7 0

CONTROL CHIP
CODE SELECT X = Don’t Care Bit
BITS

DS21191B-page 6  1998 Microchip Technology Inc.

 24AA128/24LC128
6.0 WRITE OPERATIONS 6.2 Page Write

6.1 Byte Write The write control byte, word address, and the first data
byte are transmitted to the 24xx128 in the same way as
Following the start condition from the master, the in a byte write. But instead of generating a stop condi-
control code (four bits), the chip select (three bits), and tion, the master transmits up to 63 additional bytes,
the R/W bit (which is a logic low) are clocked onto the which are temporarily stored in the on-chip page buffer
bus by the master transmitter. This indicates to the and will be written into memory after the master has
addressed slave receiver that the address high byte will transmitted a stop condition. After receipt of each word,
follow after it has generated an acknowledge bit during the six lower address pointer bits are internally
the ninth clock cycle. Therefore, the next byte incremented by one. If the master should transmit more
transmitted by the master is the high-order byte of the than 64 bytes prior to generating the stop condition, the
word address and will be written into the address address counter will roll over and the previously
pointer of the 24xx128. The next byte is the least signif- received data will be overwritten. As with the byte write
icant address byte. After receiving another acknowl- operation, once the stop condition is received, an inter-
edge signal from the 24xx128, the master device will nal write cycle will begin (Figure 6-2). If an attempt is
transmit the data word to be written into the addressed made to write to the array with the WP pin held high, the
memory location. The 24xx128 acknowledges again device will acknowledge the command but no write
and the master generates a stop condition. This ini- cycle will occur, no data will be written, and the device
tiates the internal write cycle, and, during this time, the will immediately accept a new command.
24xx128 will not generate acknowledge signals
(Figure 6-1). If an attempt is made to write to the array 6.3 Write Protection
with the WP pin held high, the device will acknowledge
The WP pin allows the user to write-protect the entire
the command but no write cycle will occur, no data will
array (0000-3FFF) when the pin is tied to VCC. If tied to
be written, and the device will immediately accept a
VSS or left floating, the write protection is disabled. The
new command. After a byte write command, the inter-
WP pin is sampled at the STOP bit for every write
nal address counter will point to the address location
command (Figure 1-1) Toggling the WP pin after the
following the one that was just written.
STOP bit will have no effect on the execution of the
write cycle.

FIGURE 6-1: BYTE WRITE

S
BUS ACTIVITY T S
MASTER A CONTROL ADDRESS ADDRESS T
R BYTE HIGH BYTE LOW BYTE DATA O
T P
SDA LINE S 1 0 1 0 A AA
2 1 0 0
X X P

A A A A
BUS ACTIVITY C C C C
K K K K
X = don’t care bit

FIGURE 6-2: PAGE WRITE

S
T S
BUS ACTIVITY A CONTROL ADDRESS ADDRESS T
MASTER R BYTE HIGH BYTE LOW BYTE DATA BYTE 0 DATA BYTE 63 O
T P
SDA LINE A A A XX P
S10 1 0 2 1 0 0
A A A A A
BUS ACTIVITY C C C C C
K K K K K
X = don’t care bit

 1998 Microchip Technology Inc. DS21191B-page 7

24AA128/24LC128
7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the stop condition for a write com-
mand has been issued from the master, the device ini- Send
tiates the internally timed write cycle. ACK polling can Write Command
be initiated immediately. This involves the master
sending a start condition, followed by the control byte
for a write command (R/W = 0). If the device is still busy Send Stop
with the write cycle, then no ACK will be returned. If no Condition to
ACK is returned, then the start bit and control byte must Initiate Write Cycle
be resent. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next read or write command. See Figure 7-1 for Send Start
flow diagram.

Send Control Byte

with R/W = 0

Did Device NO
Acknowledge
(ACK = 0)?
YES

Next
Operation

DS21191B-page 8  1998 Microchip Technology Inc.

 24AA128/24LC128
8.0 READ OPERATION 8.2 Random Read
Read operations are initiated in the same way as write Random read operations allow the master to access
operations with the exception that the R/W bit of the any memory location in a random manner. To perform
control byte is set to one. There are three basic types this type of read operation, first the word address must
of read operations: current address read, random read, be set. This is done by sending the word address to the
and sequential read. 24xx128 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
8.1 Current Address Read start condition following the acknowledge. This termi-
The 24xx128 contains an address counter that main- nates the write operation, but not before the internal
tains the address of the last word accessed, internally address pointer is set. Then, the master issues the
incremented by one. Therefore, if the previous read control byte again but with the R/W bit set to a one. The
access was to address n (n is any legal address), the 24xx128 will then issue an acknowledge and transmit
next current address read operation would access data the 8-bit data word. The master will not acknowledge
from address n + 1. the transfer but does generate a stop condition which
causes the 24xx128 to discontinue transmission
Upon receipt of the control byte with R/W bit set to one, (Figure 8-2). After a random read command, the inter-
the 24xx128 issues an acknowledge and transmits the nal address counter will point to the address location
8-bit data word. The master will not acknowledge the following the one that was just read.
transfer but does generate a stop condition and the
24xx128 discontinues transmission (Figure 8-1). 8.3 Sequential Read

FIGURE 8-1: CURRENT ADDRESS READ Sequential reads are initiated in the same way as a ran-
dom read except that after the 24xx128 transmits the
S
T S first data byte, the master issues an acknowledge as
BUS ACTIVITY A CONTROL DATA T
MASTER opposed to the stop condition used in a random read.
R BYTE BYTE O
T P This acknowledge directs the 24xx128 to transmit the
SDA LINE S 1 0 1 0 A AA 1 P
next sequentially addressed 8-bit word (Figure 8-3).
2 1 0 Following the final byte transmitted to the master, the
A N
BUS ACTIVITY C O
master will NOT generate an acknowledge but will gen-
K
A
erate a stop condition. To provide sequential reads, the
C 24xx128 contains an internal address pointer which is
K incremented by one at the completion of each opera-
tion. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will automatically roll over from
address 3FFF to address 0000 if the master acknowl-
edges the byte received from the array address 3FFF.

FIGURE 8-2: RANDOM READ

S S
BUS ACTIVITY T T S
MASTER A CONTROL ADDRESS ADDRESS A CONTROL DATA T
R BYTE HIGH BYTE LOW BYTE R BYTE BYTE O
T T P
SDA LINE S1 0 1 0 AAA0 XX S 1 0 1 0 A A A1 P
2 1 0 2 1 0
A A A A N
BUS ACTIVITY C C C C O
K K K K A
C
X = Don’t Care Bit K

FIGURE 8-3: SEQUENTIAL READ

S
BUS ACTIVITY CONTROL T
MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X O
P

SDA LINE P
A A A A N
C C C C O
BUS ACTIVITY K K K K A
C
K

 1998 Microchip Technology Inc. DS21191B-page 9

24AA128/24LC128
NOTES:

DS21191B-page 10  1998 Microchip Technology Inc.

 24AA128/24LC128
24xx128 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24xx128 — /P
P = Plastic DIP (300 mil Body), 8-lead
SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead
Package: SN = Plastic SOIC (150 mil Body), 8-lead
ST = TSSOP, 14-lead
Temperature I = -40°C to +85°C
Range: E = -40°C to +125°C

24AA128 128K bit 1.8V I2C Serial EEPROM

24AA128T 128K bit 1.8V I2C Serial EEPROM (Tape and Reel)
Device:
24LC128 128K bit 2.5V I2C Serial EEPROM
24LC128T 128K bit 2.5V I2C Serial EEPROM (Tape and Reel)

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

 1998 Microchip Technology Inc. DS21191B-page 11

M
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Dallas, TX 75240-8809
Tel: 972-991-7177 Fax: 972-991-8588 Singapore
Microchip Technology Taiwan
JAPAN
Dayton Microchip Technology Intl. Inc.
Singapore Branch
Microchip Technology Inc. Benex S-1 6F
200 Middle Road
Two Prestige Place, Suite 150 3-18-20, Shinyokohama
#07-02 Prime Centre
Miamisburg, OH 45342 Kohoku-Ku, Yokohama-shi
Singapore 188980
Tel: 937-291-1654 Fax: 937-291-9175 Kanagawa 222 Japan
Tel: 65-334-8870 Fax: 65-334-8850
Los Angeles Taiwan, R.O.C
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Microchip Technology Inc.
Microchip Technology Taiwan 12/30/97
18201 Von Karman, Suite 1090
10F-1C 207
Irvine, CA 92612
Tung Hua North Road
Tel: 714-263-1888 Fax: 714-263-1338
Taipei, Taiwan, ROC
New York Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253

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DS21191B-page 12  1998 Microchip Technology Inc.